JP2008047278A - Memory device using selective self-boosted programming operation and its programming method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To apply selectively different self-boosting techniques to a string of serially connected memory cells in response to a programming voltage applied to the selected word line, in a flash memory device. <P>SOLUTION: Non-local self-boosting and local self-boosting are selectively applied in response to the programming voltage applied to the selected word line. For example, the non-local self-boosting and the local self-boosting are selectively applied in response to the first string of serially connected cells in response to the programming voltage during an incremental step pulse programming operation. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a flash memory device and an operating method thereof, and more particularly, to a program for a flash memory device.

  Flash memory devices are used for data storage devices in various fields such as electronic devices. For example, the flash memory device is used in a computer memory card, a storage device (such as a USB memory key) using a semiconductor, a digital camera, a media playback device, and a mobile phone. A common form of flash memory is a column of floating gate transistor devices configured to be connected to their respective bit lines, and a row of control gates connected in parallel to a common word line. Therefore, it is called a NAND flash memory.

  The operations performed in such devices generally include programming, erasing and reading operations. The programming of a floating gate transistor cell of a flash memory device generally involves applying a first positive voltage to the drain region of the cell relative to the source region and a second positive voltage greater than the first positive voltage to the control gate of the device. This is done by applying a positive voltage. In the absence of electrons stored in the floating gate, such a bias condition causes the formation of an inverse hierarchical channel on the surface of the substrate between the source and drain. The drain-source voltage gains sufficiently large kinetic energy to accelerate electrons, usually called “hot” electrons, through the channel to the drain region. Also, the greater positive bias of the control gate creates an electric field in the tunneling oxide layer that separates the floating gate from the channel region. The electric field draws hot electrons and accelerates them toward a floating gate disposed between the control gate and the channel region by a process called tunneling. Thereafter, the floating gate accumulates charges and restrains the accumulated charges.

  Accumulating a large amount of bound charges (electrons) in the floating gate causes an increase in the effective threshold voltage of the transistor. If the threshold voltage rise is large enough, the transistor should maintain a non-conductive “off” state when a predetermined read voltage is applied to the control gate during a read operation. In this state, known in the programmed state, the cell stores a logic “0”. Once programmed, the device typically maintains a high threshold voltage even if power is interrupted or shut off for a long period of time.

  In cell reading, a predetermined read voltage is usually applied to the control gate via a word line that connects each cell row, and a positive voltage is usually applied to the drain region via a bit line that connects each cell column. This is done by applying to. If the cell is programmed, no drain current will flow. However, if the cell is not programmed (or erased), drain current should flow. In such a state, the cell is said to store a logic “1”. Therefore, by monitoring the bit line current, the state of the cell can be determined.

  The cell is erased by removing the charge stored in the floating gate. For example, the erase operation can be performed by grounding the control gate and applying a positive voltage (for example, 10 to 20 volts) to the substrate. Generally, in a flash memory device, a large number of cells are erased at once.

  As described above, in the NAND flash memory device, a number of columns including strings in which cells are connected in series are arranged. In order to program the cells in the NAND string, the bit line connected to the string is grounded. The select transistor that connects the string to the bit line is then turned on and the unprogrammed cell in the string has a sufficient pass voltage (e.g., 10 volts) to operate the cell without causing tunneling. It is activated by applying it to the word line. When a higher program voltage (e.g., 18 volts) is applied to the word line of the cell being programmed, tunneling occurs between the cell channel and the floating gate.

  In ISPP techniques, the program voltage applied to the control gate of the cell being programmed increases gradually until the cell threshold voltage reaches the required level. In particular, after the program voltage is applied as the first level, the threshold voltage of the programmed cell is checked (read) to determine whether the cell has been programmed correctly. If verification fails, the program voltage increases and verification is performed again. The program voltage is increased stepwise in the manner described above until the required threshold voltage is achieved. In the above method, cell overprogramming is reduced or avoided.

  In a NAND flash memory device, the word line of the cell being programmed is also connected to cells of other strings. In general, the other cells are biased such that incorrect programming is reduced or eliminated. In particular, to increase the channel potential, i.e., to reduce the voltage difference between the channel and the gate electrode when a program voltage is applied to the control gate, a voltage is applied to the above-described anti-programmed cell. The

  In order to further reduce the possibility of incorrect programming, techniques have been developed to increase the channel voltage of program-inhibited cells. In the “self-boost” technique, unselected strings of cells are first connected to a power supply voltage via a string select transistor and a bit line, and the channel is raised to the power supply voltage. Thus, the string select transistor is turned off and the precharged channel is floated. Thereafter, when a program voltage is applied to a selected cell and a program-inhibited cell of an unselected string that shares the same word line, the channel voltage of the program-inhibited cell increases. This prevents the voltage between the control gate and the channel from becoming large enough to maintain a tunnel ring between the channel and the floating gate electrode of the program-inhibited cell.

  A potential problem with the self-boost technique as described above occurs when a cell connected to a cell that has been inhibited from programming has already been programmed. As described above, programming typically raises the threshold voltage of the cell transistor. Therefore, when the above-described self-boost technique is used, when a program voltage is applied to the control gate of a program-prohibited cell, the channel voltage of the program-prohibited cell connected to the already programmed cell is not programmed. It is much lower than the cell channel voltage. This causes a much larger voltage between the channel of the control gate and the program-inhibited cell, to the extent that tunneling can occur between the channel and the floating gate of the program-inhibited cell. Thus, incorrect programming of the program-prohibited cell occurs, a phenomenon known as program disruption.

A technique for reducing the possibility of program disruption is called “local self-boost”. In this technique, after applying the pass voltage and before applying the program voltage, a low voltage (eg, 0 volts) is applied to the control gate of the cell adjacent to the program inhibited cell, and the channel of the already programmed cell is The cell's channel in the string is separated from the program inhibited cello after being precharged. This allows the channel voltage of the prohibited cell to increase independently of the threshold voltage of the already programmed cell when the program voltage is applied, thus the control gate and the channel of the prohibited cell Limit the voltage between. However, a potential problem with these techniques is that they require additional time for the sequential application of the pass voltage and isolation voltage, which increases the programming time. The self-boost technique is described in the following Patent Document 1 and the like, and the technique using the local self-boost is described in the following Patent Document 2 and Patent Document 3.
US Pat. No. 5,677,873 US Pat. No. 5,715,194 US Pat. No. 6,061,270

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a flash memory device and a program method thereof that can minimize program disturb and reduce program time.

  The exemplary embodiments of the present invention select a different self-boost technique for serially connected memory cells in a method of operating a flash memory device in response to a program voltage applied to a selected word line. A method is provided that includes the step of applying automatically.

  In an exemplary embodiment, selectively applying different self-boost techniques to series-connected memory cells in response to a program voltage applied to the selected word line comprises selecting the selected Selectively applying non-local self-boost and local self-boost in response to the programming voltage applied to a word line.

  In an exemplary embodiment, the step of selectively applying the non-local self-boost and the local self-boost is in an incremental step pulse programming (ISPP) period of a selected cell of a second string of cells connected in series. Selectively applying a non-local self boost and a local self boost to the first string of cells connected in series in response to the programming voltage.

  In an exemplary embodiment, the incremental step pulse programming (ISPP) includes changing the programming voltage in response to a test of a threshold voltage of the selected cell.

  In an exemplary embodiment, the method for selectively applying the non-local self-boost and the local self-boost includes: changing the programming voltage; and responding to the change in the programming voltage; Selectively applying a local self-boost to the string.

  In an exemplary embodiment, the string of serially connected cells includes a first string of serially connected cells, and the step of changing the programming voltage comprises selecting a selected cell of a second string of serially connected cells. In response to the threshold voltage test, the programming voltage is changed stepwise.

  In an exemplary embodiment, the method further includes detecting a program failure in response to multiple programming voltage changes that have reached a predetermined number of times.

  According to another exemplary embodiment of the present invention, in a method of operating a flash memory device including a string of memory cells configured to be connected in series between a bit line and a source line, the bit line and the program A pass voltage is applied to a word line that controls an upstream cell coupled between the prohibited cells and a word line that controls a downstream cell coupled between the source line and the prohibited program cell. Applying a first level programming voltage to selected word lines that control the programmed cells, and then applying a pass voltage to the word lines controlling the upstream cells, A word line that controls any one of the downstream cells During the application of the separation voltage, the method comprising the steps of applying the programming voltage of the first level is different from the second level to the selected word line.

  In an exemplary embodiment, while applying a pass voltage to the word line controlling the upstream cell and applying a separation voltage to the word line controlling any one of the downstream cells, the Applying the programming voltage of a second level different from the first level to the selected word line selected comprises changing the programming voltage from the first level to the second level; Responsive to determining whether a level meets a predetermined criterion, the pass voltage is applied to the word line that controls the upstream cell to control any one of the downstream cells. The second level of the programming voltage is selected while the isolation voltage is applied to the word line to be selected. And a step to be applied to the word line has.

  In an exemplary embodiment, the predetermined criterion includes a voltage threshold criterion.

  In an exemplary embodiment, while applying a pass voltage to the word line controlling the upstream cell and applying a separation voltage to the word line controlling any one of the downstream cells, the Applying the programming voltage at a second level different from the first level to the selected word line selected includes applying a pass voltage to the word line that controls the upstream cell during the first level. Applying a second level of the programming voltage to the selected word line and applying a separation voltage to the word line controlling the first downstream cell immediately after downstream of the inhibited cell. And the word line controlling the second downstream cell And a step of applying an overvoltage.

  In an exemplary embodiment, while applying a pass voltage to the word line controlling the upstream cell and applying a separation voltage to the word line controlling any one of the downstream cells, the Applying the programming voltage at a second level different from the first level to the selected word line selected includes applying a pass voltage to the word line that controls the upstream cell during the first level. Applying a second level of the programming voltage to the selected word line and applying a separation voltage to the word line controlling the first downstream cell immediately after downstream of the inhibited cell. And the word line controlling the second downstream cell Including overvoltage, and a programming voltage and applying a voltage other than the separation voltage.

  In an exemplary embodiment, a word line that controls an upstream cell coupled between the bit line and the program inhibited cell, and a source line coupled between the source line and the program inhibited cell. Applying a first level programming voltage to a selected word line that controls a program-inhibited cell while applying a pass voltage to a word line that controls a downstream cell comprises the programming of the first level. Generating a voltage; comparing the first level to a programming voltage threshold; and a word line that controls an upstream cell coupled between the bit line and the program inhibited cell; and Source line and the program A first level programming voltage is applied to the selected word line that controls the program inhibited cell while a pass voltage is applied to the word line that controls the downstream cell coupled between the stopped cells. Applying a channel bias voltage to the bit line while applying the first level of the programming voltage to the selected word line; and responding to the first level voltage less than the programming voltage threshold. Applying the pass voltage to the word line controlling the upstream and downstream cells, applying a pass voltage to the word line controlling the upstream cell, To the word line that controls any one of Applying a programming voltage at a second level different from the first level to the selected word line while applying a voltage comprises performing a threshold voltage test on a selected cell of a second string of cells connected in series. In response to determining whether a threshold voltage of the selected cell has failed to meet a transistor threshold voltage reference, changing the programming voltage to the second level; A word line that is performed by comparing the second level with the programming voltage threshold, applies a pass voltage to the word line that controls the upstream cell, and controls any one of the downstream cells. The programming voltage at a second level different from the first level while applying a separation voltage to Applying the second level of the programming voltage to the selected word line while applying the pass voltage to the word line that controls the upstream cell. And applying the isolation voltage to the word line that controls any one of the downstream cells in response to the second level being greater than the programming voltage threshold.

  In an exemplary embodiment, the method further includes confirming a program fail in response to multiple changes in the applied programming voltage while programming the selected cell that has reached a predetermined number of times. .

  Yet another exemplary embodiment of the present invention provides a plurality of strings of serially connected memory cells sharing a word line and the plurality of strings in response to a programming voltage applied to a selected word line. A flash memory device is provided that includes a program circuit configured to selectively apply a different self-boost technique to the prohibited strings.

  In an exemplary embodiment, the programming circuit is configured to selectively apply non-local self boost and local self boost in response to the programming voltage applied to the selected word line. .

  In an exemplary embodiment, the programming circuit performs incremental step pulse programming (ISPP) and in response to the programming voltage during ISPP to a selected cell of a second string of cells connected in series. The non-local self boost and the local self boost are selectively applied to the first string of memory cells connected in series.

  In an exemplary embodiment, the programming circuit is configured to change the programming voltage in response to testing a threshold voltage of the selected cell.

  In an exemplary embodiment, the program circuit is configured to confirm a program fail in response to multiple changes in the programming voltage that have reached a predetermined number of times.

  In an exemplary embodiment, the programming circuit changes the programming voltage and causes the string to selectively apply non-local self boost and local self boost in response to changing the programming voltage. Configured.

  In an exemplary embodiment, the programming circuit is configured to change the programming voltage in steps in response to a threshold voltage test of a selected cell.

  In an exemplary embodiment, the programming circuit generates a programming voltage, a pass voltage, and an isolation voltage, and a word line voltage generator configured to change the programming voltage in response to a programming voltage control signal And a programming voltage, the pass voltage, and the isolation voltage are selectively applied to the word lines of a plurality of strings connected in series in response to a selection control signal. And a selector circuit configured to, and a control circuit configured to generate the programming voltage control signal and the selection control signal.

  In an exemplary embodiment, the plurality of strings are arranged like a block of memory cells of a plurality of blocks of memory cells of the memory device, and the selector circuit includes the programming voltage, the pass voltage, and the A first decoder circuit configured to input a separation voltage and selectively pass the programming voltage, the passing voltage, and the separation voltage through a plurality of intermediate word lines in response to the selection control signal; And a second decoder circuit coupled to the intermediate word line and configured to couple the intermediate word line to the word lines of the plurality of strings in response to a block address signal.

  In an exemplary embodiment, the first decoder circuit is configured to generate a string selection and ground selection signal in response to a page address signal.

  Yet another exemplary embodiment of the present invention includes a plurality of strings of serially connected memory cells sharing a word line and an upstream cell coupled between the bit line and the program inhibited cell. Selected to control the prohibited cell while applying a pass voltage to the controlling word line and the word line controlling the downstream cell coupled between the source line and the prohibited cell. A first level programming voltage is applied to the word line, a pass voltage is applied to the word line controlling the upstream cell, and a separation voltage is applied to the word line controlling any one of the downstream cells. The second level of programming different from the first level while applying And a programming circuit configured to apply a pressure to the selected word line, wherein each string of the memory cells is configured to be connected in series between a bit line and a source line. Providing equipment.

  In an exemplary embodiment, the program circuit is responsive to changing the programming voltage from the first level to the second level and determining the second level to satisfy a predetermined criterion. And applying the second level of the programming voltage to the selected word line while applying the pass voltage to the word line controlling the upstream cell, and selecting one of the downstream cells. The isolation voltage is applied to a word line that controls one.

  In an exemplary embodiment, the predetermined criterion includes a voltage threshold criterion.

  In an exemplary embodiment, the program circuit includes a word line that controls an upstream cell coupled between the bit line and the program-inhibited cell, and between the source line and the program-inhibited cell. Applying a first level programming voltage to the selected word line that controls the inhibited cell while applying a pass voltage to the word line for controlling the downstream cell coupled to the While passing voltage is applied to the word line controlling the stream cell, separation voltage is applied to the word line controlling the first downstream cell, and the passing voltage is applied to the word line controlling the second downstream cell And the second level of the program different from the first level. Configured to ring voltage to be applied to the selected word line.

  In an exemplary embodiment, the program circuit includes a word line that controls an upstream cell coupled between the bit line and the program-inhibited cell, and between the source line and the program-inhibited cell. Applying a first level programming voltage to the selected word line that controls the inhibited cell while applying a pass voltage to the word line for controlling the downstream cell coupled to the A pass voltage is applied to the word line that controls the stream cell, a separation voltage is applied to the word line that controls the first downstream cell, and a voltage other than the passage voltage, the programming voltage, and the separation voltage is applied to the second line. Applied to the word line that controls the downstream cell To, configured to apply a different second level the programming voltage to the selected word line of the first level.

  In an exemplary embodiment, the programming circuit generates a first level of the programming voltage, compares the first level to a programming voltage threshold, and compares the first level of the programming voltage to the selected word line. A channel bias voltage is applied to the bit line while the pass voltage is applied to the word line that controls the upstream and downstream cells, and a selected cell of a second string of cells connected in series In response to determining whether a threshold voltage of the selected cell did not satisfy a transistor threshold voltage criterion, changing the programming voltage to the second level, and And the programming voltage threshold are greater than the programming voltage threshold In response to the second level, the pass voltage is applied to the word line that controls the upstream cell, and the isolation voltage is applied to the word line that controls any one of the downstream cells. In the meantime, the second level of the programming voltage is configured to be applied to the selected word line.

  In an exemplary embodiment, the program circuit performs a program fail in response to multiple changes in the programming voltage applied while programming the selected memory cell that has reached a predetermined number of times. Configured to confirm.

  According to the present invention, the program disturb is minimized and the program time is reduced by selectively using the non-local self-boost method and the local self-boost method depending on whether or not the program voltage has reached the target voltage. It is possible to reduce.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  In some embodiments according to the present invention, the risk of program disruption typically increases with increasing program voltage, and the more complex and more time consuming local self-boosting is associated with lower program voltage levels. Based on the recognition that it is not necessary to reduce or eliminate program disturbance.

  Some embodiments in accordance with the present invention beneficially use incremental programming techniques such as ISPP with selective self-boost based on program voltage levels for negotiation between programming speed and risk of program disruption. To do.

  FIG. 1 shows a memory device 100 and its operation according to an embodiment of the present invention.

As shown in FIG. 1, the memory device 100 includes a NAND string of a plurality of flash memory cells and a memory cell array 30 including a row controlled by each word line WL in the string. The memory device 100 further includes a word line voltage generation circuit 10 configured to generate a number of different voltages including a program voltage V _pgm , a pass voltage V _pass , and a separation voltage V _decouple .

In response to a control input corresponding to the program voltage V _pgm generated by the control circuit 40, the selection circuit 20 selectively applies the program voltage V _pgm , the pass voltage V _pass , and the separation voltage V _decouple to the word line WL. Configured as follows.

In particular, the control circuit 40 is responsive to the level of the program voltage _{V pgm,} the program voltage _{V pgm,} pass voltage _{V pass,} configured to control the application of the separation voltage _{V decouple.} For example, in some embodiments, the word line voltage generation circuit 10 is configured to increase the program voltage V _pgm stepwise in an ISPP operation. For example, the control circuit 40 may determine, for example, a program voltage V _pgm , a pass voltage V _pass , and a separation voltage V _decouple to determine which of a number of different self-boost techniques are applied in cell programming of the array 30. Is applied to represent a non-local self-boost effect or to represent a local self-boost effect, the program voltage V _pgm is compared with one or more threshold voltages. Composed.

  FIG. 2 is a flowchart showing a preferred operation of the memory device 100 according to the embodiment of the present invention.

As shown in FIG. 2, the data and address to be programmed are input to the selected cell (block 205), and in response, the control circuit 40 initializes the loop count and the program voltage V _pgm . When the program voltage V _pgm is smaller than the target voltage V _target , the control circuit 40 causes the selection circuit 20 to apply the program voltage V _pgm and the passing voltage V _pass to the word line WL, and non-local self boost is applied. The For example, the program voltage V _pgm is applied to the word line of the selected cell while the _pass voltage V _pass is applied to all other word lines (block 225a). However, when the program voltage V _pgm is greater than the target voltage V _target , the control circuit 40 causes the selection circuit 20 to _display the program voltage V _pgm , the pass voltage V _pass , and the separation voltage V _decouple to exhibit a local self boost (block 225 b) effect. To be applied.

After application of the word line voltage, the control circuit 40 determines the threshold voltage _Vth of the selected cell (block 230). For example, the control circuit 40 performs a program verification read operation in order to determine whether the selected cell appropriately cuts off the current. If the selected cell passes the threshold voltage test, the program is complete (block 245). However, otherwise, the control circuit 40 determines whether the maximum loop count has been reached, and if the maximum loop count has been reached, the control circuit 40 confirms the program as fail (block 250). However, if the maximum loop count is not reached, the control circuit 40 increases the program voltage V _pgm , increases the loop count (block 240), and optionally performs another non-local self-boost programming operation. Alternatively, a local self-boost programming operation is performed in response to verification as described above (blocks 225a, 225b, 230).

  FIG. 3 shows a memory device 30 according to an embodiment of the present invention.

  As shown in FIG. 3, in particular, the memory device 300 is configured to perform an ISPP operation with the selective self-boost described above. The memory device 300 includes a NAND memory cell array 110 including word lines WL and bit lines BL. The bit line BL is connected to a page buffer PB circuit that exchanges data with the y-selector circuit. The page buffer PB circuit 120 and the y-selector circuit 130 are configured to transmit data between the bit line BL and the input / output line I / O. The apparatus 300 includes an x-selector circuit 160 configured to selectively drive the word line WL with the word line voltage generated by the word line voltage generation circuit 140.

Application of the word line voltage by the x-selector circuit 160 is controlled by the control circuit 190. The control circuit 190 includes a comparison circuit 180 that generates a comparison signal OK corresponding to the comparison between the program voltage V _pgm generated by the word line voltage generation circuit 140 and a predetermined threshold voltage. In response to the comparison signal OK, the control logic 150 controls the word line voltage applied to the word line WL by the x-selector circuit. The control circuit 190 is configured to generate a control input to the word line voltage generation circuit 140 such that the program voltage V _pgm gradually increases as part of the ISPP operation. The control circuit 190 is configured to instruct the control logic 150 the number of times the program voltage V _pgm is specified, for example, so that the control logic 150 can confirm the program failure.

  FIG. 4 shows the x-selector circuit 160 of the memory device 300 according to the embodiment of the present invention.

As shown in FIG. 4, the x-selector circuit 160 receives the page address PA together with the program voltage V _pgm , the passing voltage V _pass , the separation voltage V _couple and the internal voltage IVC generated by the word line voltage generation circuit 140 of FIG. A primary decoder / driver circuit 162 for receiving is included. Based on the page address PA, the word line voltage is selectively applied to the word line driving signal line Si. The first decoder / driver circuit 162 generates a voltage on the string selection drive signal line SS and the ground selection drive signal line GS based on the page address PA. The x-selector circuit 160 receives the block address BA, and in response to this, the word line drive signal line Si, the string selection drive signal line SS, and the ground selection drive signal line GS are sent to the word line WL and the string selection line of the memory array 110. A secondary decoder / driver circuit 164 connected to the SSL and ground selection line GSL is included.

  FIG. 5 shows a preferred embodiment of the first decoder / driver circuit 162 according to an embodiment of the present invention.

As shown in FIG. 5, the first decoder / driver circuit 162 includes a page address decoder circuit 162a that receives a page address and generates a decoded signal DA in response thereto. The decoded signal DA is applied to a driver circuit 162b including each driver DRV having an output connected to each of the word line drive signal lines S0 to S31. In response to the decoded signal DA and the control signals PGM_WLVPASS, PGM_WLVPGM, SLFB / LSLFB generated by the control logic 150, the driver DRV outputs the program voltage V _pgm , the pass voltage V _pass , the separation voltage V _decouple and the internal voltage IVC. It is selectively applied to the word line drive signal lines S0 to S31. In particular, the control signal PGM_WLVPASS controls the period during which the _pass voltage V _pass is applied, the control signal PGM_WLVPGM controls the period during which the program voltage V _pgm is applied, and the control signal SLFB / LSFLB is (non-local) self Controls whether boost or local self-boost is applied.

  FIG. 6 shows a preferred embodiment of the second decoder / driver circuit 164 of FIG.

  As shown in FIG. 6, the second decoder / driver circuit 164 receives the block address BA, and in response thereto, the word line driving signal lines S0 to S31, the string selection driving signal line SS, the ground selection driving signal line GS, A block address decoder circuit 164a that generates a control signal BLKWL that collectively controls a plurality of transistors WT0 to WT31, ST, and GT that respectively connect and disconnect the word lines WL0 to WL31, the string selection line SSL, and the ground selection line GSL of the memory array 110. including. As shown in FIG. 6, the string selection line SSL is connected to the string selection transistor SST, the word lines WL0 to WL31 are connected to the memory cells M0 to M31, and the ground selection line GSL is the ground selection transistor of the parallel NAND string. GST is connected to each bit line BL0 to BLm-1.

7A and 7B illustrate a preferred non-local self-boost operation performed in the memory device 300 of FIG. 3 when the program voltage V _pgm is low enough to reduce or avoid program disturb.

As shown in FIG. 7A, in the programming operation of the target cell 610, the power supply voltage _Vcc is applied to the bit line of the adjacent NAND string, and at the same time, the bit line of the NAND string including the target cell 610 is grounded. At the same time as the ground selection line GSL is grounded, the power supply voltage _Vcc is applied to the string selection line SSL. This causes the channel of the non-target string cell to be charged and then floated.

As shown in FIG. 7B, the program voltage V _pgm is applied to the selected word line WL29 of the target cell 610, while the passing voltage V _pass is applied to the other word lines W0 to W28, W30, and W31. . This includes the forbidden cell 620 connected to the selected word line WL29 and raises the channel voltage of the unselected cell string. If the program voltage V _pgm is sufficiently low, the voltage difference between the program voltage V _pgm applied to the control gate of the cell 620 that has been inhibited and the channel of the cell is sufficiently low to prevent incorrect programming.

FIGS. 8A and 8B illustrate a preferred non-local self-boost operation performed by the memory device 300 of FIG. 3 when the program voltage V _pgm is high enough to undesirably increase the likelihood of program disruption.

As shown in FIG. 8A, the power supply voltage _Vcc is applied to the bit line of the adjacent NAND string including the cell 620 in which the program is inhibited, and at the same time, the bit line of the NAND string including the target cell 610 is grounded. At the same time as the ground selection line GSL is grounded, the power supply voltage _Vcc is applied to the string selection line SSL.

As shown in FIG. 8B, first, the pass voltage V _pass is applied to all the word lines WL0 to WL31. t20 interval after the word line WL28 adjacent to the word line WL29 which is selected is grounded at t21 interval, thereafter, it is driven by a separate voltage _{V decouple.} During the upper part of the word line WL30~WL31 word line WL29 which is selected continues to be driven in the pass voltage _{V pass,} the lower portion of the word line WL0~WL27 separation word line WL28 is driven by the internal voltage IVC. In other embodiments, for example, other of the lower word lines WL0-WL27 may generally be driven with a combination of the pass voltage _Vcc , the internal voltage IVC, and / or the isolation voltage _Vdecouple. . After the time interval t22, the selected word line WL29 is driven with the program voltage V _pgm during the time interval t23. After the time interval t23, all the word lines WL0 to WL31 are grounded during the time interval t24.

  FIG. 9 illustrates how the memory device 300 uses ISPP with selective self-boost according to some embodiments of the present invention.

As shown in FIG. 9, when the program voltage V _pgm increases from the minimum level V _{pgm_min} and maintains a level lower than the target level V _target , the apparatus 300 uses an operation to which non-local self boost is applied. However, once the program voltage V _pgm exceeds the target level V _target and rises toward the maximum program voltage _{Vpgm_max} , the device 300 uses local self-boost to reduce the likelihood of program disturbance.

  It will be appreciated that the circuits and operations of FIGS. 3-9 are provided for purposes of illustration and that the present invention may be implemented in a variety of other ways. For example, in some embodiments of the invention, different non-local self-boost operations based on program voltage instead of or in addition to the selective application of non-local self-boost and local self-boost described above Alternatively, there may be a memory device configured to selectively employ different local self-boost operations. Instead of, or in addition to, the local self-boost technique described above, other forms of local self such as the local self-boost described above in US Pat. No. 5,715,194 and US Pat. No. 6,061,207. Boost can be used. In an embodiment, the selective self-boost based on the program voltage can also be used for a programming operation other than a cyclic operation such as an ISPP operation.

  The above-described preferred embodiments of the present invention are disclosed for the purpose of illustration, and those having ordinary knowledge in the technical field to which the present invention pertains depart from the technical idea of the present invention. Various substitutions, modifications, and alterations are possible within the scope of not being included, and such substitutions, alterations, and the like belong to the scope of the claims.

1 shows a memory device and its operation according to an embodiment of the present invention. 4 is a flowchart showing a preferred operation of the memory device according to the embodiment of the present invention. 1 shows a memory device according to an embodiment of the present invention. 1 shows an x-selector circuit of a memory device according to an embodiment of the present invention. 1 shows a preferred embodiment of a first decoder / driver circuit according to an embodiment of the present invention. 5 illustrates a preferred embodiment of the second decoder / driver circuit of FIG. FIG. 4 illustrates a preferred non-local self-boost operation performed in the memory device of FIG. 3 when the program voltage V _pgm is low enough to reduce or avoid program disturb. FIG. 4 illustrates a preferred non-local self-boost operation performed in the memory device of FIG. 3 when the program voltage V _pgm is low enough to reduce or avoid program disturb. FIG. 4 illustrates a preferred non-local self-boost operation performed by the memory device of FIG. 3 when the program voltage V _pgm is high enough to undesirably increase the likelihood of program disturb. FIG. 4 illustrates a preferred non-local self-boost operation performed by the memory device of FIG. 3 when the program voltage V _pgm is high enough to undesirably increase the likelihood of program disturb. Fig. 4 illustrates how a memory device uses ISPP with selective self-boost according to some embodiments of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Word line voltage generation circuit 20 Selection circuit 30 Memory cell array 40 Control circuit 100 Memory device

Claims (31)

In a method of operating a flash memory device,
Selectively applying different self-boost techniques to serially connected memory cells in response to a program voltage applied to a selected word line. Selectively applying different self-boost techniques to serially connected memory cells in response to a program voltage applied to the selected word line;
The method of claim 1, comprising selectively applying non-local self boost and local self boost in response to the programming voltage applied to the selected word line.   The step of selectively applying the non-local self boost and the local self boost is in response to the programming voltage in an incremental step pulse programming (ISPP) period of a selected cell of a second string of cells connected in series. 3. The method of claim 2, comprising selectively applying non-local self boost and local self boost to a first string of cells connected in series.   4. The method of claim 3, wherein the incremental step pulse programming (ISPP) includes changing the programming voltage in response to a test of a threshold voltage of the selected cell. The method of selectively applying the non-local self boost and the local self boost is as follows:
Changing the programming voltage;
3. The method of claim 2, comprising selectively applying a non-local self boost and a local self boost to the string in response to a change in the programming voltage.   The string of serially connected cells includes a first string of serially connected cells, and the step of changing the programming voltage is responsive to a threshold voltage test of a selected cell of a second string of serially connected cells. 6. The method of claim 5, comprising the step of changing the programming voltage stepwise.   7. The method of claim 6, further comprising detecting a program fail in response to a number of changes in the programming voltage reaching a predetermined number of times. In a method of operating a flash memory device including a string of memory cells configured to be connected in series between a bit line and a source line,
A word line for controlling an upstream cell coupled between the bit line and the program-inhibited cell, and a word line for controlling a downstream cell coupled between the source line and the program-inhibited cell. Applying a first level programming voltage to a selected word line that controls the inhibited cell while applying a pass voltage to
Next, a pass voltage is applied to the word line controlling the upstream cell, and a separation voltage is applied to the word line controlling any one of the plurality of downstream cells. Applying a second level different programming voltage to the selected word line. A second level different from the first level while applying a pass voltage to the word line controlling the upstream cell and applying a separation voltage to the word line controlling any one of the downstream cells. Applying the programming voltage to the selected word line selected from:
Changing the programming voltage from the first level to the second level;
In response to determining whether the second level meets a predetermined criterion, the pass voltage is applied to the word line that controls the upstream cell and any one of the downstream cells. 9. Applying the second level of the programming voltage to the selected word line while applying the isolation voltage to a word line that controls one.   The method of claim 9, wherein the predetermined criterion comprises a voltage threshold criterion. A second level different from the first level while applying a pass voltage to the word line controlling the upstream cell and applying a separation voltage to the word line controlling any one of the downstream cells. Applying the programming voltage to the selected word line selected from:
Applying a programming voltage of a second level different from the first level to the selected word line while applying a pass voltage to the word line controlling the upstream cell;
Applying a separation voltage to a word line controlling the first downstream cell immediately after downstream of the program inhibited cell;
Applying the pass voltage to a word line controlling a second downstream cell. A second level different from the first level while applying a pass voltage to the word line controlling the upstream cell and applying a separation voltage to the word line controlling any one of the downstream cells. Applying the programming voltage to the selected word line selected from:
Applying a programming voltage of a second level different from the first level to the selected word line while applying a pass voltage to the word line controlling the upstream cell;
Applying a separation voltage to a word line controlling the first downstream cell immediately after downstream of the program inhibited cell;
Applying the voltage other than the pass voltage, the programming voltage, and the isolation voltage to a word line that controls a second downstream cell. A word line for controlling an upstream cell coupled between the bit line and the program-inhibited cell, and a word line for controlling a downstream cell coupled between the source line and the program-inhibited cell. Applying a first level programming voltage to a selected word line that controls a program inhibited cell while applying a pass voltage to:
Generating the programming voltage of the first level;
Comparing the first level to a programming voltage threshold;
A word line for controlling an upstream cell coupled between the bit line and the program-inhibited cell, and a word line for controlling a downstream cell coupled between the source line and the program-inhibited cell. Applying a first level programming voltage to a selected word line that controls a program inhibited cell while applying a pass voltage to:
Applying a channel bias voltage to the bit line while applying the first level of the programming voltage to the selected word line;
Applying the pass-through voltage to the word line controlling the upstream and downstream cells in response to the first level voltage being less than the programming voltage threshold;
A second level different from the first level while applying a pass voltage to the word line controlling the upstream cell and applying a separation voltage to the word line controlling any one of the downstream cells. Applying the programming voltage to the selected word line comprises:
Performing a threshold voltage test on selected cells of a second string of cells connected in series;
Changing the programming voltage to the second level in response to determining whether a threshold voltage of the selected cell has failed to meet a transistor threshold voltage reference;
Comparing the second level with the programming voltage threshold;
A second level different from the first level while applying a pass voltage to the word line controlling the upstream cell and applying a separation voltage to the word line controlling any one of the downstream cells. Applying the programming voltage to the selected word line comprises:
Applying the second level of the programming voltage to the selected word line while applying the pass voltage to the word line controlling the upstream cell;
9. The method of claim 8, comprising: applying the isolation voltage to the word line that controls any one of the downstream cells in response to the second level being greater than the programming voltage threshold. .   14. The method of claim 13, further comprising verifying a program fail in response to multiple changes in the applied programming voltage while programming the selected cell that has reached a predetermined number of times. A plurality of strings of serially connected memory cells sharing a word line; and
A flash memory including a program circuit configured to selectively apply a different self-boost technique to a program-inhibited string of the plurality of strings in response to a programming voltage applied to a selected word line apparatus.   16. The flash memory of claim 15, wherein the program circuit is configured to selectively apply non-local self boost and local self boost in response to the programming voltage applied to the selected word line. apparatus.   The programming circuit performs incremental step pulse programming (ISPP) and responds to the programming voltage while performing ISPP on selected cells of a second string of serially connected cells. 17. The flash memory device according to claim 16, wherein the flash memory device is configured to selectively apply a non-local self boost and a local self boost to one string.   The flash memory device of claim 17, wherein the program circuit is configured to change the programming voltage in response to testing a threshold voltage of the selected cell.   The flash memory device of claim 17, wherein the program circuit is configured to check for a program fail in response to a number of changes in the programming voltage reaching a predetermined number of times.   17. The program circuit of claim 16, wherein the programming circuit is configured to selectively apply a non-local self boost and a local self boost to the string in response to changing the programming voltage and changing the programming voltage. The flash memory device described.   21. The flash memory device of claim 20, wherein the program circuit is configured to change the programming voltage in steps in response to a threshold voltage test of a selected cell. The program circuit includes:
A word line voltage generation circuit configured to generate a programming voltage, a pass voltage, and an isolation voltage, and to change the programming voltage in response to a programming voltage control signal;
The programming voltage, the passing voltage, and the isolation voltage are selectively applied to the word lines of a plurality of strings connected in series in response to a selection control signal. A configured selector circuit; and
The flash memory device of claim 16, comprising a control circuit configured to generate the programming voltage control signal and the selection control signal. The plurality of strings are arranged like a block of memory cells of a plurality of blocks of memory cells of the memory device;
The selector circuit is
The programming voltage, the passing voltage, and the separation voltage are input, and the programming voltage, the passing voltage, and the separation voltage are selectively passed through a plurality of intermediate word lines in response to the selection control signal. A first decoder circuit configured to:
23. A second decoder circuit coupled to the intermediate word line and configured to couple the intermediate word line to the word line of the plurality of strings in response to a block address signal. The flash memory device described.   24. The flash memory device of claim 23, wherein the first decoder circuit is configured to generate a string selection and ground selection signal in response to a page address signal. A plurality of strings of serially connected memory cells sharing a word line; and
A word line for controlling an upstream cell coupled between the bit line and the program-inhibited cell, and a word line for controlling a downstream cell coupled between the source line and the program-inhibited cell. Applying a first level programming voltage to a selected word line controlling a program inhibited cell and applying a passing voltage to the word line controlling the upstream cell. And applying a second level of the programming voltage different from the first level to the selected word line while applying an isolation voltage to the word line controlling any one of the downstream cells. And a program circuit configured in
The flash memory device is configured such that each string of the memory cells is connected in series between a bit line and a source line. The program circuit includes:
Changing the programming voltage from the first level to the second level;
In response to determining that the second level satisfies a predetermined criterion, the programming voltage of the second level while applying the pass voltage to the word line that controls the upstream cell. To the selected word line,
The flash memory device according to claim 25, wherein the isolation voltage is applied to a word line that controls any one of the downstream cells.   27. The flash memory device of claim 26, wherein the predetermined criterion includes a voltage threshold criterion. The program circuit includes:
A word line for controlling an upstream cell coupled between the bit line and the prohibited cell, and a downstream cell coupled between the source line and the prohibited cell. Applying a first level programming voltage to a selected word line that controls a program inhibited cell while applying a pass voltage to the word line;
A pass voltage is applied to the word line that controls the upstream cell, a separation voltage is applied to the word line that controls the first downstream cell, and a pass voltage is applied to the word line that controls the second downstream cell. 26. The flash memory device of claim 25, wherein the flash memory device is configured to apply the programming voltage at a second level different from the first level to the selected word line. The program circuit includes:
A word line for controlling an upstream cell coupled between the bit line and the prohibited cell, and a downstream cell coupled between the source line and the prohibited cell. Applying a first level programming voltage to a selected word line that controls a program inhibited cell while applying a pass voltage to the word line;
A pass voltage is applied to the word line that controls the upstream cell, a separation voltage is applied to the word line that controls the first downstream cell, and a voltage other than the passage voltage, the programming voltage, and the separation voltage is applied. 26. The device of claim 25, configured to apply the programming voltage at a second level different from the first level to the selected word line while applying the second downstream cell to a controlling word line. Flash memory device. The program circuit includes:
Generating a first level of the programming voltage;
Comparing the first level to a programming voltage threshold;
Applying a first level of the programming voltage to the selected word line;
Applying a channel bias voltage to the bit line while applying the pass voltage to the word line controlling the upstream and downstream cells;
Performing a threshold voltage test on selected cells of the second string of cells connected in series;
Responsive to determining whether the threshold voltage of the selected cell did not meet a transistor threshold voltage criterion, changing the programming voltage to the second level;
Comparing the second level with the programming voltage threshold;
In response to the second level being greater than the programming voltage threshold, applying the pass voltage to the word line controlling the upstream cell;
The programming voltage of the second level is applied to the selected word line while the isolation voltage is applied to the word line controlling any one of the downstream cells. Item 26. The flash memory device according to Item 25.   The program circuit is configured to verify a program fail in response to a number of changes in the programming voltage applied while programming the selected memory cell that has reached a predetermined number of times. Item 30. The flash memory device according to Item 30.

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