JP2008041767A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which includes a full silicide gate electrode comprising paladium silicide, and includes a silicide layer on a source/drain region. <P>SOLUTION: There is provided a semiconductor device having a MOS structure comprising a semiconductor substrate, a gate electrode of paladium silicide provided on the semiconductor substrate via a gate insulating film, and a source/drain region formed on the semiconductor substrate at both sides of the gate electrode. In the semiconductor device, the work function of the gate electrode becomes small by doping the gate electrode using boron as an impurity. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a MOS type semiconductor device using a full silicide gate electrode made of palladium silicide and a manufacturing method thereof.

  In the conventional CMOS integrated circuit, the work function of the gate electrode is controlled by adjusting the amount and concentration of impurities in the polycrystalline silicon using polycrystalline silicon as the gate electrode. However, as the semiconductor device becomes finer and the thickness of the gate oxide film is reduced to 2 nm or less, the thickness of the depletion layer extending into the gate electrode cannot be ignored, and the capacitance corresponding to 10% or more of the gate oxide film. There was also an increase in the number.

In order to avoid such a problem, a semiconductor device using a metal as a gate electrode instead of a polycrystalline silicon gate electrode has been proposed, but a semiconductor using a NiSi fully silicided (FUSI) gate electrode is proposed. A device is one of them (for example, see Non-Patent Document 1).
C. Cabral et al., "Dual workfunction fully silicided metal gates", VLSI Tech. Symp., Pp. 174-185, 2004

  However, when NiSi full silicide is used for the gate electrode, there is a problem that silicon is deposited or it is difficult to control the silicide phase. In addition, in the heat treatment process in which the silicon phase is silicided to form the gate electrode, the NiSi layer previously formed on the source / drain regions undergoes phase change and phase separation, and the junction leakage current increases due to contact resistance and Ni diffusion. There was also a problem of doing.

On the other hand, as a result of intensive studies, the inventors have found that these problems can be solved by employing a full silicide gate electrode using Pd ₂ Si as a material, and have completed the present invention.

  That is, an object of the present invention is to provide a semiconductor device using a full silicide gate electrode made of palladium silicide and a manufacturing method thereof.

  The present invention relates to a MOS structure including a semiconductor substrate, a palladium silicide gate electrode provided on the semiconductor substrate via a gate insulating film, and source / drain regions formed in the semiconductor substrate on both sides of the gate electrode. The semiconductor device is characterized in that the work function of the gate electrode is shifted to be small by doping the gate electrode with boron as an impurity.

  The present invention also includes a semiconductor substrate, a palladium silicide gate electrode provided on the semiconductor substrate via a gate insulating film, and source / drain regions formed in the semiconductor substrate on both sides of the gate electrode. A semiconductor device having a MOS structure, in which the work function of the gate electrode is increased by doping the gate electrode with an element selected from the group consisting of antimony, arsenic, phosphorus, and fluorine as an impurity. This is also a semiconductor device.

  The present invention also provides a step of preparing a semiconductor substrate, a step of forming a p-type well region in the semiconductor substrate, a step of forming a gate insulating film on the p-type well region and depositing a silicon layer thereon. A step of doping the silicon layer with boron as an impurity, a step of patterning the silicon layer to form a gate electrode, and p-type well regions on both sides of the gate electrode are doped with n-type ions to sandwich the gate electrode A source / drain region forming step, a first heat treatment step of forming a nickel layer on the source / drain region and forming a silicide layer made of nickel silicide by heat treatment, and a palladium layer covering the gate electrode And a second heat treatment step in which the gate electrode is made a full silicide electrode made of palladium silicide by heat treatment. Process is also a method of manufacturing a semiconductor device which comprises carrying out at a lower temperature than the first heat treatment step.

  The present invention also provides a step of preparing a semiconductor substrate, a step of forming an n-type well region in the semiconductor substrate, and a step of forming a gate insulating film on the n-type well region and depositing a silicon layer thereon. Doping the silicon layer with an element selected from the group consisting of antimony, arsenic, phosphorus, and fluorine as an impurity, patterning the silicon layer to form a gate electrode, and n-type on both sides of the gate electrode Doping p-type ions in the well region to form a source / drain region so as to sandwich the gate electrode, forming a nickel layer on the source / drain region, and forming a silicide layer made of nickel silicide by heat treatment A palladium layer is formed so as to cover the gate electrode, and the gate electrode is made of palladium silicide by the heat treatment. And a second heat treatment step of the fully silicided electrode, the second heat treatment step is also a method of manufacturing a semiconductor device which comprises carrying out at a lower temperature than the first heat treatment step.

In the semiconductor device according to the present invention, the work function of the full silicide gate electrode made of Pd ₂ Si can be adjusted while forming a good silicide layer on the source / drain regions.

  FIG. 1 is a cross-sectional view of the MOS type semiconductor device according to the present embodiment, the whole being represented by 100. The MOS semiconductor device 100 has a CMOS structure including an n-ch MOSFET 100a and a p-ch MOSFET 100b.

  The MOS type semiconductor device 100 includes a semiconductor substrate 1 made of, for example, silicon. The semiconductor substrate 1 is provided with a p-type well region 1a and an n-type well region 1b. The p-type well region 1a and the n-type well region 1b are electrically separated by an isolation region 2 made of, for example, silicon oxide. The isolation region 2 may be a trench type isolation region or a LOCOS type isolation region.

  In the p-type well region 1a, an n-type source / drain region 9a and an n-type extension region 7a are provided. A metal silicide film 11 made of, for example, NiSi is provided on the source / drain region 9a.

  A p-type well region 1a sandwiched between two extension regions 7a serves as an n-channel region, and a gate electrode 14a is provided thereon via a gate insulating film 3 made of, for example, silicon oxide. The gate electrode 14a is a full silicide (FUSI) gate electrode using palladium silicide.

  On the other hand, the n-type well region 1b is provided with a p-type source / drain region 9b and a p-type extension region 7b. A metal silicide film 11 made of, for example, NiSi is provided on the source / drain region 9b.

  An n-type well region 1b sandwiched between two extension regions 7b serves as a p-channel region, and a gate electrode 14b is provided on the n-type well region 1b with a gate insulating film 3 interposed therebetween. The gate electrode 14b is a full silicide (FUSI) gate electrode using palladium silicide.

Here, in the gate electrodes 14a and 14b made of palladium silicide (Pd ₂ Si), the Fermi level is in the vicinity of the center of the forbidden band of silicon in a state where impurities are not doped. For this reason, in the n-ch MOSFET 100a, the gate electrode 14a is doped with, for example, impurity ions such as boron (B), and the Fermi level is shifted toward the conduction band (E _C ) (to a smaller work function). Let On the other hand, in the p-ch MOSFET 100b, the gate electrode 14b is doped with impurity ions such as antimony (Sb), arsenic (As), phosphorus (P), fluorine (F), etc., and the Fermi level is changed to the valence band (E _V ) is shifted (to which the work function becomes larger). Thereby, the threshold voltages of the n-ch MOSFET 100a and the p-ch MOSFET 100b can be reduced.

FIG. 2 is a graph showing the work function modulation region when various impurity ions are doped into NiSi and Pd ₂ Si. In the vertical axis of FIG. 2, the center (Undoped) is the Fermi level when ions are not doped, and is near the center of the forbidden band.
As is clear from FIG. 2, in Pd ₂ Si, when Sb, As, P, and F ions are doped, the Fermi level is shifted in the direction of the valence band (E _V ), and B ions are doped. In this case, the Fermi level shifts in the direction of the conduction band (E _C ). This is because the Fermi level shifts in the opposite direction compared to the case where these elements are implanted into NiSi.

  Side wall insulating films 8 made of, for example, silicon oxide are provided on both sides of the gate electrode 14a. Although not shown in FIG. 1, a surface protective film and a wiring layer are appropriately formed.

Thus, in the MOS type semiconductor device 100 according to the present embodiment, a Pd ₂ Si layer free from silicon deposition or the like can be used as a gate electrode.
Further, the work function of the gate electrode can be adjusted by doping the gate electrode with p-type or n-type impurities. In this case, compared to the case where NiSi is used for the gate electrode, the Fermi level shift direction is reversed when a predetermined impurity is doped in the gate electrode.

  Next, a method for manufacturing the MOS semiconductor device 100 according to the present embodiment will be described with reference to FIG. 3, the same reference numerals as those in FIG. 1 denote the same or corresponding parts. The manufacturing method of the MOS type semiconductor device 100 includes the following steps 1 to 10.

  Step 1: As shown in FIG. 3A, a semiconductor substrate 1 made of, for example, silicon is prepared. Next, the isolation region 2 made of, for example, silicon oxide is formed using a LOCOS (Local Oxidation of Silicon) method or an STI (Shallow Trench Isolation) method. Subsequently, p-type ions such as boron (B) and n-type ions such as phosphorus (P) are selectively implanted into the semiconductor substrate 1 to form a p-type well region 1a and an n-type well region 1b, respectively.

Step 2: As shown in FIG. 3B, a gate insulating film (gate oxide film) 3 is formed on the surface of the semiconductor substrate 1 by using, for example, a thermal oxidation method. The gate insulating film 3 is made of silicon oxide and has a film thickness of, for example, 2.5 to 3.0 nm.
Next, a silicon layer 4 made of polysilicon or amorphous silicon is formed on the gate insulating film 3 by using, for example, a CVD method. The film thickness of the silicon layer 4 is, for example, 100 to 150 nm.
Subsequently, impurity ions such as boron are selectively implanted (pre-doped) into the silicon layer 4 on the p-type well region 1a. Further, impurity ions such as phosphorus are selectively implanted (pre-doped) into the silicon layer 4 on the p-type well region 1a. Thereby, the work function of the gate electrode of full silicide (FUSI) formed from the silicon layer 4 can be controlled.
As described above, the relationship between the impurity implanted into the gate electrode and its work function modulation region is as shown in FIG. 2, and shows a behavior different from the case where NiSi is used for the gate electrode.

  Step 3: As shown in FIG. 3C, a hard mask 5 is formed on the silicon layer 4 by, eg, CVD. The hard mask 5 is made of, for example, silicon nitride and has a film thickness of 100 nm or less. Subsequently, a photoresist layer is formed on the hard mask 5 and patterned by a photolithography method or the like to form a resist mask 6.

  Step 4: As shown in FIG. 3D, the hard mask 5 is etched using the resist mask 6 as an etching mask. Next, the resist mask 6 is removed, and the silicon layer 4 and the gate insulating film 3 are etched using the hard mask 5 as an etching mask.

Step 5: As shown in FIG. 3E, n-type ions such as phosphorus are selectively implanted into the p-type well region 1a using the hard mask 5 as an implantation mask, and the n-type well region 1b. Then, p-type ions such as boron are selectively implanted. Thereby, extension regions 7a and 7b are formed. The impurity concentration of the extension regions 7a and 7b is, for example, 1 × 10 ²⁰ / cm ³ .

Step 6: As shown in FIG. 3F, the sidewall of the silicon layer 4 is oxidized by, eg, thermal oxidation to form a sidewall insulating film 8 made of silicon oxide. Next, using the hard mask 5 and the sidewall oxide film 8 as an implantation mask, n-type ions such as phosphorus are selectively implanted into the p-type well region 1a, and boron or the like is implanted into the n-type well region 1b. A p-type ion is selectively implanted. Thereby, source / drain regions 9a and 9b are formed. The impurity concentration of the source / drain regions 9a and 9b is, for example, 1 × 10 ²¹ / cm ³ . Further, the depths of the source / drain regions 9a and 9b are larger than the depths of the extension regions 7a and 7b. Subsequently, the implanted ions are activated by an annealing process. As a result, source / drain regions 9a and 9b and extension regions 7a and 7b provided inward thereof are formed.

  Step 7: As shown in FIG. 3G, a nickel layer 10 is deposited on the semiconductor substrate 1 by using, for example, a sputtering method.

  Step 8: As shown in FIG. 3H, a silicide layer 11 made of NiSi is formed on the surfaces of the source / drain regions 9a and 9b by heat treatment. For example, lamp annealing is used for the heat treatment, and the heat treatment temperature is in the range of 400 to 500 ° C., preferably 450 ° C. Next, the nickel layer 10 that has not become the silicide layer 11 is selectively removed using, for example, a mixed solution of sulfuric acid and hydrogen peroxide solution.

  Step 9: As shown in FIG. 3I, after an insulating film 13 made of, for example, silicon oxide is deposited on the entire surface, the surface is planarized using, for example, a CMP method. In the CMP process, the hard mask 5 is also removed, and the upper surfaces of the silicon layers 4a and 4b are exposed.

Step 10: As shown in FIG. 3J, a palladium layer 12 is deposited on the semiconductor substrate 1 by using, for example, a sputtering method. The thickness of the palladium layer 12 is such that the entire silicon layers 4a and 4b can be silicided in the next heat treatment step, and is preferably about one half of the thickness of the silicon layers 4a and 4b, for example.
Subsequently, the entire silicon layers 4a and 4b are silicided by heat treatment to form silicon layers 14a and 14b which are full silicide (FUSI) gate electrodes made of Pd ₂ Si. For example, lamp annealing is used for the heat treatment, and the heat treatment temperature is in the range of 250 to 300 ° C. Since the heat treatment temperature is lower than the heat treatment temperature of the silicide layer 11 made of NiSi (step 8), in the step of forming the silicon layers 14a and 14b, further silicidation of the silicide layer 11 (NiSi becomes NiSi ₂ etc.) ) And Ni can be prevented from diffusing in the depth direction and increasing the junction leakage current. Finally, the MOS layer 100 shown in FIG. 1 is completed by selectively removing the non-silicided palladium layer 12 using, for example, aqua regia.

  Note that the surface protective film and the wiring layer are appropriately formed.

As described above, in the method of manufacturing the MOS type semiconductor device 100 according to the present embodiment, the silicidation (full silicidation) process of the gate electrode is performed more than the formation process of the silicide layer 11 on the source / drain regions 9a and 9b. Done at low temperatures. Therefore, further silicidation of the silicide layer 11 (NiSi becomes NiSi ₂ or the like) can be prevented in the process of forming the full silicide gate. Further, it is possible to prevent Ni from diffusing in the depth direction of the semiconductor substrate and increasing the leakage current at the pn junction surface.

It is sectional drawing of the MOS type semiconductor device concerning embodiment of this invention. This is a work function modulation region when impurity ions are implanted into NiSi and Pd ₂ Si. It is sectional drawing of the manufacturing process of the MOS type semiconductor device concerning embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 1a p-type well region, 1b n-type well region, 2 separation region, 7a, 7b extension region, 8 side wall insulating film, 9a, 9b source / drain region, 11 silicide layer, 12 palladium layer, 13 insulating film , 14a, 14b Gate electrode, 100 MOS type semiconductor device, 100a n-ch MOSFET, 100b p-ch MOSFET.

Claims (9)

A semiconductor substrate;
A palladium silicide gate electrode provided on the semiconductor substrate via a gate insulating film;
A MOS structure semiconductor device including source / drain regions formed in the semiconductor substrate on both sides of the gate electrode,
A semiconductor device characterized in that the work function of the gate electrode is shifted to be small by doping the gate electrode with boron as an impurity.   2. The semiconductor device according to claim 1, wherein the semiconductor device having the MOS structure is an n-channel MOSFET. A semiconductor substrate;
A palladium silicide gate electrode provided on the semiconductor substrate via a gate insulating film;
A MOS structure semiconductor device including source / drain regions formed in the semiconductor substrate on both sides of the gate electrode,
A semiconductor device wherein the gate electrode is doped with an element selected from the group consisting of antimony, arsenic, phosphorus, and fluorine as an impurity, thereby shifting the work function of the gate electrode so as to increase. .   4. The semiconductor device according to claim 3, wherein the semiconductor device having the MOS structure is a p-channel MOSFET. A semiconductor substrate;
A palladium silicide gate electrode provided on the semiconductor substrate via a gate insulating film;
A semiconductor device including source / drain regions formed in the semiconductor substrate on both sides of the gate electrode,
And a silicide layer made of nickel silicide on the source / drain region. Preparing a semiconductor substrate;
Forming a p-type well region in the semiconductor substrate;
Forming a gate insulating film on the p-type well region and depositing a silicon layer thereon;
Doping the silicon layer with boron as an impurity;
Patterning the silicon layer to form a gate electrode;
Doping the p-type well region on both sides of the gate electrode with n-type ions to form source / drain regions so as to sandwich the gate electrode;
A first heat treatment step of forming a nickel layer on the source / drain regions and forming a silicide layer made of nickel silicide by heat treatment;
Forming a palladium layer so as to cover the gate electrode, and performing a heat treatment to make the gate electrode a full silicide electrode made of palladium silicide,
The method for manufacturing a semiconductor device, wherein the second heat treatment step is performed at a lower temperature than the first heat treatment step. Preparing a semiconductor substrate;
Forming an n-type well region in the semiconductor substrate;
Forming a gate insulating film on the n-type well region and depositing a silicon layer thereon;
Doping the silicon layer with an element selected from the group consisting of antimony, arsenic, phosphorus, and fluorine as an impurity;
Patterning the silicon layer to form a gate electrode;
Doping the n-type well region on both sides of the gate electrode with p-type ions to form source / drain regions so as to sandwich the gate electrode;
A first heat treatment step of forming a nickel layer on the source / drain regions and forming a silicide layer made of nickel silicide by heat treatment;
Forming a palladium layer so as to cover the gate electrode, and performing a heat treatment to make the gate electrode a full silicide electrode made of palladium silicide,
The method for manufacturing a semiconductor device, wherein the second heat treatment step is performed at a lower temperature than the first heat treatment step. The second heat treatment step is performed at a temperature of 400 ° C. or more and 500 ° C. or less,
The manufacturing method according to claim 6 or 7, wherein the first heat treatment step is performed at a temperature of 250 ° C or higher and 300 ° C or lower. The manufacturing method according to claim 6, wherein the silicon layer is made of a polycrystalline silicon layer or an amorphous silicon layer.

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