JP2008041204A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device reducing the manufacturing costs, the device size thereof and the power consumption thereof by securing a bit line sense margin while reducing the number of divided bit lines. <P>SOLUTION: The semiconductor memory device is provided with: a memory cell array having a plurality of memory cells 10 constituted of transistors and capacitors formed on a semiconductor substrate; a plurality of word lines 13; a plurality of bit lines; and a plurality of sense amplifiers for amplifying signals read from the plurality of memory cells to the bit lines, the plurality of memory cells 10 being connected to the bit lines, the plurality of bit lines being paired and having a plurality of switch circuits 15 for dividing the bit lines for each pair of bit lines 12, and having a plurality of second differential amplifying circuits 16 for amplifying signals read from the memory cells 10. Each pair of bit lines is connected to the sense amplifier 11. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory (DRAM).

In recent years, DRAMs are also required to have a reduced device size and lower power consumption. In order to reduce the device size, the number of bit line divisions is reduced. However, if the number of bit line divisions is reduced, the length of the bit line becomes longer and the word line is opened. There is a problem that the signal potential to the bit line to be read decreases.

In addition, when the number of bit line divisions is reduced, when the bit line information is latched in the sense amplifier, the current consumption due to charging / discharging of the bit line is reduced because the capacity of all bit lines connected to the sense amplifier to be latched There is a problem that gets bigger.

JP 2002-298592 A

An object of the present invention is to provide a semiconductor memory device that reduces the device size and the manufacturing cost by securing the bit line sense margin while reducing the number of bit line divisions, and also reduces the power consumption. .

In one embodiment of the present invention, a memory cell array having a plurality of memory cells made of transistors and capacitors formed on a semiconductor substrate, a plurality of word lines respectively connected to control gates of the plurality of memory cells, and a plurality of memory cells A bit line, a plurality of source lines, and a plurality of sense amplifiers for amplifying signals read from the plurality of memory cells to the bit lines, the bit lines including a plurality of sense amplifiers. A plurality of switch circuits that divide the bit line for each pair of bit lines and a plurality of second differences that amplify signals read from the memory cells; There is provided a semiconductor memory device having a dynamic amplifier circuit, wherein the bit lines are connected to the sense amplifiers in pairs.

According to an embodiment of the present invention, a semiconductor memory device is provided in which the device size is reduced by reducing the number of bit line divisions while securing the bit line sense margin, thereby reducing the manufacturing cost and reducing the power consumption. Is done.

Hereinafter, semiconductor devices according to embodiments of the present invention will be described in detail with reference to the drawings. In the embodiments, examples of the semiconductor device of the present invention are shown, and the manufacturing method of the semiconductor device of the present invention is not limited to these embodiments. In this description, common parts are denoted by common reference numerals throughout the drawings.

In recent years, demand for dynamic random access memory (hereinafter referred to as DRAM), which is high-speed random access, is increasing as a cache storage element for communication routers, data servers, and mobile phones. For use, etc., reduction in device size and reduction in power consumption are required.

In order to reduce the device size, the number of bit line divisions is reduced. However, if the number of bit line divisions is to be reduced, the bit line length becomes longer and the word line is opened for reading. The signal potential to the bit line decreases in inverse proportion to the length of the bit line. Further, the interference between the bit lines becomes remarkable according to the shrinkage of the device, and this interference may reduce the signal potential to the bit lines, which may deteriorate the bit line sense margin and cause a yield problem. Further, when the bit line information is latched in the sense amplifier, there is a problem that current consumption due to charging / discharging of the bit line increases because the capacity of all the bit lines connected to the sense amplifier to be latched is charged.

Before describing the semiconductor memory device according to the first embodiment of the present invention, the general configuration of a conventional semiconductor memory device will be described by taking a DRAM as an example. A conventional DRAM has a plurality of memory cells arranged in a matrix in the row direction and the column direction, and a plurality of n word lines that select the plurality of memory cells in a predetermined direction in the column direction. And a plurality of bit lines connected to the plurality of memory cells for each predetermined unit in the row direction and transmitting data of the memory cells in a selected state by the word lines.

The plurality of memory cells have one transistor and one capacitor, and a control electrode of the transistor is connected to one of n word lines, and a predetermined voltage is provided from the connected word line at the time of writing and reading. . The source of the transistor is connected to a source line through a capacitor, while the drain is connected to one of the plurality of bit lines. The memory cell to which a predetermined voltage is applied by the word line reads data by outputting the data stored in the cell to the bit line.

The plurality of word lines are connected to a row decoder, and the row decoder is connected to an address line. In order to reduce the device size by reducing the number of sense amplifiers, the plurality of bit lines are generally connected to one sense amplifier every two. The two bit lines connected to this one sense amplifier are hereinafter referred to as bit line pairs for the sake of explanation. Usually, a plurality of bit line pairs are arranged, but for explanation, it is assumed that m bit line pairs are arranged. Note that the number of bit lines connected to one sense amplifier is not limited to two, and more than that may be connected.

The sense amplifier is connected to the bit line to read data and also serves as a data latch for holding write data. A column gate for selecting a column is attached to the sense amplifier, and a column decoder performs this column gate control. By this column control, data transfer (reading and writing) is performed in units of one page between the sense amplifier and the memory cell array, whereas, for example, 1 byte is transferred between the sense amplifier and the external input / output terminal. Serial data transfer is performed in units.

In the conventional DRAM described above, as described above, when the number of bit line divisions is to be reduced, the length of the bit line is increased so that the signal to the bit line read by opening the word line is read. The potential decreases in inverse proportion to the length of the bit line. In particular, when the device size is further reduced, the interval between the bit lines is further reduced, and the interference between the bit lines becomes remarkable as the device shrinks. When this interference occurs, the signal potential to the bit line decreases, which may degrade the bit line sense margin and cause a yield problem.

In addition, when latching bit line information in the sense amplifier, it is necessary to charge the capacity of all the bit lines connected to the sense amplifier to be latched. However, as described above, since each sense amplifier is connected to two bit lines, that is, one bit line pair, even when latching data of a memory cell connected to one bit line. Therefore, it is necessary to charge the remaining one bit line of the pair of bit lines connected to the sense amplifier. For this reason, current consumption due to charging / discharging of the bit line is increased, which is an obstacle to realizing low power consumption.

Therefore, in order to solve such a problem, in the semiconductor memory device according to the first embodiment of the present invention, a switch that divides bit lines between adjacent memory cell arrays is provided, and further connected to one sense amplifier. A differential amplifier for amplifying the two bit lines is provided. The semiconductor memory device according to the first embodiment of the present invention will be described below with reference to the drawings, taking a DRAM as an example.

FIG. 1 is a schematic diagram schematically showing a configuration of a memory cell array and a sense amplifier of the semiconductor memory device according to the first embodiment of the present invention. The semiconductor memory device includes a plurality of memory cells 10 arranged in a matrix in a row direction and a column direction, and n word lines 13 that select the plurality of memory cells 10 in a predetermined direction in the column direction. And a 2m bit line connected to the plurality of memory cells 10 in a predetermined unit in the row direction and transmitting data of the memory cell 10 in a selected state by the word line 13 (not shown) )).

The plurality of memory cells 10 have one transistor 10a and one capacitor 10b. The control electrode of the transistor 10a is connected to one of the n word lines 13, and a predetermined voltage is applied from the word line 13 during writing and reading. Provided. The source of the transistor 10a is connected to a source line (not shown) via a capacitor 10b, and the drain is connected to one of 2m bit lines. The memory cell 10 to which a predetermined voltage is applied by the word line 13 reads data by outputting the data stored in the cell to the bit line.

The 2m bit lines are composed of two odd bit lines 12a and even bit lines 12b to form one bit line pair BLpair12 and connected to one sense amplifier 11. In FIG. 1, m bit line pairs BLpair 12 are arranged, but the number of bit lines connected to one sense amplifier 11 is not limited to two.

The sense amplifier 11 is connected to the bit line pair BLpair12 to read data, and also serves as a data latch that holds write data. Data transfer (reading and writing) is performed in units of one page between the sense amplifier 11 and the memory cell array, and serial data transfer is performed in units of, for example, 1 byte between the sense amplifier 11 and the external input / output terminals. Is called.

Between the word line WL1 (13) and the word line WLn (13) of the memory cell array, a switch (hereinafter referred to as a bit line MUX switch circuit 15) that divides each bit line pair BLpair12 is arranged. For the sake of explanation, in FIG. 1, a region closer to the sense amplifier 11 than the bit line MUX switch circuit 15 is referred to as a word line region A, and the opposite side is referred to as a word line region B.

The bit line MUX switch circuit 15 includes a pair of N channel transistors (N channel transistor 15a and N channel transistor 15b) for each bit line pair BLpair12. A gate signal LMUX17 is applied to the gate of the N-channel transistor from a signal line LMUX. The gate signal LMUX17 is set to a low level, for example, a GND level before the word line 13 is opened.

As shown in FIG. 1, the bit line MUX switch circuit 15 causes the bit line pair BLpair1 to the bit line pair BLpairM (12) to be connected to the word line area A and the word line area B on the left and right sides of the bit line MUX switch circuit 15, respectively. 2 minutes.

In the DRAM according to the first embodiment of the present invention, the sense amplifier 11 is connected to the bit line MUX switch circuit 15 in which the sense amplifier 11 is not directly connected to each pair of bit line pairs BLpair1 to BLpairM (12). A differential amplifier (hereinafter referred to as pre-sense amplifier 16) for amplifying the signal potential of the bit line pair BLpair 12 located on the far side is provided.

The pre-sense amplifier 16 includes a pair of N-channel transistor differential amplifiers 16b and 16c and an N-channel transistor 16a that controls activation / inactivation of the N-channel transistor differential amplifiers 16b and 16c.

The plurality of bit line pairs BLpair 12 are controlled to be connected to the sense amplifier 11 by opening and closing the bit line MUX switch circuit 15, and the pre-sense amplifier 16 amplifies the signal of the bit line not connected to the sense amplifier 11.

The pre-sense amplifier 16 is controlled by a signal LSEN 18 from a signal line LSEN, and the signal LSEN 18 from the signal line LSEN becomes a high level when the pre-sense amplifier 16 is used to amplify a signal on a bit line. .

The operation of the signal line LMUX and the signal LSEN will be described with reference to FIG. FIG. 2 is a timing chart of signals when the word line area A is accessed in the first embodiment of the present invention. Similarly, FIG. 3 is a timing chart of signals when the word line region B is accessed in the first embodiment of the present invention. A case where data is read from the memory cell in each word line region when each word line region A and word line region B are accessed will be described with reference to FIGS.

A case where data is read into the memory cells in the word line area A will be described with reference to FIG. In FIG. 2, at time t1, the gate signal LMUX 17 is switched from the high level to the low level. At time t2, the gate signal LMUX17 becomes a predetermined low level, whereby the bit line MUX switch circuit 15 is turned off, and the word line area A and the word line area B are cut off. At this time, a predetermined voltage is applied to the word line 13 in order to read data from the target memory cell. A predetermined read voltage is applied to the bit line of the bit line pair BLpair12 to which the target memory cell is connected, while a read pass voltage is applied to the remaining bitlines of the bitline pair BLpair12.

At time t3, the voltage of the word line 13 becomes a predetermined voltage. At time t4, the signal SEN14 is switched from the Low level to the High level, and at the same time, the voltage of the bit line to which the target memory cell is connected transitions to a predetermined read voltage. At time t5, the signal SEN14 reaches a predetermined high level, the sense amplifier 11 is activated, and at the same time, the bit line to which the read pass voltage is applied transitions to the predetermined voltage. At time t6, the potential of the bit line to which the target memory cell is connected transitions to the read voltage, and reading from the target memory cell to the bit line is performed.

At time t7, the voltage of the word line 13 is switched. At time t8, the signal SEN14 is switched to the low level, and the voltage of the bit line to which the target memory cell is connected is also switched from the read voltage to the precharge level. At time t9, the signal SEN14 returns to a predetermined low level, and the bit line pair BLpair returns to the precharge level. At time t10, the gate signal LMUX17 returns to the high level, the bit line MUX switch circuit 15 is turned on, and the shutoff of the word line area A and the word line area B is completed. Since the memory cell in the word line region A is accessed, amplification by the pre-sense amplifier is not performed, so that the signal LSEN 18 is held at the low level during this period. By the operation as described above, the memory cell located in the word line region A is accessed.

Next, a case where a memory cell located in the word line region B is accessed will be described with reference to FIG. At time t1 in FIG. 3, the gate signal LMUX17 is switched from the high level to the low level. At time t2, the gate signal LMUX17 becomes a predetermined low level, whereby the bit line MUX switch circuit 15 is turned off, and the word line area A and the word line area B are cut off. At time t3, a predetermined voltage is applied to the word line 13 in order to read data from the target memory cell. In the bit line pair BLpair12, the bit line connected to the target memory cell is read from the memory cell.

At time t4, the signal LSEN 18 is switched from the Low level to the Hihg level in order to amplify the signal read from the target memory cell to the bit line. At time t5, the pre-sense amplifier is turned on to amplify the signal read to the bit line. At time t6, the signal SEN14 is switched from the low level to the high level, and at the same time, the gate signal LMUX17 is switched from the low level to the high level.

At time t7, the gate signal LMUX17 becomes a predetermined high level, the block of the word line area A and the word line area B is completed, and the bit line located in the word line area A and the bit line located in the word line area B are Conduct. At the same time, the signal SEN14 reaches a predetermined high level and the sense amplifier 11 is activated. The signal amplified by the pre-sense amplifier 16 is transferred to the sense amplifier through the bit line in the word line region A, further amplified by the sense amplifier 11, and transferred to the external input / output terminal.

At time t8, the voltage of the word line 13 is switched. At time t9, the word line 3 returns to a predetermined low level, the amplification in the pre-sense amplifier 6 ends, and the signal LSEN18 is switched to the low level. At the same time, the signal SEN14 is switched to the Low level, and the voltage of the bit line to which the target memory cell is connected is also switched from the read voltage to the precharge voltage.

At time t10, the signal SEN14 returns to a predetermined low level and the operation of the sense amplifier 11 is terminated, and the bit line pair BLpair12 returns to the precharge level. By the operation as described above, a memory cell located in the word line region B is accessed.

As described above, when accessing a memory cell in the word line region A, the bit line on the word line region B side is blocked by the bit line MUX switch circuit 15, and therefore the bit line a1 (12a) and the bit line b1 The bit line length of (12b) is substantially about half. Therefore, it is possible to sufficiently secure a signal potential read to the bit line that decreases in inverse proportion to the length of the bit line, and to directly amplify the signal by the sense amplifier 11, thereby suppressing deterioration of the bit line sense margin. be able to.

On the other hand, when accessing the memory cell in the word line region B, the bit line MUX switch circuit 15 is once closed, so that the bit line lengths of the bit line a1 (12a) and the bit line b1 (12b) are substantially the same. About half the length. Therefore, the signal potential is ensured, and the read signal is amplified by the pre-sense amplifier 16, then the bit line MUX switch circuit 15 is opened, transferred to the sense amplifier 11, and amplified by the sense amplifier 11. Transferred to external input / output terminal. In this case, when the bit line MUX switch circuit 15 is opened, the bit line lengths of the bit line a1 (12a) and the bit line b1 (12b) are the original bit line lengths. Since the bit line MUX switch circuit 15 is in a closed state, a sufficient signal potential is ensured, and further amplified by the pre-sense amplifier 16 and transferred to the sense amplifier 11, so that the deterioration of the bit line sense margin is small.

In a semiconductor memory device, a word line is opened and a signal is transferred from a memory cell to a bit line and read. However, since the signal potential read to the bit line is extremely small, amplification is performed by a sense amplifier. However, when the number of bit line divisions is reduced, the signal potential to the bit line read by opening the word line is increased in inverse proportion to the length of the bit line. Will decrease. Further, when the device size is reduced, the interference between the bit lines becomes remarkable according to the shrinkage of the device, and the signal potential to the bit line decreases due to the interference. The margin will deteriorate.

In the semiconductor memory device according to the first embodiment of the present invention, as shown in FIG. 1, the bit line connected to the memory cell 10 to be accessed is connected to the sense amplifier 11 by the bit line MUX switch circuit 15. When not in a state, the signal is amplified to some extent by the pre-sense amplifier 16 and then the bit line MUX switch circuit 15 is opened to transfer a bit line signal to the sense amplifier 11, so that a sufficient signal potential can be secured. Can be reliably amplified. When the bit line connected to the memory cell 10 to be accessed is connected to the sense amplifier 11 by the bit line MUX switch circuit 15, it is amplified by the sense amplifier 11 as it is.

In the semiconductor memory device according to the first embodiment of the present invention, the bit line is separated by the bit line MUX switch 15 to open the word line 13 and transfer the signal from the bit line to the memory cell 10. Since the line capacitance looks effectively small, the signal potential can be increased. Therefore, even when the signal is directly amplified by the sense amplifier 11, a large signal potential is transferred, so that the deterioration of the bit line sense margin is small. Further, when the data is transferred after being amplified to some extent by the pre-sense amplifier 16, the deterioration of the sense margin can be further reduced. As a result, a large signal potential can be transferred even when the length of the bit line is increased, so that the number of bit line divisions can be reduced and the device size can be reduced.

In the semiconductor memory device according to one embodiment of the present invention, even when a shared sense amplifier (hereinafter referred to as a shared S / A) is employed as the sense amplifier, the same as in the first embodiment of the present invention. Demonstrate the effect.

FIG. 4 is a schematic diagram schematically showing the configuration of the memory cell array and the sense amplifier circuit of the semiconductor memory device according to the second embodiment of the present invention. FIG. 5 is an enlarged schematic view of a part including the word line region A and the word line region B in the configuration of the memory cell array and the sense amplifier circuit shown in FIG. As shown in FIG. 4, the semiconductor memory device has a plurality of memory cells 10 arranged in a matrix in the row direction and the column direction, and the plurality of memory cells 10 are selected in predetermined units in the column direction. N word lines 13 and 2m bit lines connected to the plurality of memory cells 10 in predetermined units in the row direction and transferring data of the memory cells 10 in a selected state by the word lines 13 A cell array (not shown).

FIG. 5 is an enlarged schematic view of a part of the word line region A and the word line region B in the configuration of the memory cell array and the sense amplifier circuit shown in FIG. As shown in FIG. 5, the plurality of memory cells 10 are composed of one transistor 10a and one capacitor 10b, and the control electrode of the transistor 10a is connected to one of n word lines 13, and the word is written and read. A predetermined voltage is provided from line 13. The transistor 10a has a source connected to a source line (not shown) via a capacitor 10b, and a drain connected to one of a plurality of bit lines. The memory cell 10 to which a predetermined voltage is applied by the word line 13 reads data by outputting the data stored in the cell to the bit line. The 2m bit lines are composed of an odd bit line 12a and an even bit line 12b to form one bit line pair BLpair12, and two bit line pairs BLpair12 are connected to one shared S / A19.

The shared S / A 19 is connected to the bit line pair BLpair12 to read data, and also serves as a data latch that holds write data. Data transfer (reading and writing) is performed between the shared S / A 19 and the memory cell array, and serial data transfer is performed between the shared S / A 19 and the external input / output terminals, for example, in units of 1 byte. Is done.

Two bit line pairs BLpair12 are connected to the shared S / A19. By using the shared S / A 19, a column decoder circuit (not shown) can be shared by a plurality of sense amplifiers. Therefore, the number of column decoders can be reduced, and the device size can be reduced. .

As shown in FIG. 5, a bit line MUX switch circuit 15 that divides bit lines is arranged between the word lines WL1 (13) and the word lines WLn (13) of the memory cell array.

The bit line MUX switch circuit 15 includes a pair of N channel transistors (15a, 15b) for each bit line pair BLpair12. The odd bit line pair (odd bit line pair) 12odd is connected to the bit line MUX switch circuit 1 (15odd) that receives the gate signal LMUX1 (17a) from the gate signal line LMUX1, and the even bit line pair (even bit line pair). ) 12even is connected to the bit line MUX switch circuit 2 (15even) that receives the gate signal LMUX2 (17b) from the gate signal line LMUX2. For the sake of explanation, in FIG. 5, the area on the shared S / A 19 side from each of the bit line MUX switch circuits (15odd, 15even) is called a word line area A, and the opposite side is called a word line area B.

The gate signal LMUX1 (17a) and the gate signal LMUX2 (17b) are set to, for example, a GND level Low level before the word line 13 is opened.

A pre-sense amplifier 16 that amplifies a signal read from the bit line is provided for each pair of bit line pairs BLpair1 to BLpairM (12). The pre-sense amplifier 16 includes a pair of N-channel transistor differential amplifiers 16b and 16c and an N-channel transistor 16a that controls the activation / inactivation of the N-channel transistor differential amplifiers 16b and 16c. Amplifies signals on bit lines that are not directly connected.

A pre-sense amplifier 1 (16odd) controlled by a signal LSEN1 (18a) from the signal line LSEN1 is connected to the odd bit line pair (odd bit line pair) 12odd, and an even bit line pair (even bit line) 12even is connected to the even bit line pair (even bit line) 12even. The pre-sense amplifier 2 (16even) controlled by the signal LSEN2 (18b) from the signal line LSEN2 is connected. The signal LSEN1 (18a) and the signal LSEN2 (18b) are at a high level when the signal on the bit line is amplified using the pre-sense amplifier 1 (16odd) and the pre-sense amplifier 2 (16even).

Operations of the signals LMUX and LSEN will be described with reference to FIGS. FIG. 6 is a timing chart of signals when the word line area A is accessed in the second embodiment of the present invention. FIG. 7 is a timing chart of signals when the word line region B is accessed in the second embodiment of the present invention. 6 and 7, in order to represent the operation of the odd bit line pair and the even bit line pair connected to the shared S / A 19, each bit line pair and the corresponding bit line MUX switch circuit 1 (15odd) and The gate signal LMUX1 (17a) and the gate signal LMUX2 (17b) for controlling the bit line MUX switch circuit 2 (15even) are displayed, but the bit line pair and bit corresponding to the bit line to which the target memory cell is connected The line MUX switch circuit operates.

A case of accessing a memory cell connected to an odd bit line pair (12odd) located in the word line region A will be described with reference to FIG. At time t1 in FIG. 6, the gate signal LMUX1 (17a) is switched from the high level to the low level. At time t2, the gate signal LMUX1 (17a) becomes a predetermined low level, whereby the bit line MUX switch circuit 1 (15odd) is turned off, and the word line area A and the word line area B are cut off. At this time, a predetermined voltage is applied to the word line 13 in order to read data from the target memory cell. A predetermined read voltage is applied to the bit line to which the target memory cell is connected in the bit line pair BLpair1 (12odd), and reading is performed from the memory cell.

At time t3, the voltage of the word line 13 becomes a predetermined voltage. At time t6, the signal SEN14 is switched from low level to high level. At time t7, the signal SEN14 reaches a predetermined high level, the sense amplifier 11 is activated, and the voltage of the bit line to which the target memory cell is connected is A transition is made to a predetermined read voltage, and reading from the target memory cell to the bit line is performed. At time t8, the voltage of the word line 13 is switched. At time t9, the word line 13 returns to a predetermined low level, and the signal SEN14 is switched to low level, and the operation of the sense amplifier 11 ends. The voltage of the bit line to which the target memory cell is connected is also switched from the read voltage to the precharge level. At time t10, the bit line returns to the precharge level, the gate signal LMUX1 (17a) becomes a predetermined high level, the bit line MUX switch circuit 1 is turned on, and the shutoff of the word line area A and the word line area B is completed. . Further, the signal SEN14 returns to the low level. By the operation as described above, the memory cells connected to the odd bit line pair (12odd) located in the word line region A are accessed.

Next, a case where a memory cell connected to the even bit line pair (12even) located in the word line region A is accessed will be described with reference to FIG. At time t1 in FIG. 6, the gate signal LMUX1 (17a) is switched from the high level to the low level. At time t2, the gate signal LMUX1 (17a) becomes a predetermined low level, whereby the bit line MUX switch circuit 2 (15even) is turned off, and the word line area A and the word line area B are cut off. At this time, a predetermined voltage is applied to the word line 13 in order to read data from the target memory cell. Of the bit line pair BLpair2 (12even), the bit line to which the target memory cell is connected is read from the memory cell.

At time t3, the voltage of the word line 13 becomes a predetermined voltage. At time t4, the signal LSEN2 (18b) is switched from the Low level to the High level in order to turn on the pre-sense amplifier 2 (16even) that amplifies the signal read from the target memory cell to the bit line. At time t5, the pre-sense amplifier 2 (16even) is turned on to pre-sense the read signal. At time t6, the signal SEN14 is switched from the Low level to the High level, and at the same time, the signal amplified by the pre-sense amplifier 2 (16even) is transferred to the shared S / A 19, so that the gate signal LMUX2 (17b) is changed from the Low level to the High level. Can be switched to. At time t7, the bit line MUX switch circuit 2 (15even) is turned on, the signal SEN14 reaches a predetermined high level, and the sense amplifier 11 is activated.

At time t8, the voltage of the word line 13 is switched. At time t9, the word line 13 returns to a predetermined low level, and the signal LSEN2 (18b) is switched to low level to turn off the signal SEN14 and the pre-sense amplifier 16. It is done. The voltage of the bit line to which the target memory cell is connected is also switched from the read voltage to the precharge level. At time t10, the signal SEN14 and the signal LSEN2 (18b) return to a predetermined low level, the operation of the sense amplifier 11 is completed, and the bit line also returns to a predetermined precharge level. By the operation as described above, data is read from the memory cells connected to the even bit line pair (12even) located in the word line region A.

Next, a case where a memory cell connected to an odd bit line pair (12odd) located in the word line region B is accessed will be described with reference to FIG. At time t1 in FIG. 7, the gate signal LMUX1 (17a) is switched from the high level to the low level. At time t2, the gate signal LMUX1 (17a) becomes a predetermined low level, whereby the bit line MUX switch circuit 1 (15odd) is turned off, and the word line area A and the word line area B are cut off. At this time, a predetermined voltage is applied to the word line 13 in order to read data from the target memory cell. Of the bit line pair BLpair1 (12odd), the bit line to which the target memory cell is connected is read from the memory cell.

At time t3, the voltage of the word line 13 becomes a predetermined voltage. At time t4, the signal LSEN1 (18a) is switched from the Low level to the High level in order to turn on the pre-sense amplifier 1 (16odd) that amplifies the signal read to the bit line. At time t5, the signal LSEN1 (18a) reaches a predetermined high level. At time t6, the signal SEN14 is switched from the Low level to the High level, and the bit line MUX switch circuit 1 (15odd) is turned on for the purpose of connecting the word line area A and the word line area B that have been interrupted. The gate signal LMUX1 (17a) is switched from the Low level to the High level.

At time t7, the gate signal LMUX1 (17a) reaches a predetermined high level, and the bit line MUX switch circuit 1 (15odd) is turned on. At time t8, the voltage of the bit line to which the target memory cell is connected transitions to a predetermined read voltage, and reading from the target memory cell to the bit line is performed. When the potential of the signal SEN14 reaches a predetermined high level, the sense amplifier 11 is activated. At time t9, the voltage of the word line 13 is switched. At time t10, the word line 13 returns to a predetermined low level, the potential of the signal SEN14 is switched to low level, and the bit line connected to the target memory cell is connected. The voltage is also switched from the read level to a predetermined precharge level, while the application of the read pass voltage is completed for the remaining bit lines of the bit line pair BLpair1 (12odd). Further, amplification in the pre-sense amplifier 1 (16odd) is completed, and the signal LSEN1 (18a) is switched to a predetermined low level. At time 11, the bit line returns to the predetermined precharge level, the signal LSEN1 (18a) becomes the predetermined high level, the signal SEN14 returns to the low level, and the operation of the sense amplifier 11 is completed. By the operation as described above, the memory cells connected to the odd bit line pair (12odd) located in the word line region B are accessed.

Next, referring to FIG. 7, a case where a memory cell connected to the even bit line pair (12even) located in the word line region B is accessed will be described. At time t1 in FIG. 7, the gate signal LMUX2 (17b) is switched from the high level to the low level. At time t2, the gate signal LMUX2 (17b) becomes a predetermined low level, whereby the bit line MUX switch circuit 2 (15even) is turned off, and the word line area A and the word line area B are cut off. At this time, a predetermined voltage is applied to the word line 13 in order to read data from the target memory cell. Of the bit line pair BLpair2 (12even), the bit line to which the target memory cell is connected is read from the memory cell.

At time t3, the voltage of the word line 13 becomes a predetermined voltage. At time t6, the potential of the signal SEN14 is switched from Low level to High level. At time t8, the potential of the signal SEN14 reaches a predetermined High level, and the sense amplifier 11 is activated.

At time t9, the voltage of the word line 13 is switched. At time t10, the word line 13 returns to a predetermined low level and the signal SEN14 is switched to low level. At the same time, the gate signal LMUX2 (17b) is switched from the Low level to the High level in order to turn on the bit line MUX switch circuit 2 (15even) for the purpose of connecting the word line region A and the word line region B which have been shut off. It is done. The voltage of the bit line to which the target memory cell is connected is also switched from the read level to a predetermined precharge level. At time t11, the signal SEN14 returns to a predetermined low level, the operation of the sense amplifier 11 is finished, the gate signal LMUX2 (17b) reaches a predetermined high level, and the bit line MUX switch circuit 2 (15even) is turned on. Then, the blocking of the word line area A and the word line area B is completed. At the same time, the bit line returns to the GND level. By the operation as described above, data is read from the memory cells connected to the even bit line pair (12even) located in the word line region B.

As described above, the word line region located on the shared S / A 19 side from the bit line MUX switch circuit (15odd, 15even) (that is, the word line region A in the odd bit line pair and the word line region B in the even bit line pair). When accessing the memory cell, the bit line MUX switch circuit (15odd, 15even) causes other word line regions (that is, the word line region B in the odd bit line pair and the word line region A in the even bit line pair). Since the bit line is cut off, the bit line length is substantially about half. Therefore, it is possible to sufficiently secure the signal potential read to the bit line that decreases in inverse proportion to the length of the bit line, and to suppress the deterioration of the bit line sense margin because the signal is directly amplified by the shared S / A 19. can do.

On the other hand, the word line region (ie, the word line region B in the odd bit line pair and the word line region A in the even bit line pair) located on the opposite side of the shared S / A 19 across the bit line MUX switch circuit (15odd, 15even). ) Is accessed, the bit line MUX switch circuit (15odd, 15even) is temporarily closed at the time of reading, so that the bit line length is substantially about half as well. Therefore, the signal potential is secured, and the read signal is once amplified by the pre-sense amplifier (16odd, 16even), and then the bit line MUX switch circuit (15odd, 15even) is opened to share the S / A19. , Amplified by the shared S / A 19 and transferred to the external input / output terminal. In this case, when the bit line MUX switch circuit (15odd, 15even) is opened, the bit line length becomes the original bit line length, but when the signal is read, the bit line MUX switch circuit (15odd, 15even) Since the signal is closed, a sufficient signal potential is secured, and further amplified by the pre-sense amplifier 16 and transferred to the shared S / A 19, so that the bit line sense margin is hardly deteriorated.

In a semiconductor memory device, a word line is opened and a signal is transferred from a memory cell to a bit line and read. However, since the signal potential read to the bit line is extremely small, amplification is performed by a sense amplifier. However, when the number of bit line divisions is reduced, the signal potential to the bit line read by opening the word line is increased in inverse proportion to the length of the bit line. Will decrease. Further, when the device size is reduced, the interference between the bit lines becomes remarkable according to the shrinkage of the device, and the signal potential to the bit line decreases due to the interference. The margin will deteriorate.

In the semiconductor memory device according to the second embodiment of the present invention, the bit line connected to the accessed memory cell is not connected to the shared S / A 19 by the bit line MUX switch circuit (15odd, 15even). In this case, a sufficient signal potential can be secured by opening the bit line MUX switch circuit (15odd, 15even) and transferring the bit line signal to the shared S / A 19 after being amplified once by the pre-sense amplifier 16. Amplification can be ensured at S / A19. When the bit line connected to the memory cell to be accessed is connected to the shared S / A 19 by the bit line MUX switch circuit (15odd, 15even), it is amplified by the shared S / A 19 as it is.

In the semiconductor memory device according to the second embodiment of the present invention, the bit line is divided by the bit line MUX switch circuit (15odd, 15even), thereby opening the word line 13 and transferring the signal from the memory cell to the bit line. Since the bit line capacitance at this time appears to be effectively small, the signal potential can be increased. Therefore, even when the signal is directly amplified by the shared S / A 19, since a large signal potential is transferred, the deterioration of the bit line sense margin is small. Further, when the data is amplified once by the pre-sense amplifier 16 and then transferred, the deterioration of the sense margin can be further reduced. As a result, a large signal potential can be transferred even when the length of the bit line is increased, so that the number of bit line divisions can be reduced and the device size can be reduced.

In the semiconductor memory device according to the third embodiment of the present invention, the number of bit lines can be greatly reduced while preventing the signal potential from being lowered to the bit lines read by opening the word lines. When the number of bit lines is reduced, the length of one bit line is increased, and the signal potential to the bit line read by opening the word line is lowered. This is an obstacle to reducing the device size, but according to the present invention, such a problem can be solved.

In the third embodiment of the present invention, P−1 bit line MUX switch circuits are provided for each bit line pair BLpair, the bit line is divided into P areas, and the sense amplifier among the divided bit lines is provided. P-1 pre-sense amplifiers are connected to the bit lines in each region except for the bit lines directly connected to the.

FIG. 8 is a schematic diagram schematically showing the configuration of the memory cell array and the sense amplifier circuit of the semiconductor memory device according to the third embodiment of the present invention. The semiconductor memory device includes a plurality of memory cells 10 arranged in a matrix in a row direction and a column direction, and n word lines 13 that select the plurality of memory cells 10 in a predetermined direction in the column direction. And a 2m bit line connected to the plurality of memory cells 10 in predetermined units in the row direction and transferring data of the memory cells 10 in a selected state by the word line 13 (not shown) )).

The plurality of memory cells 10 have the same configuration as the memory cells shown in the first embodiment and the second embodiment, and thus a detailed description is omitted, but a predetermined voltage is applied by the word line 13. The memory cell 10 reads data by outputting the data stored in the cell to the bit line.

The 2m bit lines are composed of two odd bit lines 12a and even bit lines 12b to form one bit line pair BLpair12 and connected to one sense amplifier 11. In FIG. 8, m bit line pairs BLpair 12 are arranged, but the number of bit lines connected to one sense amplifier 11 is not limited to two.

The sense amplifier 11 is connected to the bit line pair BLpair12 to read data, and also serves as a data latch that holds write data. Data transfer (reading and writing) is performed in units of one page between the sense amplifier 11 and the memory cell array, and serial data transfer is performed in units of, for example, 1 byte between the sense amplifier 11 and the external input / output terminals. Is called.

Between the word line WL1 (13) and the word line WLn (13) of the memory cell array, a bit line MUX switch circuit 15 that divides each bit line pair BLpair12 is arranged.

The configuration of the bit line MUX switch circuit 15 is the same as the configuration shown in the first embodiment and the second embodiment, and the details thereof will be omitted. However, the N-channel transistor configuring the bit line MUX switch circuit 15 is omitted. The gate signal LMUX17 is supplied from the signal line LMUX to these gates. The gate signal LMUX 17 is set to a low level (for example, a GND level) before the word line 13 is opened.

As shown in FIG. 8, the bit line MUX switch circuit 15 causes each of the bit line pairs BLpair1 to BLpairM (12) to be connected to P word line regions by P-1 bit line MUX switch circuits 15. Dividing and opening / closing the P-1 bit line switches 15 controls the transfer of information from the memory cells 10 connected to the bit line pair BLpair 12 in each word line region.

The semiconductor memory device according to the third embodiment of the present invention amplifies the signal potential of the bit line pair BLpair12 not directly connected to the sense amplifier 11 for each pair of bitline pairs BLpair1 to BLpairM (12). P-1 pre-sense amplifiers 16 are provided.

Since the configuration of the pre-sense amplifier 16 is the same as that of the first and second embodiments, the details are omitted.

The plurality of bit line pairs BLpair 12 are controlled to be connected to the sense amplifier 11 by opening and closing the bit line MUX switch circuit 15, and the pre-sense amplifier 16 amplifies the signal of the bit line not connected to the sense amplifier 11.

The pre-sense amplifier 16 is controlled by a signal LSEN 17 from a signal line LSEN, and the signal LSEN 17 from the signal line LSEN becomes a high level when the signal on the bit line is amplified using the pre-sense amplifier 16. .

In the semiconductor memory device according to the third embodiment of the present invention configured as described above, the bit line MUX switch circuit SWn and the bit line MUX switch sandwiching the word line region n + 1 to which the desired memory cell A10 is connected are sandwiched. The circuit SWn + 1 (not shown) is set to a low level when the word line WLl (13) connected to the desired memory cell A10 is opened, thereby reading data from the desired memory cell A10 to the bit line. The signal potential can be increased.

That is, when data is read from the desired memory cell A10 connected to the word line region n + 1 sandwiched between the bit line MUX switch circuit SWn and the bit line MUX switch circuit SWn + 1, the word to which the desired memory cell A10 is connected is read. When the line WLl (13) is opened, the two bit line MUX switch circuits 15 are set to a low level and the bit line MUX switch circuit 15 is closed. As a result, the word line region n + 1 is isolated from the adjacent word line region n and the word line region n + 2.

When the word line WLl (13) is opened and a sufficient signal potential is secured on the bit line, the pre-sense amplifier n16 disposed in the word line region n + 1 is activated by setting the signal LSENn18 to the high level. The signal on the word line WLl (13) is differentially amplified by the pre-sense amplifier n16.

After being sufficiently amplified by the pre-sense amplifier n16, the bit line MUX switch circuit n15 is opened by causing the bit line MUX switch circuit n15 located on the sense amplifier 11 side to transition to a high level, and the signal on the bit line is sensed. 11 and amplified again by the sense amplifier 11 and then transferred to the external input / output terminal.

When the signal is amplified by the pre-sense amplifier n16 and then transferred to the sense amplifier 11, all the bit line MUX switch circuits 15 located on the sense amplifier 11 side from the bit line MUX switch circuit n15 are opened, so that the length of the bit line is long. Although the signal potential is reduced, since it has already been sufficiently amplified by the pre-sense amplifier n16 before transfer, a sufficient signal potential that can be amplified again by the sense amplifier 11 can be secured even if the signal potential is reduced.

Since the operation corresponding to the signal of the semiconductor memory device according to the third embodiment of the present invention is the same as that of the first embodiment and the second embodiment, the detailed description by the timing chart is omitted. According to the third embodiment, when accessing the memory cell 10 in the desired word line region n + 1, the bit line MUX switch circuit n15 and the bit line switch circuit n + 1 (on both sides of the word line region n + 1) 15), the length of the bit line can be substantially reduced by blocking from the adjacent word line region n and the word line region n + 2, and the bit line can be reduced in inverse proportion to the length of the bit line. It is possible to suppress a decrease in the called signal potential.

Further, when a signal is transferred from the pre-sense amplifier n16 to the sense amplifier 11, the bit line MUX switch circuits 15 in all the word line regions located between the sense amplifier 11 and the word line region n + 1 are simultaneously opened, and the sense amplifier Since the signal is transferred through the bit lines arranged in all the word line regions located between 11 and the word line region n + 1, the length of the bit line is from the sense amplifier 11 to the word line region n at the time of transfer. In this invention, the signal potential is reduced after being sufficiently amplified by the pre-sense amplifier n16 disposed in the word line region n + 1. Therefore, a sufficient signal potential can be transferred even in consideration of a decrease in the signal potential at the time of transfer.

Further, by providing the bit line MUX switch circuit 15 and the pre-sense amplifier 16 shown in FIG. 8, according to the semiconductor memory device according to the third embodiment of the present invention, the device size that will be required more and more in the future is reduced. Sufficient response to requests is possible. That is, when the device size is reduced, it is required to reduce the interval between the bit lines. In this case, the signal potential to the bit lines is reduced due to the interference between the bit lines. Further, as the device shrinks, the interference between the bit lines becomes significant, and the signal potential is also significantly reduced. On the other hand, as a measure for reducing the device size, it is possible to reduce the device size by reducing the number of bit lines to reduce the number of bit lines themselves. In this case, as described above, one bit line is reduced. The length of must be increased. Then, as the length of the bit line becomes longer, the signal potential to the bit line decreases, so that the bit line sense margin deteriorates and the yield decreases. Therefore, the device size cannot be reduced unless the decrease in signal potential can be sufficiently suppressed.

As shown in FIG. 8, in the semiconductor memory device according to the third embodiment of the present invention, when reading data to the bit line, the bit line MUX switch circuit 15 assigns the bit line in the desired word line region to the other. Since data is read after the length of the word line is substantially shortened by blocking from the bit line in the word line region, the bit line capacitance appears to be effectively small, so that the signal potential can be increased. The signal potential is once amplified by the pre-sense amplifier 16 and then transferred to the sense amplifier 11. Therefore, regardless of the length of one bit line, the bit line MUX switch circuit 15 can reduce the effective length of the bit line to suppress the decrease in the signal potential. Even when the signal potential is decreased due to the significant interference, the signal is transferred after being amplified once by the pre-sense amplifier 16, so that it is possible to sufficiently meet the demand for a reduction in the device size.

Further, when data read from the memory cell 10 is latched in the sense amplifier 11, it is necessary to charge the capacity of all the bit lines connected to the sense amplifier 11 to be latched, and current consumption due to charging / discharging of the bit lines is reduced. However, in the semiconductor memory device according to the third embodiment of the present invention, the current consumption can be suppressed and the power consumption can be reduced. . That is, when reading the data of the memory cell 10 to the bit line, as described above, the bit line MUX switch sandwiching the word line region where the bit line connected to the desired memory cell 10 is disposed. Since the circuit 15 cuts off from the word line regions located on both sides, the only bit line that needs to be charged is the bit line arranged in the word line region, and the bit lines in the other word line regions do not need to be charged. Therefore, current consumption due to charging / discharging of the bit line can be reduced. Therefore, it is possible to measure a reduction in power consumption.

The effects of the third embodiment of the present invention described above are the same even when a shared sense amplifier is used as the sense amplifier. In the fourth embodiment of the present invention, a shared S / A is used for the sense amplifier, P−1 bit line MUX switch circuits are provided for each bit line pair BLpair, the bit line is divided into P regions, Of the divided bit lines, P-1 pre-sense amplifiers are connected to the bit lines in each region excluding the bit lines directly connected to the sense amplifiers.

FIG. 9 is a schematic diagram schematically showing the configuration of the memory cell array and the sense amplifier circuit of the semiconductor memory device according to the fourth embodiment of the present invention. FIG. 10 is an enlarged schematic view of a part of the configuration of the memory cell array and sense amplifier circuit shown in FIG. For the sake of explanation, description will be made below with reference to FIG.

The semiconductor memory device includes a plurality of memory cells 10 arranged in a matrix in a row direction and a column direction, and n word lines 13 that select the plurality of memory cells 10 in a predetermined direction in the column direction. And a 2m bit line connected to the plurality of memory cells 10 in predetermined units in the row direction and transferring data of the memory cells 10 in a selected state by the word line 13 (not shown) )).

The plurality of memory cells 10 have the same configuration as the memory cells shown in the first to third embodiments, and thus a detailed description is omitted, but a predetermined voltage is applied by the word line 13. The memory cell 10 reads data by outputting the data stored in the cell to the bit line.

The 2m bit lines are composed of two odd bit lines 12a and even bit lines 12b to form one bit line pair BLpair12 and connected to one shared S / A 19. 9 and 10, m bit line pairs BLpair 12 are arranged, but the number of bit lines connected to one shared S / A 19 is not limited to two.

The shared S / A 19 is connected to the bit line pair BLpair12 to read data, and also serves as a data latch that holds write data. Data transfer (reading and writing) is performed between the shared S / A 19 and the memory cell array, and serial data transfer is performed between the shared S / A 19 and the external input / output terminals, for example, in units of 1 byte. Is done.

Between the word line WL1 (13) and the word line WLn (13) of the memory cell array, a bit line MUX switch circuit 15 that divides each bit line pair BLpair12 is arranged.

Since the configuration of the bit line MUX switch circuit 15 is the same as that shown in the first to third embodiments, the details thereof will be omitted, but an N-channel transistor constituting the bit line MUX switch circuit 15 is omitted. The gate signal LMUX17 is supplied from the signal line LMUX to these gates. The gate signal LMUX 17 is set to a low level (for example, a GND level) before the word line 13 is opened.

As shown in FIG. 10, the bit line MUX switch circuit 15 causes each of the bit line pairs BLpair1 to BLpairM (12) to be connected to P word line regions by P-1 bit line MUX switch circuits 15. Dividing and opening / closing the P-1 bit line switches 15 controls the transfer of information from the memory cells 10 connected to the bit line pair BLpair 12 in each word line region.

Further, in the semiconductor memory device according to the fourth embodiment of the present invention, the signal potential of the bit line pair BLpair12 not directly connected to the shared S / A 19 is set for each pair of bitline pairs BLpair1 to BLpairM (12). P-1 pre-sense amplifiers 16 to be amplified are provided.

Since the configuration of the pre-sense amplifier 16 is the same as that of the first to third embodiments, the details are omitted.

The plurality of bit line pairs BLpair12 are controlled to be connected to the shared S / A 19 by opening / closing the bit line MUX switch circuit 15, and the pre-sense amplifier 16 amplifies the signal of the bit line not connected to the shared S / A 19 .

The pre-sense amplifier 16 is controlled by a signal LSEN 18 from a signal line LSEN, and the signal LSEN 18 from the signal line LSEN becomes a high level when the pre-sense amplifier 16 is used to amplify a signal on a bit line. .

In the semiconductor memory device according to the fourth embodiment of the present invention configured as described above, the bit line MUX switch circuit n15 and the bit line MUX switch sandwiching the word line region n + 1 to which the desired memory cell A10 is connected. The circuit n + 1 (15) (not shown) is set to a low level when the word line WLl (13) connected to the desired memory cell A10 is opened, so that the desired memory cell A10 is transferred to the bit line. The read signal potential can be increased.

That is, when data is read from a desired memory cell A10 connected to the word line region n + 1 sandwiched between the bit line MUX switch circuit n (15) and the bit line MUX switch circuit n + 1 (15), the desired memory cell When the word line WLl (13) to which A10 is connected is opened, the two bit line MUX switch circuits 15 are set to a low level and the two bit line MUX switch circuits 15 are closed. As a result, the word line region n + 1 is isolated from the adjacent word line region n and the word line region n + 2.

When the word line WLl (13) is opened and a sufficient signal potential is secured on the bit line, the pre-sense amplifier n16 disposed in the word line region n + 1 is activated by setting the signal LSENn18 to the high level. The signal on the word line WLl (13) is differentially amplified by the pre-sense amplifier n16.

After sufficiently amplifying by the pre-sense amplifier n16, the bit line MUX switch circuit n15 which is located on the shared S / A 19 side is shifted to a high level, so that the bit line MUX switch circuit n15 is opened and the signal on the bit line is The data is transferred to the shared S / A 19, amplified again by the shared S / A 19, and transferred to the external input / output terminal.

Since the operation corresponding to the signal of the semiconductor memory device according to the fourth embodiment of the present invention is the same as that of the first to third embodiments, the detailed description by the timing chart is omitted, but the present invention is omitted. According to the fourth embodiment, when accessing a memory cell in a desired word line region n + 1, the word line region n + is controlled by the bit line MUX switch circuits 15 on both sides of the word line region n. By blocking 1 from the adjacent word line region, the length of the bit line can be substantially shortened, and the decrease in the signal potential called from the bit line, which decreases in inverse proportion to the length of the bit line, is suppressed. It becomes possible to do.

Further, when a signal is transferred from the pre-sense amplifier n16 to the shared S / A 19, the signal potential is reduced as in the second embodiment. However, in the present invention, the pre-sense arranged in the word line region n + 1 is generated. Since the signal is transferred after being sufficiently amplified by the amplifier n16, a sufficient signal potential can be transferred even in consideration of a decrease in the signal potential at the time of transfer.

Further, when data is read out to the bit line, the bit line MUX switch circuit 15 cuts off the bit line in the desired word line region from the bit line in the other word line region to substantially reduce the length of the word line. In addition, since the data is read out, the bit line capacitance appears to be effectively small, so that the signal potential can be increased, and the signal potential is once amplified by the pre-sense amplifier 16 and then transferred to the shared S / A 19. Even if the interference between the bit lines becomes remarkable due to the shrinkage of the device and the signal potential is reduced, there is no problem and the size of the device can be reduced.

When reading the data of the memory cell to the bit line, as described above, the word line area where the bit line connected to the desired memory cell is arranged on both sides by the bit line MUX switch circuit 15 sandwiching the word line area. Therefore, the only bit line that needs to be charged is the bit line arranged in the word line region, and the current consumption due to charging / discharging of the bit line is small. It becomes possible to measure

1 is a schematic diagram schematically showing a configuration of a memory cell array and a sense amplifier of a semiconductor memory device according to a first embodiment of the present invention. FIG. 6 is a timing chart of signals when a word line area A is accessed in the first embodiment. FIG. 5 is a timing chart of signals when a word line region B is accessed in the first embodiment. FIG. 5 is a schematic diagram schematically showing a configuration of a memory cell array and a sense amplifier circuit of a semiconductor memory device according to a second embodiment of the present invention. 5 is an enlarged schematic view of a part including a word line region A and a word line region B in the configuration of the memory cell array and the sense amplifier circuit shown in FIG. It is a timing chart figure of the signal at the time of accessing the word line area A in the 2nd Embodiment of this invention. It is a timing chart figure of a signal at the time of accessing word line field B in a 2nd embodiment of the present invention. FIG. 6 is a schematic diagram schematically showing a configuration of a memory cell array and a sense amplifier circuit of a semiconductor memory device according to a third embodiment of the present invention. FIG. 10 is a schematic diagram schematically showing a configuration of a memory cell array and a sense amplifier circuit of a semiconductor memory device according to a fourth embodiment of the present invention. FIG. 10 is a schematic diagram enlarging a part of the configuration of the memory cell array and the sense amplifier circuit shown in FIG. 9.

Explanation of symbols

10: memory cell 10a: transistor 10b: capacitor 11: sense amplifier 12, 12odd, 12even: bit line pair 12a: odd bit line 12b: even bit line 13: word line 14: signal SEN
15, 15odd, 15even: bit line MUX switch circuits 15a, 15b: N-channel transistors 16, 16odd, 16even: pre-sense amplifiers 16a, 16b, 16c: N-channel transistors 17, 17a, 17b: gate signal LMUX
18, 18a, 18b: signal LSEN
19: Shared S / A

Claims (5)

A memory cell array having a plurality of memory cells made of transistors and capacitors formed on a semiconductor substrate;
A plurality of word lines respectively connected to control gates of the plurality of memory cells;
Multiple bit lines,
Multiple source lines,
A semiconductor memory device having a plurality of sense amplifiers for amplifying signals read from the plurality of memory cells to the bit lines;
A plurality of the memory cells are connected to the bit line,
The bit line is a plurality of pairs,
A plurality of switch circuits that divide bit lines for each pair of bit lines and a plurality of second differential amplifier circuits that amplify signals read from the memory cells;
2. The semiconductor memory device according to claim 1, wherein the pair of bit lines are connected to the sense amplifier in pairs. A memory cell array having a plurality of memory cells made of transistors and capacitors formed on a semiconductor substrate;
A plurality of word lines respectively connected to control gates of the plurality of memory cells;
Multiple bit lines,
Multiple source lines,
A semiconductor memory device having a plurality of sense amplifiers for amplifying signals read from the plurality of memory cells to the bit lines;
A plurality of the memory cells are connected to the bit line,
The bit line is a plurality of pairs,
A plurality of switch circuits that divide bit lines for each pair of bit lines and a plurality of second differential amplifier circuits that amplify signals read from the memory cells;
2. The semiconductor memory device according to claim 1, wherein a plurality of pairs of bit lines are connected to the sense amplifier. When the semiconductor memory device reads out a signal stored in a desired memory cell to the bit line, the two most recent switches arranged at positions where the desired memory cell is sandwiched among the plurality of switch circuits. 3. The semiconductor according to claim 1, wherein a switch circuit is made non-conductive to increase a signal potential read to a bit line to which a desired memory cell of the pair of bit lines is connected. Storage device. The semiconductor memory device reads out the desired two memory cells from the desired memory cell to the bit line by disabling the two nearest switch circuits arranged at positions where the desired memory cell is sandwiched among the plurality of switch circuits. Of the plurality of second differential amplifier circuits provided on the pair of bit lines including the bit line is amplified by the second differential amplifier circuit closest to the sense amplifier side from the memory cell. 3. The semiconductor memory device according to claim 1, wherein after the plurality of switch circuits are turned on, the amplified signal is transferred to the sense amplifier. In the semiconductor memory device, when the desired memory cell is located between one of the plurality of sense amplifiers and one of the plurality of switch circuits, the signal stored in the desired memory cell is transmitted to the bit line. When reading the data, the switch circuit is made non-conductive and read from the desired memory cell to the bit line, and the signal read to the bit line is amplified by the sense amplifier while the switch circuit is made non-conductive. The semiconductor memory device according to claim 1, wherein:

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