JP2008038208A - Plating apparatus and method of manufacturing semiconductor device - Google Patents

Plating apparatus and method of manufacturing semiconductor device Download PDF

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JP2008038208A
JP2008038208A JP2006214895A JP2006214895A JP2008038208A JP 2008038208 A JP2008038208 A JP 2008038208A JP 2006214895 A JP2006214895 A JP 2006214895A JP 2006214895 A JP2006214895 A JP 2006214895A JP 2008038208 A JP2008038208 A JP 2008038208A
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plating
substrate
anode
membrane
neutral
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JP4819612B2 (en
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Tetsuya Kurokawa
哲也 黒川
Koji Arita
幸司 有田
Kaori Noda
香織 野田
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NEC Electronics Corp
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    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D21/00Processes for servicing or operating cells for electrolytic coating
    • C25D21/16Regeneration of process solutions
    • C25D21/22Regeneration of process solutions by ion-exchange
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/001Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/002Cell separation, e.g. membranes, diaphragms
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00Electroplating characterised by the article coated
    • C25D7/12Semiconductors
    • C25D7/123Semiconductors first coated with a seed layer or a conductive layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition

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  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
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  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Electroplating Methods And Accessories (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To reduce the spending of an additive in the plating with a plating liquid containing the additive. <P>SOLUTION: The plating apparatus 200 is structured by arranging a laminated body 204 of a neutral filtration film 20 and a cation exchange film 208 between a substrate-to-be-treated 100 arranged in a plating bath 201 and an anode 220 so that the neutral filtration film 210 is positioned in the substrate-to-be-treated 100 side and separating the plating bath 201 into a first section 202a containing the substrate-to-be-treated 100 and the additive and a second section 202b containing the anode 220 by the laminated body 204. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、めっき処理装置および半導体装置の製造方法に関するものである。   The present invention relates to a plating apparatus and a method for manufacturing a semiconductor device.

半導体基板上に形成された配線溝やスルーホール等の凹部を銅等の金属材料で埋め込み、配線やビアを形成する手段として、めっき処理が用いられている。従来、このようなめっき処理において、めっき液中のアノード(陽極)側で発生するパーティクルの発生や、アクセラレータ、レベラ、またはサプレッサ等の添加剤がアノード上で分解することが問題となっていた。このような問題を防ぐために、アノードと被処理基板との間にイオン交換膜または中性膜を設けた構成が知られている。   Plating is used as a means for filling a recess such as a wiring groove or a through hole formed on a semiconductor substrate with a metal material such as copper to form a wiring or a via. Conventionally, in such a plating process, generation of particles generated on the anode (anode) side in the plating solution and decomposition of additives such as an accelerator, a leveler, or a suppressor on the anode have been problems. In order to prevent such a problem, a configuration in which an ion exchange membrane or a neutral membrane is provided between an anode and a substrate to be processed is known.

特許文献1(特開2003−73889号公報)には、半導体ウェハに電気銅めっきを行う際にめっき槽を陰イオン交換膜で陰極室と陽極室に隔離した構成が記載されている。これにより、半導体ウェハへのパーティクルの付着を防止することができるとされている。   Patent Document 1 (Japanese Patent Laid-Open No. 2003-73889) describes a configuration in which a plating tank is separated into an anion exchange membrane by a negative ion chamber when electrolytic copper plating is performed on a semiconductor wafer. Thereby, it is said that adhesion of particles to the semiconductor wafer can be prevented.

特許文献2(特開2005−133187号公報)には、イオン交換膜と基板の被めっき面とを互いに近接または接触させつつ、イオン交換膜と基板とを相対運動させた後にめっきを行うことにより、配線パターン上部におけるめっきを抑制してめっき速度を低下させる技術が記載されている。これにより、表面が平坦なめっき膜を形成することができるとされている。   In Patent Document 2 (Japanese Patent Application Laid-Open No. 2005-133187), the ion exchange membrane and the substrate to be plated are brought close to or in contact with each other, and the ion exchange membrane and the substrate are moved relative to each other to perform plating. In addition, a technique for reducing plating speed by suppressing plating at the upper part of the wiring pattern is described. Thereby, it is supposed that the plating film with the flat surface can be formed.

特許文献3(特開2000−192298号公報)には、陽極電極板と被めっき基板との間に多孔質の中性膜または陽イオン交換膜からなる隔膜を配置し、めっき槽本体内を陽極室と陰極室に隔離した構成が記載されている。これにより、めっき液中の添加剤が陽極電極板表面に接触し分解することを防止し、添加剤の不足によりめっき表面が粗くなることがなく、陽極電極板表面で発生する酸素ガスを速やかに除去でき、均一な金属めっき膜が形成できるとされている。   In Patent Document 3 (Japanese Patent Laid-Open No. 2000-192298), a diaphragm made of a porous neutral film or a cation exchange membrane is disposed between an anode electrode plate and a substrate to be plated, and the inside of the plating tank body is an anode. A separate configuration is described for the chamber and the cathode chamber. This prevents the additive in the plating solution from contacting and decomposing on the surface of the anode electrode plate, and the plating surface does not become rough due to lack of additives, and oxygen gas generated on the surface of the anode electrode plate can be quickly generated. It can be removed and a uniform metal plating film can be formed.

特許文献4(特開2001−49498号公報)には、非めっき基板と陽極電極との間にイオン交換樹脂または多孔性中性膜を配置してこれらを隔離した構成が記載されている。これにより、被めっき基板のめっき面に気泡が付着することがないようにすることができるとされている。
特開2003−73889号公報 特開2005−133187号公報 特開2000−192298号公報 特開2001−49498号公報
Patent Document 4 (Japanese Patent Laid-Open No. 2001-49498) describes a configuration in which an ion exchange resin or a porous neutral film is disposed between a non-plated substrate and an anode electrode to isolate them. Thereby, it is supposed that air bubbles can be prevented from adhering to the plating surface of the substrate to be plated.
JP 2003-73889 A JP 2005-133187 A JP 2000-192298 A JP 2001-49498 A

しかしながら、上記記載の従来技術は、以下の点で改善の余地を有していた。
陽イオンのみを選択的に透過させる陽イオン交換膜は、一般的にスルホン酸基等で構成されており、表面がマイナスに帯電している。そのため、アノードと被処理基板との間に陽イオン交換膜を設けた場合、添加剤が中性またはマイナスに帯電している場合は透過を抑制できるが、添加剤がプラスに帯電している場合は、添加剤が陽イオン交換膜に吸着しやすいという問題があった。一般的にレベラはプラスに帯電しており、陽イオン交換膜を用いた場合、レベラの消費レートが高くなるという問題があった。
However, the prior art described above has room for improvement in the following points.
Cation exchange membranes that selectively permeate only cations are generally composed of sulfonic acid groups and the like, and the surface is negatively charged. Therefore, when a cation exchange membrane is provided between the anode and the substrate to be processed, permeation can be suppressed if the additive is neutral or negatively charged, but the additive is positively charged. However, there was a problem that the additive was easily adsorbed on the cation exchange membrane. In general, the leveler is positively charged, and when a cation exchange membrane is used, there is a problem that the consumption rate of the leveler increases.

また、アノードと被処理基板との間に中性膜を設ける場合、中性膜の濾過径を細かくしすぎると、アノード側と被処理基板側とで透過が必要なイオンの透過も妨げられてしまうため、濾過径をあまり細かくできなかった。たとえば、アノードとして溶解性の銅アノードを用いた場合、アノードと被処理基板との間の銅イオン移動がスムーズに行われないと、銅イオンの投下効率が落ちてしまう。そのため、中性膜の濾過径を銅イオンが透過できる程度に大きくする必要がある。そのため、アクセラレータ等の分子量の小さい添加剤の透過を抑制できないという問題があった。   Further, when a neutral film is provided between the anode and the substrate to be processed, if the filtration diameter of the neutral film is too small, the transmission of ions that need to be transmitted between the anode side and the substrate to be processed is hindered. Therefore, the filtration diameter could not be made very fine. For example, when a soluble copper anode is used as the anode, the efficiency of dropping copper ions is lowered unless the copper ions are smoothly moved between the anode and the substrate to be processed. Therefore, it is necessary to increase the filtration diameter of the neutral membrane to such an extent that copper ions can permeate. For this reason, there is a problem that permeation of an additive such as an accelerator having a low molecular weight cannot be suppressed.

上記従来技術においては、アノードと被処理基板との間に陽イオン交換膜または中性膜(または陰イオン交換膜)のいずれか一方のみしか設けられていなかったため、めっき液中の添加剤の消費を低減できなかった。また、添加剤がアノード側に透過してしまい、アノードで接触分解し、不純物となってめっき液中に蓄積し、めっき膜の欠陥の原因となっていた。   In the above prior art, since only one of the cation exchange membrane or the neutral membrane (or anion exchange membrane) is provided between the anode and the substrate to be treated, consumption of the additive in the plating solution Could not be reduced. Further, the additive permeates to the anode side, catalytically decomposes at the anode, accumulates as impurities in the plating solution, and causes defects in the plating film.

本発明によれば、
添加剤を含むめっき液でめっき処理を行うめっき処理装置であって、
めっき槽中に配置された被処理基板とアノードとの間に、中性濾過膜と陽イオン交換膜との積層体を、前記被処理基板側に前記中性濾過膜が位置するように配置して、当該積層体により前記めっき槽を前記被処理基板および前記添加剤を含む第1室と前記アノードを含む第2室とに隔離したことを特徴とするめっき処理装置が提供される。
According to the present invention,
A plating apparatus for performing plating with a plating solution containing an additive,
A laminate of a neutral filtration membrane and a cation exchange membrane is placed between the substrate to be treated and the anode arranged in the plating tank so that the neutral filtration membrane is located on the substrate to be treated. Thus, there is provided a plating apparatus in which the plating tank is separated into the first chamber containing the substrate to be processed and the additive and the second chamber containing the anode by the laminate.

本発明によれば、
添加剤を含むめっき液でめっき処理を行う工程を含む半導体装置の製造方法であって、
前記めっき処理を行う工程は、めっき槽中に配置された被処理基板とアノードとの間に、中性濾過膜と陽イオン交換膜との積層体を、前記被処理基板側に前記中性濾過膜が位置するように配置して、前記めっき槽を前記被処理基板および前記添加剤を収容する第1室と前記アノードを収容する第2室とに隔離した状態で前記被処理基板にめっき処理を施す半導体装置の製造方法が提供される。
According to the present invention,
A method of manufacturing a semiconductor device including a step of performing a plating process with a plating solution containing an additive,
The step of performing the plating treatment includes the step of placing the neutral filtration membrane and cation exchange membrane between the substrate to be processed and the anode disposed in the plating tank, and the neutral filtration on the substrate to be processed. Placing the plating substrate on the substrate to be processed in a state where the film is positioned and the plating tank is separated into the first chamber containing the substrate to be processed and the additive and the second chamber containing the anode A method for manufacturing a semiconductor device is provided.

ここで、中性濾過膜は、極性を有しない無極性の濾過膜とすることができる。また、中性濾過膜は、多孔質構造を有し、孔径により分子量(分子径)の大きい分子の透過を抑制するように構成することができる。   Here, the neutral filtration membrane can be a nonpolar filtration membrane having no polarity. Further, the neutral filtration membrane has a porous structure, and can be configured to suppress permeation of molecules having a large molecular weight (molecular diameter) depending on the pore diameter.

このような構成とすると、たとえばめっき液が添加剤としてレベラ、アクセラレータ、およびサプレッサを含む場合でも、レベラが陽イオン交換膜に吸着するのを防ぐことができるとともに、分子量の小さい添加剤がアノード側に透過するのを防ぐことができる。これにより、添加剤の消費量を低減することができる。   With such a configuration, for example, even when the plating solution includes a leveler, an accelerator, and a suppressor as additives, the leveler can be prevented from adsorbing to the cation exchange membrane, and an additive having a low molecular weight can be added to the anode side. Can be prevented from passing through. Thereby, the consumption of an additive can be reduced.

なお、アノード(陽極電極板)は、溶解性のたとえば銅アノードにより構成することもでき、また不溶性陽極とすることもできる。アノードを銅アノードにより構成した場合、積層体は、銅イオンを透過可能に構成することができる。   The anode (anode electrode plate) can be made of a soluble copper anode, for example, or an insoluble anode. When the anode is constituted by a copper anode, the laminate can be constituted so as to be able to transmit copper ions.

本発明によれば、添加剤を含むめっき液でめっき処理を行う際に、添加剤の消費を低減することができる。   ADVANTAGE OF THE INVENTION According to this invention, when performing a plating process with the plating solution containing an additive, consumption of an additive can be reduced.

本実施の形態におけるめっき処理装置200は、半導体基板上に、銅膜をめっき法で形成する際に用いられる。   Plating apparatus 200 in the present embodiment is used when a copper film is formed on a semiconductor substrate by a plating method.

図1は、本実施の形態におけるめっき処理装置200の構成を示す断面図である。
めっき処理装置200は、めっき槽201と、めっき槽201中に配置されたアノード220とを含む。本実施の形態において、アノード220は、溶解性の銅アノードにより構成することができる。めっき槽201には、めっき液202が収容されている。めっき液202は、たとえば硫酸銅水溶液等により構成される。また、図示していないが、めっき処理装置200は、被処理基板100を載置する載置台を有し、当該載置台上に被処理基板100が配置されている。
FIG. 1 is a cross-sectional view showing a configuration of a plating apparatus 200 in the present embodiment.
The plating apparatus 200 includes a plating tank 201 and an anode 220 disposed in the plating tank 201. In the present embodiment, the anode 220 can be composed of a soluble copper anode. A plating solution 202 is accommodated in the plating tank 201. The plating solution 202 is composed of, for example, an aqueous copper sulfate solution. Although not shown, the plating apparatus 200 includes a mounting table on which the substrate to be processed 100 is mounted, and the substrate to be processed 100 is disposed on the mounting table.

めっき処理装置200は、さらに、被処理基板100とアノード220との間に配置された中性濾過膜210と陽イオン交換膜208との積層体204を含む。積層体204は、被処理基板100側に中性濾過膜210が位置するように配置される。めっき槽201は、積層体204により被処理基板100を含む第1室202aとアノード220を含む第2室202bとに隔離される。また、めっき処理装置200は、積層体204と被処理基板100との間に配置された整流板214を含む。整流板214は、被処理基板100近傍でのめっき液202液の流れを均一にする目的で設置される。ただし、孔径が充分大きく、めっき液202の構成材料の透過可能に構成される。   The plating apparatus 200 further includes a laminate 204 of a neutral filtration membrane 210 and a cation exchange membrane 208 disposed between the substrate to be processed 100 and the anode 220. The stacked body 204 is disposed so that the neutral filtration membrane 210 is positioned on the substrate 100 side to be processed. The plating tank 201 is isolated by the stacked body 204 into a first chamber 202 a containing the substrate to be processed 100 and a second chamber 202 b containing the anode 220. The plating apparatus 200 includes a rectifying plate 214 disposed between the stacked body 204 and the substrate to be processed 100. The current plate 214 is installed for the purpose of making the flow of the plating solution 202 near the substrate 100 to be processed uniform. However, the hole diameter is sufficiently large so that the constituent material of the plating solution 202 can pass therethrough.

第1室202aにおいて、めっき液202中には、添加剤としてレベラ、アクセラレータ(促進剤)、およびサプレッサ(抑制剤)が導入されている。     In the first chamber 202a, a leveler, an accelerator (accelerator), and a suppressor (inhibitor) are introduced into the plating solution 202 as additives.

本実施の形態において、レベラとしては、たとえば分子量2000〜3000で、正に帯電した材料を用いることができる。このような材料としては、たとえば陽イオン性アミンポリマーを用いることができる。   In the present embodiment, as the leveler, for example, a positively charged material having a molecular weight of 2000 to 3000 can be used. As such a material, for example, a cationic amine polymer can be used.

本実施の形態において、アクセラレータとしては、たとえば分子量500以下で、ジスルフィド結合を有し、負に帯電した材料を用いることができる。このような材料としては、一般式
SO −R−S−S−R−SO (ここでRおよびRはそれぞれ独立して炭化水素鎖)
で表されるものを用いることができる。
In the present embodiment, as the accelerator, for example, a negatively charged material having a molecular weight of 500 or less and having a disulfide bond can be used. Such materials, the general formula SO 3 - -R 1 -S-S -R 2 -SO 3 - ( hydrocarbon chain wherein R 1 and R 2 each independently)
Can be used.

本実施の形態において、サプレッサとしては、たとえば分子量2000〜3000で、極性を有しない材料を用いることができる。このような材料としては、たとえばポリエチレングリコールを用いることができる。   In the present embodiment, as the suppressor, for example, a material having a molecular weight of 2000 to 3000 and having no polarity can be used. As such a material, for example, polyethylene glycol can be used.

積層体204は、レベラ、アクセラレータ、およびサプレッサの透過を抑制するように構成される。また、本実施の形態において、積層体204は、銅イオンを透過可能に構成される。中性濾過膜210は、微細な孔を有し、孔径よりも小さいサイズの分子を透過するとともに大きいサイズの分子の透過を抑制する。中性濾過膜210は、無極性であるとともに、少なくともレベラの透過を抑制する孔径を有するように構成される。本実施の形態において、中性濾過膜210の孔径は、0.5μm以下とすることができる。これにより、上記のようなレベラの透過を抑制することができる。一方、銅イオンを通過させるために、中性濾過膜210の孔径は、0.01μm以上とすることができる。中性濾過膜210としては、たとえばポリプロピレンを用いることができる。   The laminate 204 is configured to suppress transmission of the leveler, the accelerator, and the suppressor. Moreover, in this Embodiment, the laminated body 204 is comprised so that copper ion can permeate | transmit. The neutral filtration membrane 210 has fine pores, transmits molecules having a size smaller than the pore diameter, and suppresses transmission of molecules having a large size. The neutral filtration membrane 210 is nonpolar and is configured to have at least a pore size that suppresses permeation of the leveler. In the present embodiment, the pore size of the neutral filtration membrane 210 can be 0.5 μm or less. Thereby, permeation | transmission of the above levelers can be suppressed. On the other hand, in order to allow copper ions to pass through, the pore size of the neutral filtration membrane 210 can be set to 0.01 μm or more. As the neutral filtration membrane 210, for example, polypropylene can be used.

陽イオン交換膜208は、陽イオンのみを選択的に透過させる。陽イオン交換膜208としては、たとえばスルホン酸基を有するポリアクリル樹脂を用いることができる。   The cation exchange membrane 208 selectively transmits only cations. As the cation exchange membrane 208, for example, a polyacrylic resin having a sulfonic acid group can be used.

本実施の形態において、積層体204は、中性濾過膜210と陽イオン交換膜208とが互いに接して設けられた積層膜206と、積層膜206を保持する保持板212とを含む。このような積層膜206を用いることにより、中性濾過膜210と陽イオン交換膜208との間に空気等の気泡が侵入するのを防ぎ、めっき槽201中のめっき液の流れの制御を容易に行うことができる。   In the present embodiment, the laminate 204 includes a laminate membrane 206 in which a neutral filtration membrane 210 and a cation exchange membrane 208 are provided in contact with each other, and a holding plate 212 that holds the laminate membrane 206. By using such a laminated film 206, it is possible to prevent bubbles such as air from entering between the neutral filtration membrane 210 and the cation exchange membrane 208, and to easily control the flow of the plating solution in the plating tank 201. Can be done.

図2は、積層体204を中性濾過膜210側から見た平面図である。図示していないが、めっき槽201は、円柱型に構成されている。積層体204は、めっき槽201の断面積と等サイズに構成され、めっき槽201を第1室202aと第2室202bとに区画する。ただし、積層体204は、第1室202aに導入されたレベラ、アクセラレータ、およびサプレッサが第2室202bに透過しない構成となっていればどのような構成とすることもできる。たとえば、他の例において、めっき液202と被処理基板100との間を部分的に隔てる隔壁を設け、隔壁で隔たれていない開放部分に積層体204を配置する構成とすることもできる。ここで、保持板212は、たとえばプラスチック材料により構成され、積層膜206を補強する骨組み構造を有する。   FIG. 2 is a plan view of the laminate 204 as viewed from the neutral filtration membrane 210 side. Although not shown, the plating tank 201 is formed in a cylindrical shape. The laminated body 204 is configured to have the same size as the cross-sectional area of the plating tank 201, and partitions the plating tank 201 into a first chamber 202a and a second chamber 202b. However, the stacked body 204 can have any configuration as long as the leveler, the accelerator, and the suppressor introduced into the first chamber 202a do not pass through the second chamber 202b. For example, in another example, a partition wall that partially separates the plating solution 202 and the substrate to be processed 100 may be provided, and the laminate 204 may be disposed in an open portion that is not separated by the partition wall. Here, the holding plate 212 is made of, for example, a plastic material and has a framework structure that reinforces the laminated film 206.

次に、以上のように構成された積層体204の機能を説明する。
積層体204において、中性濾過膜210が第1室202a側に設けられている。そのため、第1室202aにレベラ、アクセラレータ、およびサプレッサが導入されている場合に、まず、中性濾過膜210により、分子量の大きいレベラおよびサプレッサの透過が抑制される。そのため、レベラおよびサプレッサが第2室202bに移動するのを防ぐことができ、これらの消費量を低減することができる。また、プラスに帯電したレベラが陽イオン交換膜208に接するのを防ぐことができるので、レベラの消費量をより低減することができる。一方、分子量の小さいアクセラレータが中性濾過膜210を透過しても、陽イオン交換膜208によりアクセラレータが第2室202bに移動するのを防ぐことができる。これにより、中性濾過膜210の孔径をアクセラレータが通過できる程度に大きくしても、アクセラレータの消費量も低減することができる。
Next, the function of the laminate 204 configured as described above will be described.
In the laminate 204, a neutral filtration membrane 210 is provided on the first chamber 202a side. Therefore, when a leveler, an accelerator, and a suppressor are introduced into the first chamber 202a, the neutral filtration membrane 210 first suppresses the permeation of the leveler and suppressor having a large molecular weight. Therefore, it is possible to prevent the leveler and suppressor from moving to the second chamber 202b, and to reduce their consumption. In addition, since the positively charged leveler can be prevented from coming into contact with the cation exchange membrane 208, the consumption of the leveler can be further reduced. On the other hand, even if an accelerator having a small molecular weight passes through the neutral filtration membrane 210, the cation exchange membrane 208 can prevent the accelerator from moving to the second chamber 202b. Thereby, even if the hole diameter of the neutral filtration membrane 210 is increased to such an extent that the accelerator can pass, the consumption of the accelerator can also be reduced.

次に、本実施の形態におけるめっき処理装置200を用いて半導体装置を製造する手順を図6を参照して説明する。   Next, a procedure for manufacturing a semiconductor device using the plating apparatus 200 according to the present embodiment will be described with reference to FIG.

半導体装置300は、トランジスタ等が形成された半導体基板302と、半導体基板302上に形成された層間絶縁膜304と、その上に形成された層間絶縁膜306とを含む。層間絶縁膜304および層間絶縁膜306中には、配線やビアが形成されている。   The semiconductor device 300 includes a semiconductor substrate 302 on which transistors and the like are formed, an interlayer insulating film 304 formed on the semiconductor substrate 302, and an interlayer insulating film 306 formed thereon. Wirings and vias are formed in the interlayer insulating film 304 and the interlayer insulating film 306.

このように構成された半導体装置300において、まず、層間絶縁膜306に配線溝(凹部)を形成する。ここで、図示したように、層間絶縁膜306には、第1の配線溝308、第2の配線溝310、第3の配線溝312、第4の配線溝314、第5の配線溝316、第6の配線溝318、および第7の配線溝320が形成される(図6(a))。   In the semiconductor device 300 configured as above, first, a wiring groove (concave portion) is formed in the interlayer insulating film 306. Here, as illustrated, the interlayer insulating film 306 includes a first wiring groove 308, a second wiring groove 310, a third wiring groove 312, a fourth wiring groove 314, a fifth wiring groove 316, A sixth wiring groove 318 and a seventh wiring groove 320 are formed (FIG. 6A).

このような配線溝を配線材料で埋め込む手順は、以下のようになる。まず、層間絶縁膜306の配線溝内にバリアメタル膜を形成する。バリアメタル膜は、たとえばTaN/Ta等、通常の銅配線のバリアメタル膜として用いられるものとすることができる。つづいて、バリア膜上にめっきのシード膜を形成する。ここで、シード膜は、CVD法等により形成された銅膜等とすることができる。   The procedure for filling such a wiring groove with a wiring material is as follows. First, a barrier metal film is formed in the wiring trench of the interlayer insulating film 306. The barrier metal film can be used as a barrier metal film of normal copper wiring, such as TaN / Ta. Subsequently, a plating seed film is formed on the barrier film. Here, the seed film can be a copper film formed by a CVD method or the like.

その後、めっき処理装置200を用いてめっき処理を行う。これにより、配線溝内にめっき膜332を形成することができる。ここで、めっき膜332は、銅膜とすることができる(図6(b))。本実施の形態におけるめっき処理装置200を用いることにより、添加剤の分解生成物による欠陥を抑制することができる。   Thereafter, a plating process is performed using the plating apparatus 200. Thereby, the plating film 332 can be formed in the wiring groove. Here, the plating film 332 can be a copper film (FIG. 6B). By using the plating apparatus 200 in the present embodiment, defects due to the decomposition products of the additives can be suppressed.

図1を参照して説明したのと同様に、被処理基板100とアノード220との間に積層体204を配置してレベラ、アクセラレータ、およびサプレッサそれぞれの消費量を調べた。レベラとして分子量2500の陽イオン性アミンポリマー、アクセラレータとして分子量310のビス(3−スルホプロピル)ジスルフィド、サプレッサとして分子量2200のポリエチレングリコールを用いた。陽イオン交換膜としてスルホン酸基を有するポリアクリル樹脂、中性濾過膜としてポリプロピレンを用いた。実験は、30日間毎日行った。また、比較として、中性濾過膜のみ、陽イオン交換膜のみ、中性濾過膜も陽イオン交換膜もなしの場合についても同様にレベラ、アクセラレータ、およびサプレッサそれぞれの消費量を調べた。   In the same manner as described with reference to FIG. 1, the stacked body 204 is disposed between the substrate to be processed 100 and the anode 220, and the consumption amounts of the leveler, the accelerator, and the suppressor are examined. A cationic amine polymer having a molecular weight of 2500 was used as a leveler, bis (3-sulfopropyl) disulfide having a molecular weight of 310 was used as an accelerator, and polyethylene glycol having a molecular weight of 2200 was used as a suppressor. A polyacrylic resin having a sulfonic acid group was used as a cation exchange membrane, and polypropylene was used as a neutral filtration membrane. The experiment was performed daily for 30 days. For comparison, the consumption of each of the leveler, accelerator, and suppressor was also examined in the case of only the neutral filtration membrane, only the cation exchange membrane, and no neutral filtration membrane or cation exchange membrane.

図3〜図5に結果を示す。条件は以下のとおりである。
(1)積層膜(中性濾過膜+陽イオン交換膜:積層体204)
(2)中性濾過膜のみ
(3)陽イオン交換膜のみ
(4)中性濾過膜も陽イオン交換膜もなし
The results are shown in FIGS. The conditions are as follows.
(1) Laminated membrane (neutral filtration membrane + cation exchange membrane: laminate 204)
(2) Neutral filtration membrane only (3) Cation exchange membrane only (4) No neutral filtration membrane or cation exchange membrane

図3は、レベラの消費量を示す図である。ここで、縦軸は、(1)の積層膜を用いた場合を1として規格化したレベラの消費量を示す。(1)〜(3)のいずれの場合も、膜を用いていない(4)に比べるとレベラの消費量は低減された。しかし、(3)の陽イオン交換膜のみの場合、(1)の積層膜を用いた場合に比べて、レベラの消費量が2倍近く多くなっている。(2)の中性濾過膜のみの場合、(1)の積層膜を用いた場合に比べて、レベラの消費量がわずかに多くなっているが、大きな変化はなかった。いずれの場合についても、30日経過後も膜特性に変化はなかった。   FIG. 3 is a diagram showing the consumption of the leveler. Here, the vertical axis indicates the leveler consumption normalized with the case where the laminated film of (1) is used as 1. In any of the cases (1) to (3), the leveler consumption was reduced as compared to (4) in which no membrane was used. However, in the case of using only the cation exchange membrane (3), the consumption of the leveler is nearly twice as high as that in the case of using the laminated membrane (1). In the case of (2) only the neutral filtration membrane, the consumption of the leveler was slightly increased as compared with the case of using the laminated membrane of (1), but there was no significant change. In any case, there was no change in film properties even after 30 days.

図4は、アクセラレータの消費量を示す図である。ここで、縦軸は、(1)の積層膜を用いた場合を1として規格化したアクセラレータの消費量を示す。(1)〜(3)のいずれの場合も、膜を用いていない(4)に比べるとアクセラレータの消費量は低減された。しかし、(2)の中性濾過膜のみの場合、(1)の積層膜を用いた場合に比べて、アクセラレータの消費量が1.5倍以上多くなっている。(3)の陽イオン交換膜のみの場合、(1)の積層膜を用いた場合に比べて、アクセラレータの消費量がわずかに多くなっているが、大きな変化はなかった。いずれの場合についても、30日経過後も膜特性に変化はなかった。   FIG. 4 is a diagram illustrating accelerator consumption. Here, the vertical axis indicates the amount of consumption of the accelerator normalized with the case where the laminated film of (1) is used as 1. In any of the cases (1) to (3), the consumption of the accelerator was reduced as compared with (4) in which no film was used. However, in the case of (2) only the neutral filtration membrane, the consumption of the accelerator is 1.5 times or more higher than in the case of using the laminated membrane of (1). In the case of only the cation exchange membrane of (3), the consumption of the accelerator is slightly increased as compared with the case of using the laminated membrane of (1), but there is no significant change. In any case, there was no change in film properties even after 30 days.

図5は、サプレッサの消費量を示す図である。ここで、縦軸は、(1)の積層膜を用いた場合を1として規格化したサプレッサの消費量を示す。(1)〜(3)のいずれの場合も、膜を用いていない(4)に比べるとサプレッサの消費量は低減された。(2)の中性濾過膜のみの場合および(3)の陽イオン交換膜のみの場合、(1)の積層膜を用いた場合に比べて、アクセラレータの消費量がわずかに多くなっているが、大きな変化はなかった。いずれの場合についても、30日経過後も膜特性に変化はなかった。   FIG. 5 is a diagram showing the consumption of the suppressor. Here, the vertical axis indicates the consumption of the suppressor normalized with the case where the laminated film of (1) is used as 1. In any of the cases (1) to (3), the consumption of the suppressor was reduced as compared with (4) in which no membrane was used. In the case of only the neutral filtration membrane of (2) and the case of only the cation exchange membrane of (3), the consumption of the accelerator is slightly increased as compared with the case of using the laminated membrane of (1). There was no big change. In any case, there was no change in film properties even after 30 days.

以上のように、積層体204を用いることにより、レベラ、アクセラレータ、およびサプレッサの3つの添加剤すべての消費量を同時に低減することができた。   As described above, by using the laminate 204, the consumption of all three additives of the leveler, the accelerator, and the suppressor could be reduced at the same time.

以上、図面を参照して本発明の実施形態について述べたが、これらは本発明の例示であり、上記以外の様々な構成を採用することもできる。   As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

実施の形態においては、アノード220が銅アノードである場合を例として説明したが、アノード220は、不溶性アノードとすることもできる。この場合も積層体204は、上述したのと同様に構成することができるが、たとえば銅イオンを透過しないように構成してもよい。   In the embodiment, the case where the anode 220 is a copper anode has been described as an example, but the anode 220 may be an insoluble anode. Also in this case, the laminate 204 can be configured in the same manner as described above, but may be configured not to transmit, for example, copper ions.

また、以上の実施の形態において、めっき液が銅イオンを含む銅めっきを例として説明したが、本発明は他の種々のめっき処理に適用することができる。たとえば、ニッケル等を用いて、半導体装置のバンプを形成するめっき処理にも適用することができる。この場合も、アノードとしては、溶解性および不溶性のいずれを用いてもよい。   Moreover, in the above embodiment, although copper plating in which the plating solution contains copper ions has been described as an example, the present invention can be applied to other various plating processes. For example, the present invention can be applied to a plating process for forming bumps of a semiconductor device using nickel or the like. In this case as well, either soluble or insoluble may be used as the anode.

本発明の実施の形態におけるめっき処理装置の構成を示す断面図である。It is sectional drawing which shows the structure of the plating processing apparatus in embodiment of this invention. 本発明の実施の形態におけるめっき処理装置に含まれる積層体を中性濾過膜側から見た平面図である。It is the top view which looked at the laminated body contained in the plating processing apparatus in embodiment of this invention from the neutral filtration membrane side. 実施例におけるレベラの消費量を示す図である。It is a figure which shows the consumption of the leveler in an Example. 実施例におけるアクセラレータの消費量を示す図である。It is a figure which shows the consumption of the accelerator in an Example. 実施例におけるサプレッサの消費量を示す図である。It is a figure which shows the consumption of the suppressor in an Example. 本発明の実施の形態における半導体装置の製造手順を示す工程断面図である。It is process sectional drawing which shows the manufacturing procedure of the semiconductor device in embodiment of this invention.

符号の説明Explanation of symbols

100 被処理基板
200 めっき処理装置
201 めっき槽
202 めっき液
202a 第1室
202b 第2室
204 積層体
206 積層膜
208 陽イオン交換膜
210 中性濾過膜
212 保持板
220 アノード
300 半導体装置
302 半導体基板
304 層間絶縁膜
306 層間絶縁膜
308 第1の配線溝
310 第2の配線溝
312 第3の配線溝
314 第4の配線溝
316 第5の配線溝
318 第6の配線溝
320 第7の配線溝
332 めっき膜
DESCRIPTION OF SYMBOLS 100 Substrate 200 Plating apparatus 201 Plating tank 202 Plating solution 202a First chamber 202b Second chamber 204 Laminate 206 Laminated membrane 208 Cation exchange membrane 210 Neutral filtration membrane 212 Holding plate 220 Anode 300 Semiconductor device 302 Semiconductor substrate 304 Interlayer insulating film 306 Interlayer insulating film 308 First wiring groove 310 Second wiring groove 312 Third wiring groove 314 Fourth wiring groove 316 Fifth wiring groove 318 Sixth wiring groove 320 Seventh wiring groove 332 Plating film

Claims (8)

添加剤を含むめっき液でめっき処理を行うめっき処理装置であって、
めっき槽中に配置された被処理基板とアノードとの間に、中性濾過膜と陽イオン交換膜との積層体を、前記被処理基板側に前記中性濾過膜が位置するように配置して、当該積層体により前記めっき槽を前記被処理基板および前記添加剤を含む第1室と前記アノードを含む第2室とに隔離したことを特徴とするめっき処理装置。
A plating apparatus for performing plating with a plating solution containing an additive,
A laminate of a neutral filtration membrane and a cation exchange membrane is placed between the substrate to be treated and the anode arranged in the plating tank so that the neutral filtration membrane is located on the substrate to be treated. The plating apparatus is characterized in that the plating tank is separated into the first chamber containing the substrate to be processed and the additive and the second chamber containing the anode by the laminate.
請求項1に記載のめっき処理装置において、
前記積層体において、前記中性濾過膜と前記陽イオン交換膜とが接して設けられためっき処理装置。
The plating apparatus according to claim 1,
The plating apparatus in which the neutral filtration membrane and the cation exchange membrane are provided in contact with each other in the laminate.
請求項1または2に記載のめっき処理装置において、
前記中性濾過膜の孔径が0.5μm以下であるめっき処理装置。
In the plating processing apparatus according to claim 1 or 2,
A plating apparatus in which the pore size of the neutral filtration membrane is 0.5 μm or less.
請求項1から3いずれかに記載のめっき処理装置において、
前記めっき槽の前記第1室には、レベラ、アクセラレータ、およびサプレッサを含むめっき液が導入され、
前記積層体は、前記アクセラレータ、前記レベラ、および前記サプレッサの透過を抑制するように構成されためっき処理装置。
In the plating apparatus according to any one of claims 1 to 3,
A plating solution containing a leveler, an accelerator, and a suppressor is introduced into the first chamber of the plating tank,
The said laminated body is a plating processing apparatus comprised so that permeation | transmission of the said accelerator, the said leveler, and the said suppressor might be suppressed.
請求項1から4いずれかに記載のめっき処理装置において、
前記アノードは、銅アノードにより構成されためっき処理装置。
In the plating processing apparatus in any one of Claim 1 to 4,
The said anode is a plating processing apparatus comprised with the copper anode.
請求項5に記載のめっき処理装置において、
前記積層体は、銅イオンを透過可能に構成されためっき処理装置。
In the plating apparatus of Claim 5,
The said laminated body is a plating processing apparatus comprised so that copper ion could permeate | transmit.
添加剤を含むめっき液でめっき処理を行う工程を含む半導体装置の製造方法であって、
前記めっき処理を行う工程は、めっき槽中に配置された被処理基板とアノードとの間に、中性濾過膜と陽イオン交換膜との積層体を、前記被処理基板側に前記中性濾過膜が位置するように配置して、前記めっき槽を前記被処理基板および前記添加剤を収容する第1室と前記アノードを収容する第2室とに隔離した状態で前記被処理基板にめっき処理を施す半導体装置の製造方法。
A method of manufacturing a semiconductor device including a step of performing a plating process with a plating solution containing an additive,
The step of performing the plating treatment includes the step of placing the neutral filtration membrane and cation exchange membrane between the substrate to be processed and the anode disposed in the plating tank, and the neutral filtration on the substrate to be processed. Placing the plating substrate on the substrate to be processed in a state where the film is positioned and the plating tank is separated into the first chamber containing the substrate to be processed and the additive and the second chamber containing the anode A method for manufacturing a semiconductor device.
請求項7に記載の半導体装置の製造方法において、
前記めっき処理を行う工程により、半導体基板上を覆う絶縁膜中に設けられた凹部内に、銅膜を形成する半導体装置の製造方法。
In the manufacturing method of the semiconductor device according to claim 7,
A method of manufacturing a semiconductor device, wherein a copper film is formed in a recess provided in an insulating film covering a semiconductor substrate by the step of performing the plating process.
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