JP2008034607A - Solid-state imaging apparatus, and camera employing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a solid-state imaging apparatus having less deterioration in sensitivity and noise in a whole imaging region for performing imaging. <P>SOLUTION: The solid-state imaging apparatus is provided with a plurality of imaging pixels 20 formed in matrix on a substrate 10 and each including a photodiode 21, and a plurality sets of metal wiring 34 each formed to extend in a columnar direction on a portion between the photodiodes 21 adjacent in a row direction on a planarizing layer 41 formed on the substrate 10. On the planarizing layer 43 covering the sets of metal wiring 34, a plurality of first on-chip lenses 51 as cylindrical lenses for converging an incident light in a row direction are formed to extend in the columnar direction so as to cover each of the photodiodes 21 formed in one column. On the planarizing layer 44 covering the first on-chip lenses 51, a plurality of second on-chip lenses 52 are each formed on a position corresponding to each photodiode 21. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and a camera, and more particularly to a MOS type solid-state imaging device and a camera using the same.

  In recent years, MOS (metal-oxide-semiconductor) type solid-state imaging devices have been widely used as image input units for digital cameras including cameras incorporated in mobile phones. In the MOS type solid-state imaging device, an imaging region that receives light and performs photoelectric conversion, a peripheral circuit that extracts an image signal from the imaging region, and the like are formed on a substrate. In the imaging region, millions of imaging pixels are two-dimensionally arranged, and each imaging pixel includes a photodiode and a transistor formed on a substrate. A plurality of wiring layers in which wiring for driving each imaging pixel is embedded are formed in the imaging region.

  With recent digitalization, MOS type imaging devices are required to be smaller and have higher image quality, and the number of pixels has been increased by miniaturization of imaging pixels. However, if the image pickup pixel is simply miniaturized, the sensitivity is reduced. Therefore, by reducing the size of the transistor, reducing the number of wiring layers, and optimizing the layout of the transistors and wiring layers, the area of the light receiving portion is kept large and the sensitivity is reduced. It is necessary to suppress it.

  For example, Patent Document 1 discloses the following layout for miniaturizing a MOS-type imaging device in which an imaging pixel includes one photodiode and three transistors.

  A plurality of imaging pixels arranged in a matrix, gate wiring made of polysilicon extending in the row direction, and metal wiring extending in the column direction are formed in the imaging area of the substrate. The gate wiring includes a horizontal selection line that drives a transfer gate for transferring the signal charge photoelectrically converted by the photodiode from the photodiode to the floating diffusion portion, and a signal accumulated in the floating diffusion portion. This is a reset line for driving a reset transistor for resetting electric charges. The metal wiring is a power line commonly connected to the drain of the amplification transistor and the drain of the reset transistor for taking out an image signal from each imaging pixel, and a vertical signal line for transferring the image signal.

With this arrangement, the reset transistor and the amplification transistor can be arranged between the photodiodes adjacent in the column direction, and a metal wiring extending in the column direction can be formed on the reset transistor and the amplification transistor. The proportion of photodiodes in the imaging pixels can be increased. Further, since the metal wiring also serves as a light shielding film for the reset transistor and the amplification transistor, the metal wiring can be efficiently arranged in the imaging region.
JP 2000-273759 A

  However, the imaging pixels of the conventional MOS solid-state imaging device have the following problems. Since the metal wiring such as the power supply line is formed in the column direction, the photodiode has a rectangular shape whose length in the row direction is shorter than the length in the column direction. For this reason, a phenomenon called so-called vignetting occurs in which a part of the light beam uniformly collected by the on-chip microlens is blocked by the metal wiring and does not reach the photodiode. As a result, the amount of light reaching the photodiode is reduced, resulting in a decrease in sensitivity, and the light irregularly reflected by the metal wiring becomes a noise component, resulting in a problem that sensitivity unevenness occurs in the imaging region.

  An object of the present invention is to solve the above-described conventional problems and to realize a solid-state imaging device in which sensitivity reduction and noise generation are small in the entire imaging region.

  In order to achieve the above object, the present invention has a solid-state imaging device including an on-chip lens that uniformly converges incident light and an on-chip lens that converges only in one direction.

  Specifically, a solid-state imaging device according to the present invention includes a plurality of imaging pixels formed in a matrix on a substrate and each including a photodiode, a first planarization layer formed on the substrate, and a first A plurality of metal wirings formed in the column direction in regions between photodiodes adjacent in the row direction on the planarization layer, and formed on the first planarization layer so as to cover each metal wiring. A second planarizing layer, and a cylindrical member that is formed in the column direction so as to cover each photodiode formed in one column on the second planarization layer, and converges incident light in the row direction. A plurality of first on-chip lenses that are lenses; a third planarization layer formed on the second planarization layer so as to cover each first on-chip lens; and a third planarization layer In the corresponding position with each photodiode on Is formed, characterized in that the incident light and a plurality of second on-chip lens that condenses.

  According to the solid-state imaging device of the present invention, a plurality of first on-chip lenses, which are cylindrical lenses that converge incident light in the row direction, and a plurality of second on-chips formed so as to cover each photodiode. Since the lens is provided, it is possible to prevent the occurrence of vignetting in which the incident light is blocked by the metal wiring, and it is possible to make the light incident on the entire photodiode. Therefore, a decrease in sensitivity and an increase in noise due to light being blocked by the metal wiring can be suppressed, so that a solid-state imaging device with little sensitivity unevenness can be realized.

  The solid-state imaging device of the present invention preferably further includes a plurality of gate wirings formed in the row direction in regions between the photodiodes adjacent in the column direction on the substrate. In this case, each imaging pixel amplifies the transfer transistor that transfers the charge accumulated in the photodiode, the floating diffusion part that temporarily stores the transferred signal charge, and the signal charge that is accumulated in the floating diffusion part. And a reset transistor for resetting the signal charge accumulated in the floating diffusion portion, and a plurality of gate wirings, a horizontal selection line for driving each transfer transistor for each row, and a reset for each row A plurality of metal wirings including a power supply line for supplying a power supply voltage to each amplification transistor and each reset transistor, and a vertical signal line to which an output of each amplification transistor is connected for each column. It is preferable to contain. With such a configuration, the area of the photodiode can be increased.

  In the solid-state imaging device of the present invention, the planar shape of each photodiode is preferably a rectangular shape whose length in the row direction is shorter than the length in the column direction.

  In the solid-state imaging device of the present invention, each first on-chip lens is preferably formed of a color filter material.

  A camera according to the present invention includes the solid-state imaging device of the present invention.

  According to the solid-state imaging device according to the present invention, it is possible to realize a solid-state imaging device with less sensitivity reduction and noise generation in the entire imaging region.

  An embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows an equivalent circuit of a MOS type solid-state imaging device according to this embodiment. As shown in FIG. 1, the MOS solid-state imaging device of the present embodiment includes a plurality of imaging pixels 20 and a plurality of signal lines that connect the imaging pixels 20 to each other.

  Each imaging pixel 20 includes a photodiode 21 and three transistors. The three transistors include a transfer transistor 23 that transfers the signal charge accumulated in the photodiode 21 to the floating diffusion (FD) unit 22, an amplification transistor 24 that amplifies the signal charge accumulated in the FD unit 22, and an FD unit. And a reset transistor 25 that resets the signal charge accumulated in 22.

  The signal lines include a horizontal selection line 31 that connects the gates of the transfer transistors 23 for each row, a reset signal line 32 that connects the gates of the reset transistors 25 for each row, and sources of the amplification transistors 24 for each column. A vertical signal line 33 to be connected and a power line 34 commonly connecting the drains of all the reset transistors 25 and the drains of the amplification transistors 24.

  2A to 2C are MOS type solid-state imaging devices according to the present embodiment, FIG. 2A shows a layout pattern, FIG. 2B shows a cross-sectional configuration taken along line Ib-Ib in FIG. (C) has shown the cross-sectional structure in the Ic-Ic line | wire of (a).

  As shown in FIG. 2A, a plurality of photodiodes 21 are formed in a matrix in the imaging region 11 formed on the substrate 10. The horizontal selection line 31 and the reset signal line 32 are formed as polysilicon wirings extending in the row direction. The vertical signal lines 33 and the power supply lines 34 are formed as metal wirings extending in the column direction.

  When viewed in the cross-sectional direction, as shown in FIGS. 2B and 2C, the horizontal selection line 31 and the reset signal line 32, which are polysilicon wirings, and the horizontal selection line 31 and the reset signal are formed on the substrate 10. A first planarization layer 41 made of acrylic resin or the like covering the line 32 is formed. On the first planarization layer 41, a vertical signal line 33 made of aluminum or the like and a second planarization layer 42 that covers the vertical signal line 33 are formed. On the second planarization layer 42, a power line 34 made of aluminum or the like and a third planarization layer 43 covering the power line 34 are formed. The power supply line 34 also functions as a light-shielding film that shields the amplification transistor 24 and the reset transistor 25 formed on the substrate 10 on the side of the photodiode 21.

  On the third planarization layer 43, a first on-chip lens 51 made of an acrylic resin or the like and a fourth planarization layer 44 that covers the first on-chip lens 51 are formed. The first on-chip lens is a substantially semi-cylindrical cylindrical lens formed so as to extend in the column direction between adjacent power supply lines 34. The fourth planarization layer 44 is made of a material having a refractive index lower than that of the first on-chip lens 51 such as a fluororesin.

  A second on-chip lens 52 made of acrylic resin or the like is formed on the fourth planarization layer 54. The second on-chip lens 52 is a normal convex lens, and collects incident light uniformly.

  The function of the first on-chip lens 51 in the solid-state imaging device according to the present embodiment will be described below. Usually, each imaging pixel 20 is formed in a planar square shape. However, since it is necessary to form metal wiring extending in the column direction, the photodiodes 21 are laid out in a planar rectangular shape whose width in the row direction is shorter than the length in the column direction. For this reason, if the incident light is uniformly collected by the lens so as to enter the entire column direction of the photodiode 21, a part of the light beam enters the power supply line 34 in the row direction, and so-called vignetting occurs. End up.

  However, the solid-state imaging device of the present embodiment further condenses the light uniformly collected by the second on-chip lens 52 in the row direction by the first on-chip lens 51 that is a cylindrical lens. Therefore, the occurrence of vignetting by the power supply line 34 can be prevented, and light can be incident on the entire planar rectangular photodiode 21.

  In the present embodiment, an example in which the first on-chip lens 51 is formed of an acrylic resin has been described. However, the first on-chip lens 51 may be formed of a color filter that transmits only light in a specific wavelength region.

  Further, although an example in which an imaging pixel is configured by one photodiode and three transistors has been described, other configurations may be employed. Further, the layout of the imaging pixels and wirings may be changed.

  In order to make the sensitivity uniform, the positions of the first on-chip lens and the second on-chip lens may be shifted from the central portion and the peripheral portion of the imaging region. For example, in an optical system in which the exit pupil is located on the front side of the optical axis, the power line and the first on-chip lens are shifted toward the center of the imaging device in accordance with the chief ray angle on the imaging region, and the amount of shift is increased toward the periphery. The second on-chip lens has a larger shift amount in the horizontal and vertical directions toward the center of the image pickup apparatus, and a larger shift amount in the periphery and a smaller shift amount in the center. .

  Further, in an optical system in which the exit pupil is located on the back of the optical axis from the present apparatus, the power line and the first on-chip lens are horizontally directed toward the periphery of the present image capturing apparatus according to the chief ray angle on the image capturing area. The shift amount is increased toward the periphery, the shift amount is decreased toward the center, and the second on-chip lens is shifted toward the periphery of the image pickup apparatus in both horizontal and vertical directions. Should be arranged small.

  Since the solid-state imaging device of the present embodiment has high sensitivity and low noise, a high-sensitivity and low-noise camera can be realized by incorporating it in the camera.

  The solid-state imaging device and camera according to the present invention can realize a solid-state imaging device with less sensitivity reduction and less noise generation in the entire imaging region, and are useful as a MOS solid-state imaging device and a camera.

1 is a circuit diagram illustrating a solid-state imaging device according to an embodiment of the present invention. (A)-(c) shows the solid-state imaging device which concerns on one Embodiment of this invention, (a) is a top view, (b) is sectional drawing in the Ib-Ib line | wire of (a), (c) is sectional drawing in the Ic-Ic line | wire of (a).

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Substrate 11 Imaging area 20 Imaging pixel 21 Photodiode 22 Floating diffusion part 23 Transfer transistor 24 Amplification transistor 25 Reset transistor 31 Horizontal selection line 32 Reset signal line 33 Vertical signal line 34 Power supply line 41 1st planarization layer 42 2nd Planarization layer 43 Third planarization layer 44 Fourth planarization layer 51 First on-chip lens 52 Second on-chip lens

Claims (6)

A plurality of imaging pixels formed in a matrix on the substrate and each including a photodiode;
A first planarization layer formed on the substrate;
A plurality of metal wirings formed in the column direction in regions between the photodiodes adjacent in the row direction on the first planarization layer;
A second planarization layer formed on the first planarization layer so as to cover the metal wirings;
Each of the plurality of first lenses is a cylindrical lens that is formed in the column direction so as to cover the photodiodes formed in one column on the second planarization layer and converges incident light in the row direction. With an on-chip lens,
A third planarization layer formed on the second planarization layer so as to cover each of the first on-chip lenses;
A solid-state imaging device comprising: a plurality of second on-chip lenses that are formed at positions corresponding to the photodiodes on the third planarizing layer and collect incident light. .   The solid-state imaging device according to claim 1, further comprising a plurality of gate wirings formed in a row direction in a region between the photodiodes adjacent in the column direction on the substrate. Each of the imaging pixels amplifies the transfer transistor for transferring the charge accumulated in the photodiode, the floating diffusion part for temporarily storing the transferred signal charge, and the signal charge accumulated in the floating diffusion part. Each having an amplification transistor and a reset transistor for resetting the signal charge accumulated in the floating diffusion portion;
The plurality of gate wirings include a horizontal selection line for driving each transfer transistor for each row, and a reset signal line for driving each reset transistor for each row,
The plurality of metal wirings include a power supply line for supplying a power supply voltage to each amplification transistor and each reset transistor, and a vertical signal line to which an output of each amplification transistor is connected for each column. Item 3. The solid-state imaging device according to Item 2.   4. The solid-state imaging device according to claim 1, wherein the planar shape of each photodiode is a rectangular shape whose length in the row direction is shorter than the length in the column direction. 5.   5. The solid-state imaging device according to claim 1, wherein each of the first on-chip lenses is formed of a color filter material.   A camera comprising the solid-state imaging device according to claim 1.

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