JP2008028683A - Phase-locked oscillator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase-locked oscillator capable of detecting phase information even in a phase state without sensitivity in a dead band by generating pulses in a part other than the dead band in order to eliminate the unstable region of the sensitivity, so as to change the pulse width in proportion to the phase difference, concerning the phase-locked oscillator. <P>SOLUTION: A part of the output signal of a voltage-controlled oscillator 4 is connected to one input of a phase comparator 2 by way of a variable frequency divider 5. A reference signal is connected to the other input of the phase comparator 2 via a fixed frequency divider 1. Then, the output of the phase comparator 2 is connected to the input of the voltage control oscillator 4 via a low-pass filter 3 so as to form a loop. The variable frequency divider 5 is made to change so as to generate the pulse width in proportion to the phase difference. Then, the phase information is detected. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a phase-locked oscillator, and more particularly to a phase-locked oscillator that obtains stable sensitivity even in an unstable region of sensitivity to an input signal and eliminates the unstable region.

  The phase-locked oscillator is realized by a kind of frequency feedback type circuit of PLL (Phase-locked Loop).

  FIG. 9 is a block diagram of a conventional phase-synchronized oscillator. In the figure, 1 is a 1 / N frequency divider, 2 is a phase detector (PD), 3 is a low-pass filter (LPF), and 4 is a voltage-controlled oscillator (VCO). It is. The input signal is compared with the output signal by the phase comparator (PD) 2 via the 1 / N frequency divider 1, and is an error signal smoothed by the low-pass filter (LPF) 3, and is a voltage controlled oscillator (VCO). 4 is applied, and negative feedback is applied so that the phase difference becomes zero.

  FIG. 10 is a charge pump circuit diagram used for the output of the phase comparator (PD) 2. In the figure, a charge pump circuit inputs an error signal of a phase comparator (PD) 2 that outputs an error signal corresponding to a phase difference, and outputs a three-state output signal. It is a 3-state output of H pulse for charging, L pulse for discharging, and Z (high impedance) for holding.

FIG. 11 is a time chart showing the relationship between the phase difference of the input signal and the output pulse according to the prior art. In the figure, a phase error pulse proportional to the phase difference is output with a linear output characteristic. In the phase synchronization process, the pulse width of the output of the phase comparator (PD) 2 is gradually narrowed and converges to a phase difference of 0 in a steady state. However, in the vicinity of the phase difference of 0 in FIG. 11, the upper pulse and the lower pulse are interchanged, and the following states occur depending on the delay state of the circuit elements and the circuit configuration method.
(1) Linear output characteristics: The pulse width is proportional to the phase difference, and the slope of the output characteristics does not change at any phase difference.
(2) Output characteristic with dead band: There is a dead band where no output pulse is generated in the vicinity of a phase difference of 0, and there is a portion where the slope of the output characteristic becomes flat.
(3) Output characteristics having a high sensitivity band: There is a high sensitivity band where the upper and lower output pulses overlap in the vicinity of a phase difference of 0 and the output characteristics are inclined.

  FIG. 12 is a time chart showing the occurrence of a high sensitivity band according to the prior art. In the figure, in a PLL that generates an arbitrary frequency by an external signal, upper and lower output pulses that are generated in the vicinity of 0 in phase difference between a reference signal and a comparison signal in a phase comparator (PD) 2 constituting the PLL. The mechanism of the part (high sensitivity band) which overlaps is shown. That is, when the phase difference between the reference signal and the comparison signal is sufficiently positive, a voltage proportional to the upper pulse width is generated. On the other hand, when the phase difference between the reference signal and the comparison signal is sufficiently negative, the voltage is lower. A voltage proportional to the side pulse width is generated. In the high sensitivity band, when the phase difference between the reference signal and the comparison signal is near 0, voltages proportional to the upper pulse width and the lower pulse width are overlapped. When the inclination of the phase comparator (PD) 2 is Kd, the sensitivity of the high sensitivity band is 2 · Kd.

  FIG. 13 is an output characteristic diagram of a phase comparator according to the prior art. In the figure, (a) in the case of the dead band example, a portion (dead band) where the slope of the output characteristic is flat occurs in the vicinity of the phase difference 0, and (b) in the case of the high sensitivity band example, the phase difference near 0 is obtained. A portion (high sensitivity band) where the slope of the output characteristic is raised occurs. That is, if there is an unstable region of sensitivity, the output will not be proportional to the phase difference, and the output characteristics will be S-shaped characteristics and inverted S-shaped characteristics.

  FIG. 14 is a time chart of the phase comparator according to the prior art in a ten-frequency division synchronization state. In the figure, in the dead zone where the phase difference between the comparison signal and the reference signal is near 0, the output signal is not output from the phase comparator (PD) 2 even if the reference signal is shifted.

  FIG. 15 is a block diagram showing a countermeasure against an unstable region of sensitivity according to the prior art. In this circuit configuration, a method is used in which a capacitor is discharged by a leak resistor, a small pulse in the charging direction is always generated from a charge pump in a steady state, and the operating point at the steady state is shifted from an unstable region.

  However, in this general method, since the operating point is merely shifted from the unstable region of sensitivity, the unstable region of sensitivity itself is not eliminated. For this reason, there are problems such as the pulling operation becomes unstable if it passes through an unstable region at the time of pulling, and the input / output phase error increases if it passes through an unstable region when following an input with a large phase change. It was.

As another conventional technique, in a phase synchronization circuit for data separation, a dead band occurs because the SW does not operate at a minimum pulse exceeding the response characteristic of the SW used for charge / discharge of the charge pump. In order to cope with this dead zone, the minimum pulse width of SW is ensured to be equal to or more by giving the time difference To to clear the FFs constituting the phase comparator, and switching is performed within the response band. Has proposed a circuit that overlaps the upper and lower output pulses by To to avoid the dead zone. (For example, see Patent Document 1)
However, this prior art also improves the dead zone due to the minimal pulse exceeding the SW response speed, and corresponds to the dead zone caused by the delay of the SW itself and the delay generated in the logic circuit before the SW. Absent.
Japanese Patent Laid-Open No. 02-021724

  In a phase-locked oscillator, if there is an unstable region of sensitivity, the phase comparator does not respond to the phase change in the dead zone, so the loop gain decreases, and in the high sensitivity zone, the loop gain increases. The loop does not operate stably, such as when a peak occurs in the characteristics. In some cases, the loop may oscillate.

  Also, in the dead zone, small signals such as noise (amplitude that falls within the unstable region of sensitivity) will not respond to the input signal. Therefore, when the VCO noise is compressed by a loop, feedback is not effective and output noise is reduced. There was a problem that said it would get worse.

  In order to solve the above-described conventional problems, the present invention generates pulses in portions other than the unstable region by changing the frequency division number. Since the pulse width changes in proportion to the phase difference, phase information can be detected even in a phase state where no sensitivity is obtained in the dead zone, and in the high sensitivity zone, the phase with reduced loop gain change is detected. It is an object to provide a synchronous oscillator.

  A first invention for solving the above problem is that a part of an output signal of a voltage controlled oscillator is connected to one input of a phase comparator via a variable frequency divider, and the input signal is connected to a fixed frequency divider. Is connected to the other input of the phase comparator, and the output of the phase comparator is connected to the input of the voltage controlled oscillator via a low pass filter to form a loop and change the variable frequency divider Then, a pulse width proportional to the phase difference is generated to detect phase information, and an error signal including a pulse is smoothed by the low-pass filter and input to the voltage controlled oscillator.

  According to the first aspect of the present invention, it is possible to provide a phase-locked oscillator that can obtain stable sensitivity even in an unstable region and eliminate the unstable region, and can also control the phase comparison sensitivity of the unstable region part. .

  According to a second aspect of the present invention, a part of the output signal of the voltage controlled oscillator is connected to one input of the phase comparator via a fixed frequency divider, and the input signal is connected to the phase comparator via the variable frequency divider. Connected to the other input, the output of the phase comparator is connected to the input of the voltage controlled oscillator through a low pass filter to form a loop, and the variable frequency divider is changed to be proportional to the phase difference A pulse width is generated to detect phase information, and an error signal including a pulse is smoothed by the low-pass filter and input to the voltage controlled oscillator.

  According to the second aspect of the present invention, it is possible to provide a phase-locked oscillator that can obtain stable sensitivity even in an unstable region of sensitivity, eliminate the unstable region, and can also control the phase comparison sensitivity of the unstable region part. .

  According to a third invention, in the phase-locked oscillator according to the first invention or the second invention, the variable frequency divider has a plurality of repetitive frequency division patterns formed by combinations of different frequency division numbers.

  According to the third aspect of the invention, it is possible to provide a phase-locked oscillator that can cope with a dead band having a width corresponding to the number of arbitrary clocks.

  According to a fourth invention, in the phase-locked oscillator according to the first invention or the second invention, the variable frequency divider is configured by a programmable logic array.

  According to the fourth aspect of the invention, the phase-locked oscillator can be provided by using the variable frequency divider that can be programmed freely by the user.

  As described above, according to the phase-locked oscillator of the present invention, a stable sensitivity can be obtained even in an unstable region and the unstable region can be eliminated. Furthermore, since the phase comparison sensitivity of the unstable region can be controlled, the noise characteristics and the pull-in characteristics can be verified and fed back by simulation. As a result, it is possible to stabilize the loop and reduce the output noise, which greatly contributes to the improvement of the performance of a device using a clock.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a phase-locked oscillator according to an embodiment of the present invention. In the figure, (a) shows a case where a variable frequency divider is inserted on the comparison side, and (b) shows a case where a variable frequency divider is inserted on the reference side.
(A) When a variable frequency divider is inserted on the comparison side, the phase-locked oscillator is configured such that a part of the output signal of the voltage controlled oscillator (VCO) 4 is transferred to the phase comparator (VCO) 5 via the variable frequency divider 5. PD) 2 is connected to one input, and the input signal is connected to the other input of the phase comparator (PD) 2 through a fixed frequency divider (1 / N), and the phase comparator (PD) 2 A loop is formed by connecting the output to the input of a voltage controlled oscillator (VCO) 4 through a low pass filter (LPF) 3.

This phase-locked oscillator operates by changing the variable frequency divider 5 to generate a pulse width proportional to the phase difference, detecting phase information by the phase comparator (PD) 2, and by a low-pass filter (LPF) 3. The error signal including the pulse is smoothed and input to the voltage controlled oscillator (VCO) 4. The voltage controlled oscillator is controlled by a smoothed error signal and applies negative feedback so that the phase difference becomes zero.
(B) When a variable frequency divider is inserted on the reference side, the phase-locked oscillator is configured such that a part of the output signal of the voltage controlled oscillator (VCO) 4 passes through the fixed frequency divider (1 / N) 1. Is connected to one input of the phase comparator (PD) 2, and the input signal is connected to the other input of the phase comparator (PD) 2 via the variable frequency divider 5, and the phase comparator (PD) 2 Is connected to the input of a voltage controlled oscillator (VCO) 4 via a low pass filter (LPF) 3 to form a loop.

  This phase-locked oscillator operates by changing the variable frequency divider 5 to generate a pulse width proportional to the phase difference, detecting phase information by the phase comparator (PD) 2, and by a low-pass filter (LPF) 3. The error signal including the pulse is smoothed and input to the voltage controlled oscillator (VCO) 4. The voltage controlled oscillator is controlled by a smoothed error signal and applies negative feedback so that the phase difference becomes zero.

  Thus, in the present invention, the position at which the fixed frequency divider (1 / N) 1 and the variable frequency divider 5 are inserted may be on either the reference side or the comparison side.

  FIG. 2 is a configuration example of a variable frequency divider applied to the present invention and a program flow diagram. In the figure, the variable frequency divider 5 can be configured by a programmable logic array. For example, the programmable logic array can be configured by an FPGA (Field Programmable Gate Array). It is programmed to input a signal to the clock of the IC, divide the clock by changing the frequency division number, and output it. In this example, the setting of the variable frequency divider 5 is 9 division-11 division-11 division-11 division-9, and a count output of this repetition period is created.

  FIG. 3 is a time chart (Example 1) of the phase synchronization state in one embodiment of the present invention. The present invention is characterized by the frequency dividing method of the frequency divider, and here, a frequency divider of 10 is used. The average frequency division number is the same as the conventional one, but is characterized by the count number and combination of each frequency division. The phase information of 1 clock before and after the synchronous phase is obtained with respect to the synchronous phase, and the setting of the divider repeats 9-11-11-9 counts. It is going. In this example, it is possible to cope with a dead band (high sensitivity band) having a width of 2 clocks. The output characteristic of the phase comparator (PD) 2 has sensitivity even in the conventional dead zone. In the high sensitivity zone, rapid sensitivity can be improved gradually.

  FIG. 4 is a time chart (Example 2) of the phase synchronization state in one embodiment of the present invention. In the second embodiment, the combination of frequency divisions is changed and the sensitivity is higher than that in the first embodiment shown in FIG. 3, and only one clock before and after the synchronization phase is −1, +1. In the configuration for obtaining the phase information, the setting of the frequency divider repeats 8-12 counts. Even in this example, a dead zone (high sensitivity zone) having a width of 2 clocks can be handled.

  FIG. 5 is a time chart (Example 3) of the phase synchronization state in one embodiment of the present invention. The third embodiment is obtained by shifting two clocks before and after the combination of frequency division, and obtains phase information only for two clocks before and after the synchronization phase, ie, 0, -2, 0, +2... With respect to the synchronization phase. The frequency divider setting repeats 8-12-12-8 counts. Even in this example, it becomes possible to cope with a dead band (high sensitivity band) with a width of 4 clocks.

  FIG. 6 is a time chart (Example 4) of the phase synchronization state in one embodiment of the present invention. In the fourth embodiment, the sensitivity is higher than that of the third embodiment, which is shifted by two clocks before and after the combination of the frequency divisions. The phase information is obtained only for two clocks before and after the synchronization phase, -2, +2, -2, +2,... With respect to the synchronization phase, and the frequency divider setting is repeated 6-14-14-6 counts. It is going. Even in this example, it becomes possible to cope with a dead band (high sensitivity band) with a width of 4 clocks.

  FIG. 7 is a time chart (Example 5) of the phase synchronization state in one embodiment of the present invention. The fifth embodiment is an embodiment in which the sensitivity is controlled by a combination of frequency divisions, and 0, -1, 0, +1, 0, 0, 0, 0... Before and after the synchronization phase with respect to the synchronization phase. In this configuration, phase information is obtained for only one clock, and the frequency of -1, + 1 count is reduced. The setting of the frequency divider is to repeat 9-11-9-11-10-10-10-10 count. In this example, a dead band (high sensitivity band) with a width of 2 clocks can be supported. That is, Example 5 adjusts the amount of improvement in the dead zone (the same applies to the high sensitivity zone), and is a method that relaxes the effectiveness. When the effectiveness of Example 1 is set to 1, this Example 5 is , 0.5 times weaker. Thus, the effect is determined by the number and width of correction pulses.

  FIG. 8 is an output characteristic diagram of the phase comparator according to the present invention. In the figure, (a) in the case of the dead zone, according to the present invention, the sensitivity can be obtained even in the portion (dead zone) where the slope of the output characteristic is flat in the vicinity of the phase difference of 0 in the prior art. Further, (b) in the case of the high sensitivity band example, according to the present invention, the abrupt sensitivity is moderated in the portion (high sensitivity band) where the slope of the output characteristic that occurs near the phase difference of 0 in the prior art is high. Can improve.

  The following additional notes are further disclosed with respect to the embodiment including the above examples.

(Supplementary note 1) A part of the output signal of the voltage controlled oscillator is connected to one input of the phase comparator via the variable frequency divider, and the input signal is connected to the other side of the phase comparator via the fixed frequency divider. And connecting the output of the phase comparator to the input of the voltage controlled oscillator via a low-pass filter to form a loop, and changing the variable frequency divider to change the pulse width proportional to the phase difference The phase-locked oscillator is characterized by detecting phase information, smoothing an error signal including a pulse by the low-pass filter, and inputting the error signal to the voltage-controlled oscillator.
(Supplementary Note 2) A part of the output signal of the voltage controlled oscillator is connected to one input of the phase comparator via a fixed frequency divider, and the input signal is connected to the other side of the phase comparator via a variable frequency divider. And connecting the output of the phase comparator to the input of the voltage controlled oscillator via a low-pass filter to form a loop, and changing the variable frequency divider to change the pulse width proportional to the phase difference The phase-locked oscillator is characterized by detecting phase information, smoothing an error signal including a pulse by the low-pass filter, and inputting the error signal to the voltage-controlled oscillator.
(Supplementary Note 3) In the phase-locked oscillator according to Supplementary Note 1 or Supplementary Note 2, the variable frequency divider has a plurality of repetitive frequency division patterns formed by combinations of different frequency division numbers. Oscillator.
(Supplementary Note 4) In the phase-locked oscillator according to Supplementary Note 3, the repetitive frequency dividing pattern includes 0, -1, 0, +1,... And phase information of one clock before and after the synchronous phase with respect to the synchronous phase. The phase-locked oscillator according to claim 1, wherein the setting of the divider by 10 is such that 9-11-11-9 counts are repeated.

  (Supplementary Note 5) In the phase-locked oscillator according to Supplementary Note 3, the repetitive frequency dividing pattern is configured to obtain phase information only for −1, +1... The phase-locked oscillator is characterized in that the setting of the frequency divider is to repeat 8-12 counts.

  (Supplementary Note 6) In the phase-locked oscillator according to Supplementary Note 3, the repetitive frequency division pattern obtains phase information only for two clocks before and after the synchronous phase, with respect to the synchronous phase, 0, -2, 0, +2. A phase-locked oscillator having a configuration in which the setting of the frequency divider of 10 is to repeat 8-12-12-8 counts.

  (Supplementary note 7) In the phase-locked oscillator according to supplementary note 3, the repetitive frequency dividing pattern has phase information of -2, +2, -2, +2,. A phase-locked oscillator having a configuration in which the setting of the divider by 10 is to repeat 6-14-14-6 counts.

  (Supplementary Note 8) In the phase-locked oscillator according to Supplementary Note 3, the repetitive frequency dividing pattern has a synchronization phase of 0, -1, 0, +1, 0, 0, 0, 0. The phase is characterized in that the phase information is obtained only for the front and rear clocks, and the setting of the divider by 10 is such that 9-11-9-11-10-10-10-10 count is repeated. Synchronous oscillator.

  (Additional remark 9) The phase synchronous oscillator of Additional remark 1 or Additional remark 2 WHEREIN: The said variable frequency divider is comprised by a programmable logic array, The phase synchronous oscillator characterized by the above-mentioned.

  Since the present invention provides a phase-locked oscillator that can be stably synchronized with an input signal, it can be used particularly for a clock or a local oscillator in a wireless device that requires a stable output with low noise. This greatly contributes to higher performance.

It is a block diagram of the phase-locked oscillator in one Embodiment of this invention. It is a flow diagram of a configuration example and a program of a variable frequency divider applied to the present invention. It is a time chart (Example 1) of the phase-synchronization state in one Embodiment of this invention. It is a time chart (Example 2) of the phase-synchronization state in one Embodiment of this invention. It is a time chart (Example 3) of the phase-synchronization state in one Embodiment of this invention. It is a time chart (Example 4) of the phase-synchronization state in one Embodiment of this invention. It is a time chart (Example 5) of the phase-synchronization state in one Embodiment of this invention. It is an output characteristic view of a phase comparator according to the present invention. It is a block diagram of the phase-locked oscillator by a prior art. It is a charge pump circuit diagram used for the output of a phase comparator. It is a time chart which shows the relationship between the phase difference of the input signal by conventional technology, and an output pulse. It is a time chart which shows generation | occurrence | production of the high sensitivity band by a prior art. It is an output characteristic figure of the phase comparator by a prior art. 5 is a time chart of a phase comparator according to the prior art in a state of being divided by ten. It is a block diagram which shows the sensitivity unstable area countermeasure by a prior art.

Explanation of symbols

1 1 / N frequency divider 2 Phase comparator (PD)
3 Low-pass filter (LPF)
4 Voltage controlled oscillator (VCO)
5 Variable frequency divider

Claims (4)

Part of the output signal of the voltage controlled oscillator is connected to one input of the phase comparator via a variable frequency divider, and the input signal is connected to the other input of the phase comparator via a fixed frequency divider And forming a loop by connecting the output of the phase comparator to the input of the voltage controlled oscillator via a low pass filter,
The variable frequency divider is changed to generate a pulse width proportional to a phase difference to detect phase information, and an error signal including a pulse is smoothed by the low-pass filter and input to the voltage controlled oscillator. A phase-locked oscillator. Part of the output signal of the voltage controlled oscillator is connected to one input of the phase comparator via a fixed divider, and the input signal is connected to the other input of the phase comparator via a variable divider And forming a loop by connecting the output of the phase comparator to the input of the voltage controlled oscillator via a low pass filter,
The variable frequency divider is changed to generate a pulse width proportional to a phase difference to detect phase information, and an error signal including a pulse is smoothed by the low-pass filter and input to the voltage controlled oscillator. A phase-locked oscillator. The phase-locked oscillator according to claim 1 or 2,
The variable frequency divider includes a plurality of repetitive frequency division patterns formed by combinations of different frequency division numbers. The phase-locked oscillator according to claim 1 or 2,
The variable frequency divider includes a programmable logic array.

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