JP2008028651A - Signal processor and signal processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable transmission when a digital video signal of only one channel is input or when input digital video signals of two channels are different in frame rate or format, at the time of transmission by multiplexing the input digital signals of two channels. <P>SOLUTION: Provided is a rewriting means 15 of rewriting a predetermined word for word synchronization in an input digital video signal of a first channel into another word, and the digital video signal of the first channel which has the specified word rewritten into the other word by the rewriting means 15 and a digital video signal of the second channel are multiplexed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a signal processing apparatus and a signal processing method for multiplexing and transmitting an input two-channel serial digital video signal, and more particularly, when a single-channel serial digital video signal is input or input. The present invention relates to a two-channel serial digital video signal that can be transmitted even when the frame rate and format are different.

  The SDI (Serial Digital Interface) standard for serial transmission of high-definition resolution (HD) parallel digital video signals at high speed is the SMPTE (Society of Motion Picture and Television Engineers) in the United States. Has been standardized by.

  SMPTE292M converts a high-definition parallel digital video signal from SMPTE274M etc. into a serial digital video signal (HD-SDI signal) with a bit rate of 1.485 Gbps or 1.485 Gbps / 1.001 using a single cable. It is a standard for transmission.

  SMPTE372M is based on SMPTE292M, 1920 × 1080 / 50P, 60P / 4: 2: 2/10 bits, 1920 × 1080 / 24P, 30P, 50I, 60I / 4: 4: 4/10 bits, 12 bits, etc. This is a standard for serial transmission of parallel digital video signals as two channels of HD-SDI signals at a bit rate of 2.970 Gbps or 2.970 Gbps / 1.001 using two cables.

  Also, in recent years, a signal multiplexing format and coaxial in which two channels of HD-SDI signals within the range that can be transmitted by SMPTE 372M are multiplexed and serially transmitted at a bit rate of 2.970 Gbps or 2.970 Gbps / 1.001 using one coaxial cable. The standard of the interface physical layer has been standardized as SMPTE 424M and 425M (see Non-Patent Documents 1 and 2). Also, the standard of the optical interface physical layer is being standardized as SMPTE 297M (see Non-Patent Document 3).

SMPTE STANDARD for Television and Digital Cinema SMPTE 424M-200x SMPTE STANDARD for Television and Digital Cinema SMPTE 425M-200x SMPTE STANDARD for Television SMPTE 297M-200x

  However, in the SMPTE 424M and 425M standards, when the HD-SDI signal of only one channel is input or when the frame rate and format of the input two-channel HD-SDI signal are different, the HD-SDI signal is multiplexed. Cannot be transmitted.

  In view of the above-described points, the present invention multiplexes and transmits an input two-channel digital video signal, when a digital video signal of only one channel is input, or a frame of an input two-channel digital video signal. Even when the rate and format are different, it is an object to enable transmission in the same manner as when two-channel digital video signals having the same frame rate and format are input.

  In order to solve the above-mentioned problem, a first signal processing apparatus according to the present invention provides two channels of a digital video signal in which at least a video signal section and a predetermined word section for word synchronization are arranged in time series. In a signal processing apparatus for inputting a number of minutes and multiplexing the input digital video signals for two channels, the signal processing apparatus comprises rewriting means for rewriting the predetermined word in the input digital video signal of the first channel to another word. The digital video signal of the first channel and the digital video signal of the second channel that are rewritten to another word by means are multiplexed.

  The first signal processing method according to the present invention inputs and inputs two channels of digital video signals in which at least video signal sections and predetermined word sections for word synchronization are arranged in time series. In the signal processing method for multiplexing the digital video signals for two channels, a first step of rewriting the predetermined word in the input digital video signal of the first channel to another word, and this first step And a second step of multiplexing the digital video signal of the first channel rewritten to another word and the digital video signal of the second channel.

  The above invention relates to the signal processing on the side of multiplexing and transmitting the input 2-channel digital video signal, and the input digital video signal of the first channel is changed from a predetermined word for word synchronization to another word. And multiplexed with the digital video signal of the second channel.

  Since the word for word synchronization in the digital video signal of the first channel is rewritten in this way, the side receiving the multiplexed digital data detects the rewritten word to detect the first channel. Digital video signals can be distinguished. Therefore, even when a digital video signal of only one channel is input to the transmitting side, the digital video signal can be distinguished and reproduced on the receiving side, and a frame of a two-channel digital video signal input to the transmitting side. Even when the rate and format are different, the receiving side can distinguish the digital video signal of the first channel from the digital video signal of the second channel and reproduce the digital video signal of each channel.

  As a result, even when a digital video signal of only one channel is input or when the frame rate and format of the input two-channel digital video signal are different, a two-channel digital video signal having the same frame rate and format is input. Transmission can be performed as in the case.

  Next, a second signal processing apparatus according to the present invention is a digital signal obtained by multiplexing a digital video signal in which at least a video signal section and a predetermined word section for word synchronization are arranged in time series for two channels. In a signal processing apparatus that reproduces the digital video signal of each channel from the digital data in which the predetermined word in the digital video signal of the first channel is rewritten with another word, the digital data A detecting means for detecting another word, and a write-back means for writing the another word detected by the detecting means back to the predetermined word, based on the other word detected by the detecting means. The first channel digital video signal and the second channel digital video signal are distinguished from each other. Characterized by reproducing the digital video signal.

  Also, the second signal processing method according to the present invention is a digital data obtained by multiplexing two channels of digital video signals in which at least video signal sections and predetermined word sections for word synchronization are arranged in time series. In the signal processing method for reproducing the digital video signal of each channel from the digital data in which the predetermined word in the digital video signal of the first channel is rewritten to another word, A first step of detecting the second word, a second step of writing back the second word detected in the first step to the predetermined word, and a second word detected in the second step. The digital video signal of the first channel and the digital video signal of the second channel are distinguished based on the And having a third step of reproducing the Rubideo signal.

  The present invention relates to signal processing on the side that receives digital data multiplexed by the first signal processing apparatus and signal processing method described above, and detects the rewritten word to detect digital video of the first channel. Signals can be distinguished. Therefore, even when a digital video signal of only one channel is input to the transmission side, the digital video signal can be distinguished and reproduced, and the frame rate and format of the two-channel digital video signal input to the transmission side. Even if they are different, the digital video signal of each channel can be reproduced by distinguishing the digital video signal of the first channel and the digital video signal of the second channel.

  As a result, even when a digital video signal of only one channel is input or when the frame rate and format of the input two-channel digital video signal are different, a two-channel digital video signal having the same frame rate and format is input. Transmission can be performed as in the case.

  According to the present invention, when the input 2-channel digital video signal is multiplexed and transmitted, the digital video signal of only one channel is input, or the frame rate and format of the input 2-channel digital video signal are different. Even when they are different from each other, an effect is obtained that transmission can be performed in the same manner as when two-channel digital video signals having the same frame rate and format are input.

Embodiments of the present invention will be described below.
First, the format, system, and standard related to the digital video signal transmitted in this embodiment will be described.
<Signal format>
Standards for digital video equipment for broadcasting stations include SMPTE 244, which is a standardized standard-definition (SD) composite video signal, SMPTE125M, which is a standardized standard-definition component video signal, There exists SMPTE 274M, which is a standard for digitizing high definition video signals (HD).

  FIG. 1 shows the format of a parallel digital video signal according to these standards. The luminance signal (Y) / color difference signal (Cb / Cr) is quantized with 10 bits (or 8 bits), respectively. For each horizontal line, a section of a timing reference signal EAV (End of Active Video), a section of line number data LN, a section of an error detection code CRCC, and a horizontal blanking period (auxiliary data / undefined word data) ), A timing reference signal SAV (Start of Active Video) section, and an active video section (video signal section) are sequentially arranged in time series.

  The timing reference signals SAV and EAV are 4 words of 3FFh, 000h, 000h, and XYZh, respectively. Of these, the first three words (3FFh, 000h, 000h) are for establishing word synchronization and horizontal synchronization. The last one word (XYZh) is used to identify the first field / second field of the same frame, or to identify SAV and EAV.

  Digital video signals according to these standards are parallel digital video signals, but SDI (Serial Digital Interface) exists as a standard for serial transmission of such parallel digital video signals with a single cable at high speed. (For standard-definition video signals, there is SD-SDI by SMPTE259M, and for high-definition resolution video signals, there is HD-SDI by SMPTE292M).

  In this SDI, a luminance signal (Y) and a color difference signal (Cb / Cr) are multiplexed in the order of Cb / Cr, Y, Cb / Cr, Y, Cb / Cr, Y, Cb / Cr, Y,. The digital video signal is parallel / serial converted and scrambled, converted into an electrical or optical signal and transmitted. On the receiving side, the reverse processing is performed to reproduce the parallel digital video signal.

Here, scramble means that an input serial signal is regarded as a polynomial, and a ninth-order primitive polynomial X ⁹ + X ⁴ +1
By dividing the data sequentially and transmitting the resulting quotient, the mark ratio of transmission data (ratio of 1 and 0) is statistically halved. This scrambling also has the meaning of signal encryption using a primitive polynomial. The transmitting device further divides this quotient by (X + 1) to transmit the data as polarity-free (having the same information for the data and its inverted data).

The descrambling in the receiving apparatus is to reproduce the original serial signal by multiplying the received serial signal by (X + 1) and further multiplying by the primitive polynomial X ⁹ + X ⁴ +1.

<1080 / 50P, 60P signal>
Current HDTV signals are 1080 / 50I, 60I, interlace (interlaced scanning), while next-generation HDTV signals are 1080 / 50P, 60P, progressive (sequential scanning). The format of parallel 1080 / 50P, 60P signals is determined by SMPTE274M,
(1) Number of active samples; 1920 samples / line (2) Number of active lines; 1080 lines / frame (3) Frame rate; 50 Hz, 60 Hz or 60 Hz / 1.001 (progressive)
(4) Sampling frequency: 148.5 MHz or 148.5 MHz / 1.001
(5) Number of quantization bits: 8 bits or 10 bits (or 12 bits)
It is.
The parallel interface is 8 bits × 3 = 24 bits or 10 bits × 3 = 30 bits in the RGB system, and 8 bits × 2 = 16 bits or 10 bits × 2 = 20 bits in the Y, Cb / Cr system.
Currently, 10-bit quantization is common, but the demand for 12-bit quantization has become stronger due to the demand for higher image quality in the future.

<1080 / 24P-30P / 4: 4: 4 / 10-bit, 12-bit D-Cinema signal>
D-Cinema is an abbreviation for Digital-Cinema (also called E-Cinema as an abbreviation for Electric-Cinema). The D-Cinema signal is used to realize film shooting at a movie production site with an HD quality VTR, and thereby can greatly reduce movie production costs and movie distribution costs.
The D-Cinema signal format is being standardized as SMPTE481-1M.
(1) Number of active samples; 2048 samples / line (2) Number of active lines; 1080 lines / frame (3) Frame rate; 24 Hz
(4) Sampling frequency: 74.25 MHz
(5) Number of quantization bits: 12 bits.
The parallel interface is 12 bits × 3 = 36 bits in the RGB system. A mapping format for serial transmission using Dual Link 292M is defined in SMPTE 372M-200x that is currently being revised.

<Camera transmission system>
In a broadcasting station camera system, a subject is generally photographed by a plurality of cameras. At this time, the video signal from the camera is a Y, Cb / Cr signal or RGB signal in the above signal format, and is transmitted to the camera control unit or VTR. For the Y, Cb / Cr system, the transmission rate is 270 Mbps for the D1 (component SD-SDI) signal and 1.485 Gbps or 1.485 Gbps / 1.001 for the HD-SDI signal. On the other hand, in order to know what scene the other camera is shooting at the time of shooting, the image of the other camera is displayed on the monitor screen of the camera. This is called return video and is transmitted from the camera control unit or VTR to the camera. Since the return video does not necessarily have high image quality, it is a signal compressed by MPEG or the like, and has a transmission capacity of several Mbps to several hundred Mbps. In addition, a prompter signal for projecting the document on the monitor is also transmitted for the announcer. This is also a relatively small transmission capacity of about several Mbps.
In recent years, there has been an increasing demand for sending an HD signal from a CCU as a return video to the camera, and further sending an HD signal from another camera synchronized with the system from the CCU. This second channel is called the trunk line.
The camera is controlled by the camera control unit, and all the cameras, the camera control unit, and the VTR are operated in synchronization with the system clock.

<SMPTE 3Gbps standard>
The transmission rate of the HD-SDI signal by SMPTE292M is 1.485 Gbps or 1.485 Gbps / 1.001, but based on SMPTE292M, 1920 × 1080 / 50P, 60P / 4: 2: 2/10 bits, 1920 × 1080 / 24P, 30P, 50I, 60I / 4: 4: 4 / 10-bit, 12-bit parallel digital video signals for 2 channels of HD-SDI signals, bit rate 2.970 Gbps using two cables Alternatively, SMPTE 372M exists as a standard for serial transmission at 2.970 Gbps / 1.001.

  Also, in recent years, a signal multiplexing format and coaxial in which two channels of HD-SDI signals within the range that can be transmitted by SMPTE 372M are multiplexed and serially transmitted at a bit rate of 2.970 Gbps or 2.970 Gbps / 1.001 using one coaxial cable. Interface physical layer standards have been standardized as SMPTE 424M and 425M. As for the signal multiplex format, two types, a direct mapping format unique to G company that proposed a standard, and a multiplex format compatible with SMPTE 372M are defined, and are identified by a format ID. Channel coding is the same scramble system as the current HD-SDI. The coaxial physical layer standard is similar to SMPTE292M, which is a coaxial standard for HD-SDI.

  However, in the SMPTE 424M and 425M standards, when the HD-SDI signal of only one channel is input or when the frame rate and format of the input two-channel HD-SDI signal are different, the HD-SDI signal is multiplexed. Cannot be transmitted.

  Therefore, in this embodiment, the transmission system is compliant with SMPTE 424M and 425M, and when the HD-SDI signal of only one channel is input, or the frame rate and format of the input two-channel HD-SDI signal are different. In this case, a transmission system that enables transmission in the same manner as when two-channel HD-SDI signals having the same frame rate and format are input will be described.

  FIG. 2 is a diagram showing an overall configuration of a transmission system to which the present invention is applied. In this transmission system, on the transmission side, HD-SDI signals for two channels input from the outside are multiplexed and scrambled by a signal processing device 1 to be sent from a coaxial driver or electro-optical converter 2 to one coaxial cable or optical fiber 3. In the receiving side, the serial digital data received by the coaxial receiver or the opto-electric converter 4 is descrambled by the signal processing device 5 to reproduce the HD-SDI signal of each channel. Except for the parts described below, this is compliant with SMPTE 424M and 425M.

  FIG. 3 is a block diagram illustrating a configuration of the signal processing apparatus 1 on the transmission side. The HD-SDI signals of the respective channels input to the input ports 11 and 12 of the signal processing device 1 are converted into parallel digital video signals by the serial / parallel conversion circuits 13 and 14 respectively, and then the word rewriting / signal generation unit 15. Sent to.

The word rewriting / signal generating unit 15 performs the following processes (1) to (3).
(1) HD-SDI signal of the first channel (when HD-SDI signals for two channels are input, for example, the HD-SDI signal is determined in advance such as the input port 11 side, and will be described later. Of the timing reference signal SAV / EAV in the parallel digital video signal converted from the HD-SDI signal when the HD-SDI signal of only one channel is detected in (2). Of these, three words (3FFh, 000h, 000h) (see FIG. 1) for establishing word synchronization and horizontal synchronization are rewritten to words using another prohibition code.

  That is, in the direct mapping method defined in Chapter 3 of SMPTE425M, 3FFh, 000h, 000h is rewritten to 3FEh, 001h, 001h from the prohibited code using, for example, 3FEh and 001h. Also, in Mapping of 2 × SMPTE-292M HD-SDI interfaces specified in Chapter 4 of SMPTE425M, 3FFh, 3FFh, 000h, 000h, 000h, 000h are converted to 3FEh, 3FEh, 001h, 001h, 001h using 3FEh and 001h. Rewrite to 001h, 001h. (Using 3FEh and 001h is merely an example, and other prohibited codes may be used.)

(2) Whether or not HD-SDI signals for two channels are input to the signal processing device 1 is determined by detecting a timing reference signal SAV / EAV (see FIG. 1) or the like. When it is detected that an HD-SDI signal of only one channel is input, appropriate signals are stored in the timing reference signal SAV / EAV section and the active video section (see FIG. 1), respectively (for example, 3FFh, 000h, 000h, XYZh are stored in the SAV / EAV section, 040h is stored as R, G, B, Ych and 200h is stored as Cb / Crch in the active video section, or A parallel digital video signal (which stores a signal having the same value as that of the first channel) is generated as a parallel digital video signal of the second channel. Since there is no second channel, the first channel is copied to the second channel. This is stored as auxiliary data.

(3) When HD-SDI signals for two channels are input, assuming that bit synchronization is established between the HD-SDI signal of the first channel and the HD-SDI signal of the second channel, 1 Whether the frame rate and format of the parallel digital video signal converted from the HD-SDI signal of the channel and the parallel digital video signal converted from the HD-SDI signal of the second channel are the same Detection is based on the reference signal SAV / EAV and the format ID in the auxiliary data.

  The bit synchronization state means that the HD-SDI signal of the first channel and the HD-SDI signal of the second channel are synchronized with the same system clock and have the same bit rate (1.. 485 Gbps or 1.485 Gbps / 1.001). The state where the frame rates do not match is, for example, a state where the frame rate of one channel is 30P and the frame rate of the other channel is 24P or 25P. The picture format (number of active samples x number of active lines) and sampling method (4: 2: 2 sampling or 4: 4: 4 sampling, etc.) do not match the state where the formats do not match. State.

  The word rewriting / signal generating unit 15 rewrites the timing reference signal SAV / EAV by the process (1) and the parallel digital video signal of the first channel and the parallel digital video signal of the second channel (only one channel). When it is detected that an HD-SDI signal is input, a parallel digital video signal generated by the process (2) above and a signal indicating the detection result of the process (3) are shown in FIG. 3 to the multiplexing circuit 16.

  The multiplexing circuit 16 multiplexes the parallel digital video signal of the first channel and the parallel digital video signal of the second channel in units of 10 bits. If it is detected as a result of the process (3) that at least one of the frame rate and the format does not match, the timing reference signal SAV / of the parallel digital video signal of the first channel is detected. This multiplexing process is performed with an arbitrary phase without aligning the phases of the EAV and the timing reference signal SAV / EAV of the parallel digital video signal of the second channel.

  Since the timing reference signal SAV / EAV in the parallel digital video signal of the first channel has been rewritten, the timing reference signal SAV / EAV multiplexed by this multiplexing processing (Multiplexed 10-bit parallel in FIG. 3 of SMPTE 424M) The first three words of SAV / EAV in the interface are 3FFh, 3FFh, 000h, 000h, 000h, 000h, where the first and second channels are the same code as shown in FIG. 4A. On the other hand, as shown in FIG. 4B, the first channel and the second channel are 3FFh, 3FEh, 000h, 001h, 000h, 001h, which are different codes.

  If the frame rate and the format do not match between the first channel and the second channel, the timing reference signal SAV / EAV multiplexed by this multiplexing processing is originally one channel as shown in FIG. 4A. While the phase is aligned between the eyes and the second channel, the phases are not aligned.

  The parallel digital data obtained by multiplexing the parallel digital video signal of the first channel and the parallel digital video signal of the second channel in this way by the multiplexing circuit 16 is scrambled by the scrambler 17 of FIG. The bit rate of 2.970 Gbps or 2.970 Gbps / 1.001 (2.970 Gbps when the bit rate of the original input HD-SDI signal is 1.485 Gbps is determined by the serial conversion circuit 18 and the original input HD-SDI When the signal bit rate is 1.485 Gbps / 1.001, it is converted to serial digital data of 2.970 Gbps / 1.001).

  This serial digital data is transmitted from the coaxial driver or electro-optical converter 2 of FIG. 2 using a coaxial cable or optical fiber 3 and received by the receiving coaxial receiver or optical-electric converter 4.

  FIG. 5 is a block diagram illustrating a configuration of the signal processing device 5 on the reception side. Serial digital data received by the coaxial receiver or the opto-electric converter 4 is converted into parallel digital data by the serial / parallel conversion circuit 21, scrambled by the descrambler 22, and then word-synchronized / word-written back. Sent to the unit 23.

The word synchronization / word write back unit 23 performs the following processes (1) and (2).
(1) Instead of detecting consecutive codes 3FFh, 3FFh, 000h, 000h, 000h, 000h as shown in FIG. 4A and establishing word synchronization, as shown in FIG. 6, code 3FEh every 10 bits. , 001h, 001h (first three words of the timing reference signal SAV / EAV of the first channel shown in FIG. 4B) to establish word synchronization, and the parallel digital video signal of the first channel and the second channel The parallel digital video signals are distinguished from each other.

  When the phases of the timing reference signals SAV / EAV for the first channel and the timing reference signals SAV / EAV for the second channel are aligned, the codes adjacent to the 10-bit 3FEh, 001h, 001h (see FIG. 6). XXXh, XXXh, XXXh) every 10 bits is the first 3 words 3FFh, 000h, 000h of the timing reference signal SAV / EAV of the second channel. On the other hand, when the phases of the timing reference signal SAV / EAV for the first channel and the timing reference signal SAV / EAV for the second channel are not aligned, the code adjacent to the 3FEh, 001h, 001h every 10 bits is It is not the first 3 words 3FFh, 000h, 000h of the timing reference signal SAV / EAV for the second channel. However, it is always possible to detect 3FEh, 001h, and 001h every 10 bits regardless of the contents of adjacent codes.

(2) The code of the timing reference signal SAV / EAV of the first channel detected by the above process (1) is written back to 3FFh, 000h, 000h (in the direct mapping method, 3FEh, 001h, 001h is converted to 3FFh, 000h, 000h) In Mapping of 2 × SMPTE-292M HD-SDI interfaces, 3FEh, 3FEh, 001h, 001h, 001h, 001h are written back to 3FFh, 3FFh, 000h, 000h, 000h, 000h) The parallel digital video signal and the second channel parallel digital video signal are sent to the parallel / serial conversion circuits 24 and 25 of FIG.

  In the parallel / serial conversion circuits 24 and 25, the parallel digital video signal of the first channel and the parallel digital video signal of the second channel are respectively transmitted at a bit rate of 1.485 Gbps or 1.485 Gbps / 1.001 (coaxial receiver or optical signal). -When the bit rate of the serial digital data received by the electrical converter 4 is 2.970 Gbps, it is 1.485 Gbps, and when the bit rate of the serial digital data is 2.970 Gbps / 1.001 Is converted to an HD-SDI signal of 1.485 Gbps / 1.001. Then, the HD-SDI signals for two channels reproduced in this way are output from the output ports 26 and 27 to the outside of the signal processing device 5 as shown in FIG.

  As described above, in this transmission system, the signal processing apparatus 1 on the transmission side uses the input HD-SDI signal of the first channel to establish word synchronization and horizontal synchronization in the timing reference signal SAV / EAV. Are rewritten with another word and multiplexed with the HD-SDI signal of the second channel. Then, the signal processing device 5 on the receiving side distinguishes the first channel from the second channel by detecting the rewritten word.

  Therefore, even when an HD-SDI signal of only one channel is input to the signal processing apparatus 1 on the transmission side, the signal processing apparatus 5 on the reception side can distinguish and reproduce the HD-SDI signal and transmit Even when the frame rates and formats of the two-channel HD-SDI signals input to the signal processing apparatus 1 on the receiving side are different, the signal processing apparatus 5 on the receiving side distinguishes the first channel from the second channel and determines the HD of each channel. -The SDI signal can be reproduced.

  Thereby, even when the HD-SDI signal of only one channel is input to the signal processing device 1 or when the frame rate and format of the two-channel HD-SDI signal input to the signal processing device 1 are different, Transmission can be performed in the same manner as when two-channel HD-SDI signals having the same format are input to the signal processing apparatus 1.

  In the above example, the transmission system compliant with SMPTE 424M and 425M also receives the case where an HD-SDI signal of only one channel is input, or when the frame rate and format of the input two-channel HD-SDI signal are different. The transmission is made possible. However, the present invention is similarly applied to a system in which a digital video signal other than an HD-SDI signal is multiplexed and transmitted for two channels. Transmission can be performed even when the frame rate and format of the digital video signal of the channel are different.

It is a figure which shows the format of a parallel digital video signal. It is a figure which shows the whole structure of the transmission system to which this invention is applied. It is a figure which shows the structure of the signal processing apparatus of the transmission side of FIG. It is a figure which shows the timing reference signal multiplexed by the signal processing apparatus of the transmission side of FIG. It is a figure which shows the structure of the signal processing apparatus of the receiving side of FIG. It is a figure which shows the code | symbol which the signal processing apparatus of the receiving side of FIG. 2 detects for word synchronization.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Signal processing apparatus, 2 Coaxial driver or electro-optical converter, 3 Coaxial cable or optical fiber, 4 Coaxial driver or optical-electrical converter, 5 Signal processing apparatus, 11,12 input port, 13,14 Serial / parallel conversion circuit 15 word rewriting / signal generation unit, 16 multiplexing circuit, 17 scrambler, 18 parallel / serial conversion circuit, 21 serial / parallel conversion circuit, 22 descrambler, 23 word synchronization / word write back unit, 24, 25 parallel / serial Conversion circuit, 26, 27 output port

Claims (7)

A signal processing device that inputs two channels of digital video signals in which at least video signal sections and predetermined word sections for word synchronization are arranged in time series, and multiplexes the input digital video signals for the two channels. In
Rewriting means for rewriting the predetermined word in the input digital video signal of the first channel to another word;
A signal processing apparatus, wherein the digital video signal of the first channel rewritten to the different word by the rewriting means and the digital video signal of the second channel are multiplexed. The signal processing device according to claim 1,
Detection means for detecting whether the digital video signal of the second channel is input;
Generation means for generating a digital video signal storing signals in the video signal section and the timing reference signal section when the detection means detects that the digital video signal of the second channel is not input. And further comprising
When the detection means detects that the digital video signal of the second channel is not input, the digital video signal of the first channel rewritten to the other word by the rewriting means, and the generation means And a digital video signal generated by the signal processing apparatus. The signal processing device according to claim 1,
Detecting means for detecting whether the digital video signal of the first channel and the digital video signal of the second channel match with each other;
When it is detected by the detection means that at least one of the frame rate and the format does not match, the digital video signal of the first channel rewritten to the other word by the rewrite means, and the 2 A signal processing apparatus, wherein the digital video signal of the channel is multiplexed without aligning the phase of the predetermined word section. The signal processing device according to claim 1,
The digital video signal is an HD-SDI signal conforming to SMPTE292M,
The rewriting means rewrites the word 3FFh, 000h, 000h in the timing reference signal of the HD-SDI signal with another prohibited code,
A signal processing apparatus that performs multiplexing and scrambling in accordance with SMPTE424M and 425M. A signal processing method for inputting two channels of digital video signals in which at least video signal sections and predetermined word sections for word synchronization are arranged in time series, and multiplexing the input digital video signals for the two channels In
A first step of rewriting the predetermined word in the input digital video signal of the first channel with another word;
Signal processing comprising: a second step of multiplexing the digital video signal of the first channel rewritten to the different word in the first step and the digital video signal of the second channel. Method. Digital data obtained by multiplexing two channels of digital video signals in which at least a video signal section and a predetermined word section for word synchronization are arranged in time series, and are included in the first channel digital video signal In a signal processing apparatus for reproducing the digital video signal of each channel from digital data in which the predetermined word is rewritten to another word,
Detecting means for detecting the another word from the digital data;
Write-back means for writing back the another word detected by the detection means to the predetermined word;
The digital video signal of each channel is reproduced by distinguishing the digital video signal of the first channel and the digital video signal of the second channel based on the another word detected by the detecting means. Signal processing device. Digital data obtained by multiplexing two channels of digital video signals in which at least a video signal section and a predetermined word section for word synchronization are arranged in time series, and are included in the first channel digital video signal In a signal processing method for reproducing the digital video signal of each channel from digital data in which the predetermined word is rewritten to another word,
A first step of detecting the another word from the digital data;
A second step of writing back the other word detected in the first step back to the predetermined word;
Based on the another word detected in the second step, the digital video signal of each channel is reproduced by distinguishing the digital video signal of the first channel from the digital video signal of the second channel. And a signal processing method.

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