JP2008027929A - Semiconductor device, manufacturing method and inspection method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow a semiconductor device having an external connection terminal to have an electrode structure with which an electric characteristic test, a burn-in test and formation of the external connection terminal can be collectively executed in a wafer state without causing a damage on each portion. <P>SOLUTION: A protruding electrode 4 formed on an electrode pad 2 of a semiconductor substrate 1 is formed into a structure having a first flat region 14a positioned on an upper surface center portion, a second flat region 14b positioned near an upper surface external periphery so as to surround it, and a first convex region 14c between both the regions 14a, 14b. With this configuration, the electric characteristic inspection is executed on the uneven protruding electrode 4, thereby preventing a damage on a portion below the electrode pad 2. Since a non-conductor coating 6 can be formed on only the first flat region 14a when a semiconductor device determined as an unacceptable product in the electric characteristic test is electrically disconnected from a common wiring, the burn-in test and the formation of the external connection terminal can be positively and stably formed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, a manufacturing method thereof, and an inspection method, and more particularly to an electrode structure for collectively manufacturing and inspecting semiconductor devices having external connection terminals in a wafer state.

  In recent years, as information communication devices and office electronic devices have been reduced in size and functionality, semiconductor integrated circuit devices (hereinafter referred to as semiconductor devices or semiconductor chips) mounted on these electronic devices have been reduced in size. Therefore, it is required to increase the number of input / output external terminals.

  It has become difficult to satisfy these requirements by a conventional method in which electrode pads are formed on the periphery of a semiconductor chip and connected to an external circuit by a wire bonding method. For this reason, a flip chip method has been adopted in which electrode pads are formed on an active region and are connected to an external circuit via external connection terminals called bumps.

  On the other hand, with the remarkable progress of the semiconductor manufacturing process, the structure of the semiconductor chip is also miniaturized and highly integrated, and copper wiring having a relatively low resistance is used as a wiring material, and the relative dielectric constant is low as an interlayer insulating film. In many cases, so-called Low-k materials are used.

  However, in a semiconductor chip that has been miniaturized and highly integrated, the active region is easily damaged by external stress, and in order to prevent this, especially when connecting to an external circuit using the flip chip method described above. Attention has been focused on fusion bonding using solder bumps rather than pressure welding using an anisotropic conductive sheet (ACF) or the like. There are roughly two methods for forming solder bumps on electrode pads such as aluminum (Al).

  One is a method using an electroplating method. Forming an insulating film on the entire surface so as to have openings on electrode pads on the surface of a plurality of semiconductor devices formed on the semiconductor wafer, and then forming a metal layer composed of a barrier metal and a seed metal on the entire surface of the wafer; A plating resist pattern is formed on the metal layer so as to have an opening on the electrode pad, and then an under bump metal (hereinafter referred to as UBM) is formed on the opening by electroplating. After solder plating is performed, the plating resist pattern is removed, unnecessary metal layers are removed by etching, and finally heat treatment is performed to form solder bumps.

  The other is a method using a printing method or a ball mounting method. An insulating film is formed on the entire surface so as to have openings on the electrode pads on the surface of the plurality of semiconductor devices formed on the semiconductor wafer, and the electroless plating method is used on the electrode pads exposed from the openings. After the UBM is formed and solder paste or solder balls are placed on the UBM by a method such as screen printing or ball mounting, solder bumps are formed by performing heat treatment.

  By the way, a plurality of semiconductor devices having external connection terminals such as solder bumps are often mounted on a circuit board, and even if one of them is abnormal, the entire device becomes defective. The apparatus is required to have high reliability, and an inspection for checking whether or not each semiconductor device is abnormal has become an important issue. Examples of such inspection include an electrical characteristic inspection and a burn-in test performed thereafter, and each of them requires high reliability and low cost. However, as a recent trend, the electrode pad is formed on the active region as described above, and a low-k material is often used as an interlayer insulating film. The possibility of receiving has increased.

  Even in a semiconductor device of the above-described type in which solder bumps are formed and fusion-bonded, damage during mounting has been reduced, but damage has increased in the course of inspection. When an electrical property inspection or a subsequent burn-in test is performed on an electrode pad as in the prior art, an interlayer insulating film may crack or adversely affect electrical properties. In order to avoid this, if the electrical characteristic inspection is performed after the solder bump is formed, the bump may be deformed by bringing the inspection probe into contact with the surface of the solder bump, which may adversely affect the mounting. Even if the electrical characteristic inspection can be performed with little or no deformation, there is the following problem in performing the burn-in test after that.

  The burn-in test has been carried out in a wafer state because it is easy to handle and advantageous in terms of cost, and for that purpose, a plurality of semiconductor devices formed on the same wafer can be powered on simultaneously. It is necessary to operate by applying a signal. However, supplying power and signals individually to each semiconductor device requires many wires to be routed from the wafer and is not practical. It is necessary to make as many electrodes as possible and reduce the number of wires that need to be drawn out independently. However, if the wiring is shared, if an abnormal current flows in one of the semiconductor devices that are commonly wired, the other semiconductor devices are also affected, and a normal burn-in test cannot be performed. That is, if even one defective product exists among the commonly wired semiconductor devices, the burn-in test of all the shared semiconductor devices cannot be performed normally. In order to prevent this, it is necessary to electrically disconnect the semiconductor device determined to be defective in the electrical characteristic inspection from the common wiring.

  In the conventional method in which a burn-in test is performed on an electrode pad made of aluminum or the like, an electrode to which a common power line or signal line used in the burn-in test is connected to a semiconductor device in which a defect is detected in a prior electrical characteristic test. By covering the pad with a non-conductive coating, the defective burn-in test electrode pad is electrically separated from the common wiring (for example, Patent Document 1). On the other hand, in the method of inspecting the electrical characteristics on the solder bumps, the subsequent burn-in test must also be performed on the solder bumps, and the solder bumps for the burn-in test of the semiconductor device determined to be defective by the electrical characteristics inspection are shared. It is necessary to cover the solder bumps with a non-conductive coating in order to be electrically separated from the solder. However, a normal nonconductive film is a liquid material applied and cured, and it is difficult to reliably form a nonconductive film on a solder bump formed in a substantially spherical shape.

  With regard to the electrical property inspection, it has been proposed to form a protruding electrode having irregularities on the electrode pad in advance so as not to cause damage below the electrode pad during probing. Contact resistance is reduced by making it uneven (for example, Patent Document 2). There is also disclosed a structure that prevents poor contact during probing by forming the upper peripheral edge of the protruding electrode in a ring shape (for example, Patent Document 3). However, these methods cannot be applied when an electrolytic plating method is used to form solder bumps. This is because a metal layer is formed on the entire surface of the wafer at the time of solder plating. The electrical property inspection is performed either on the electrode pad or after the solder bump is formed.

When solder bumps are formed using a method other than electrolytic plating, that is, when formed using a printing method or a ball mounting method, a protruding electrode is formed as follows, and electrical characteristics are inspected on the protruding electrode. It can be performed. As shown in FIGS. 9A and 9B, an electrode pad 2 is formed on the semiconductor substrate 1, an insulating film 3 is formed on the semiconductor substrate 1 and on the peripheral edge of the electrode pad 2, and an opening in the insulating film 3 is formed. On the electrode pad 2 exposed from the portion 3a and on the step portion of the insulating film 3 placed on the peripheral portion of the electrode pad 2, a protruding electrode 4 made of Ni and Au is formed as UBM by an electroless plating method or the like. Solder bumps 5 are formed on this. When an electrical property test is performed on such a protruding electrode 4, since an Au film exists on the surface of the protruding electrode 4, it is possible to ensure electrical connection even if the probe load is set low. The damage to the bottom of the electrode pad 2 can be reduced. In order to perform the burn-in test in the wafer state as it is after the electrical characteristic inspection, the protruding electrode 4 for the burn-in test of the semiconductor device determined to be defective is electrically separated from the common wiring. FIG. 10 shows a state in which a nonconductive film 6 is formed on the protruding electrode 4 for that purpose. In this way, even if a burn-in test is performed collectively in a wafer state, abnormal current does not flow to defective products.
Japanese Patent No. 3395304 JP 2001-174514 A Japanese Patent No. 3348682

  When solder bumps are formed collectively in a wafer state after the burn-in test by a printing method or a ball mounting method, the solder bumps 5 are formed on all the protruding electrodes 4 regardless of the pass / fail judgment in the electrical property inspection. Become. Solder bumps 5 are also formed on the protruding electrodes 4 of the defective semiconductor device.

  However, in this case, since the nonconductive film 6 is formed on the protruding electrode 4 of the defective semiconductor device as described above, the protruding electrode can be formed even if a solder paste is printed or a solder ball is mounted on that portion. 4 is not metal-bonded but flows out, and irregular shaped bumps may be formed on a non-defective semiconductor device. In order to prevent this, even if the non-conductive film 6 is formed only on the inner side of the step portion of the insulating film 3, that is, only on the portion where the burn-in probe contacts, there is a high probability that the liquid film material will get over the step portion, The solder bump 5 cannot be stably formed on the protruding electrode 4.

  On the other hand, it is not difficult to form the non-conductive coating 6 on the entire surface of the bump electrode 4 as hard as it is formed on the spherical solder bump 5, but it is necessary to increase the coating amount of the liquid film material. The non-conductive film is formed on the adjacent non-defective product, which may cause poor connection and poor appearance.

  The present invention has been made in order to solve the above-described problems, and in a semiconductor device having an external connection terminal, an electrical characteristic test, a burn-in test, and formation of the external connection terminal are collectively performed in a wafer state and in each part. The object is to provide an electrode structure that can be performed without damage.

  In order to solve the above problems, a semiconductor device of the present invention includes a plurality of electrode pads formed on a semiconductor substrate and a protruding electrode formed on the electrode pad, and the protruding electrode has a central portion on an upper surface. The first flat region located at the first and second flat regions surrounding the first flat region and located near the outer periphery of the upper surface, and located between the first flat region and the second flat region. And a convex region.

  The semiconductor device of the present invention further includes a plurality of electrode pads formed on a semiconductor substrate and a protruding electrode formed on the electrode pad, and the protruding electrode is a first flat located at the center of the upper surface. A second flat region located in the vicinity of the outer peripheral portion of the upper surface surrounding the region and the first flat region, and a concave region located in at least one of the first flat region and the second flat region It is characterized by that.

In the semiconductor device having the first configuration described above, a concave region may be included in at least one of the first flat region and the second flat region.
In these semiconductor devices, since the electrical characteristic inspection can be performed on the concavo-convex protruding electrode, the contact resistance during probing can be reduced and damage under the electrode pad can be avoided. In the case where the inspection is performed in a wafer state, when a non-conductive film is formed on the protruding electrode in order to electrically disconnect the semiconductor device determined to be defective by the electrical characteristic inspection from the common wiring prior to the burn-in test. In addition, a non-conductive film can be formed only in the first flat region at the center surrounded by the convex region and / or the concave region, and the burn-in test can be performed reliably. Although not all electrode pads are used in the burn-in test, there is no problem even if the above electrode structure is realized on all electrode pads, and inspection and external connection terminals can be formed and mounted.

  The convex region of the protruding electrode is formed based on a convex portion disposed on at least one of the electrode pad and the electrode pad. Protrusion on the substrate surface under the electrode pad before forming the electrode pad, or if the protrusion is arranged after forming the electrode pad on the flat substrate surface, the protrusion provided on the projection The electrode follows and the convex region is easily formed on the surface. Since the entire surface of the protruding electrode is made of the same electrode material, the electrical characteristic inspection is facilitated. This convex region functions as a weir when a nonconductive film is formed after the electrical property inspection.

  The convex portion is an annular convex portion. In this way, there will be an annular convex region based on the annular convex part, and when forming a non-conductive film, it can be easily suppressed from flowing to the outer peripheral part, and film formation is easy and reliable. Become.

  The plurality of convex portions are arranged so as to intersect at least one convex portion when an arbitrary straight line from the center portion of the upper surface of the electrode pad toward the outer peripheral portion is assumed. The plurality of convex portions are arranged in an annular shape with a space smaller than the height of the protruding electrode between each other. Even in these structures, there will be an annular or substantially annular convex region, and the formation of the non-conductive coating will be easy and reliable.

  The concave region of the protruding electrode is formed based on a concave portion provided on an upper surface of the electrode pad. If there is a recess on the upper surface of the electrode pad, the protruding electrode provided on the electrode pad will follow and a recessed area will be easily formed on the surface. When a non-conductive film is formed after the electrical property inspection, the non-conductive film is restricted from being accumulated in the concave region and flowing to the outer peripheral portion, so that a non-conductive film with a limited region can be formed.

  The recess is an annular groove formed on the upper surface of the electrode pad. An annular concave region based on the annular groove is present, and when the non-conductive film is formed, the flow to the outer peripheral portion can be suppressed, and the film formation is easy and reliable.

  The convex portion may be made of an insulating material. If it does in this way, since the said convex part can be formed simultaneously when forming an insulating layer on or under an electrode pad, the above-mentioned effect can be acquired, without increasing the number of processes.

  At least one of the electrode pads may be formed on the semiconductor element formation region. As described above, the protruding electrode on the electrode pad has irregularities and reduces the contact resistance at the time of probing, so that it is possible to perform electrical characteristic inspection and burn-in test without damaging the semiconductor element under the electrode pad. I can do it.

  An external connection terminal is formed on the electrode pad. If it does in this way, it can mount, without giving a damage under the said electrode pad. When forming such an external connection terminal, metal bonding can be secured at the outer peripheral portion of the protruding electrode, and there is no adverse effect on the surroundings by shifting from a predetermined position.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming a plurality of electrode pads on a semiconductor substrate, a step of forming a convex portion having a predetermined shape on the electrode pad, and the electrode including the convex portion. An electrode material is disposed on the pad, and a first flat region located in the center portion of the upper surface, a second flat region located in the vicinity of the outer periphery of the upper surface surrounding the first flat region, and the first flat region Forming a projecting electrode having a convex region located between the region and the second flat region, contacting the projecting electrode, inspecting electrical characteristics of the semiconductor element, and the electrical characteristics The method includes a step of performing a burn-in test by contacting the protruding electrode after the inspection, and a step of forming an external connection terminal on the protruding electrode after the burn-in test.

  Another method of manufacturing a semiconductor device according to the present invention includes a step of forming a plurality of electrode pads on a semiconductor substrate, a step of forming a recess having a predetermined shape on the electrode pad, and the electrode including the top of the recess An electrode material is disposed on the pad, and a first flat region located in the center portion of the upper surface, a second flat region located in the vicinity of the outer periphery of the upper surface surrounding the first flat region, and the first flat region Forming a protruding electrode having a region and a recessed region located in at least one of the second flat regions, performing an electrical property test on the semiconductor element in contact with the protruding electrode, The method includes a step of performing a burn-in test by contacting the protruding electrode after an electrical characteristic test, and a step of forming an external connection terminal on the protruding electrode after the burn-in test.

  Still another method of manufacturing a semiconductor device according to the present invention includes a step of forming a plurality of electrode pads on a semiconductor substrate, a step of forming convex portions and concave portions having a predetermined shape on the electrode pads, and the convex portions. An electrode material is disposed on the electrode pad including the upper portion and the concave portion, and a first flat region located in the center portion of the upper surface and a second portion located in the vicinity of the outer peripheral portion of the upper surface surrounding the first flat region. A flat region, a convex region located between the first flat region and the second flat region, and a concave region located in at least one of the first flat region and the second flat region. Forming a projecting electrode having a region; contacting the projecting electrode; performing an electrical property test on the semiconductor element; and contacting the projecting electrode after the electrical property test and performing a burn-in test. And the burn-in test Characterized in that it comprises a step of forming external connection terminals on said protruding electrode.

  According to these methods, a protruding electrode having a convex region and / or a concave region can be formed without significant changes compared to a conventional method for manufacturing a semiconductor device. It is possible to form a non-conductive film only in the first flat region in the central portion of the protruding electrode of the semiconductor device determined to be defective, and to reliably perform a burn-in test using the non-conductive film. . In the subsequent formation of the external connection terminals, metal bonding between the protruding electrodes and the external connection terminals can be ensured in the second flat region, so that there is no problem with the adjacent chip.

  In the semiconductor device manufacturing method described above, the step of forming a convex portion having a predetermined shape on the electrode pad forms an insulating film covering the main surface of the semiconductor substrate so that at least a part of the upper surface of the electrode pad is exposed. It can be performed simultaneously with the process of performing. In this way, the bump electrode can be formed without increasing the number of steps as compared with the conventional method for manufacturing a semiconductor device, and therefore the same effect can be obtained without increasing the manufacturing cost. It becomes.

  In the semiconductor device manufacturing method described above, the process up to the step of forming the external connection terminals can be performed in a wafer state, and then divided into individual pieces. In this way, not only the non-conductor film forming process in the burn-in test described above can be easily and reliably performed, but also the semiconductor device manufacturing cost can be greatly increased by performing the burn-in test and the external connection terminal forming process in the wafer state. Can be lowered.

  The method for inspecting a semiconductor device of the present invention performs a test of electrical characteristics of a plurality of semiconductor devices formed on a semiconductor wafer in contact with a protruding electrode on the uppermost layer, and determines a semiconductor device that is determined to be defective by the electrical characteristics test. By disposing an insulating resin only in the central region surrounded by at least one of the convex region and the concave region of the protruding electrode for burn-in test, it is electrically disconnected from the common wiring, and then the plurality of semiconductor devices A burn-in test is performed by bringing the probe electrode into contact with the central region of the protruding electrode and performing a batch test. In this way, it is possible to reliably form a non-conductive film with a small amount of insulating resin, and it is possible to perform a burn-in test in a batch on the wafer, improving production efficiency and reducing manufacturing costs. It becomes possible.

  According to the present invention, by disposing at least one of the convex region and the concave region in the vicinity of the outer peripheral portion of the surface of the protruding electrode formed on the electrode pad, the non-conductive film is formed only in the region inside the region. In addition, when the external connection terminals are formed by solder, it is possible to reliably perform metal bonding using a metal portion in a region outside the region.

  Therefore, for the semiconductor device formed on the semiconductor wafer, the burn-in test electrode of the semiconductor device determined to be defective can be reliably electrically disconnected from the common wiring by forming the non-conductive film. In addition, a burn-in test can be performed in a lump in the wafer state, and then external connection terminals can be formed. Therefore, a highly reliable semiconductor device having an external connection terminal can be manufactured with reduced manufacturing cost and manufacturing lead time.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1A is a plan view showing an electrode structure of the semiconductor device according to the first embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along the line AA ′ in FIG. It is.

  1A and 1B, an electrode pad 2 made of Al is formed on a semiconductor substrate 1, and an insulating film 3 made of silicon nitride is formed on the semiconductor substrate 1 and on the peripheral edge of the electrode pad 2. At the same time, an annular protrusion 11 made of the same material as that of the insulating film 3 is formed on the electrode pad 2 exposed from the opening 3 a of the insulating film 3. A protruding electrode 4 is formed over the electrode pad 2, the protrusion 11, and the step portion of the insulating film 3 placed on the peripheral edge of the electrode pad 2.

  The protruding electrode 4 has a two-layer structure of Ni and Au by an electroless plating method or the like. On the upper surface of the protruding electrode 4, a first flat region 14a (hereinafter referred to as a first flat region 14a) located at the center thereof and a second flat region that surrounds the first flat region 4a and is located in the vicinity of the outer peripheral portion. 14b (hereinafter referred to as a second flat region 14b) and the first flat region between the first flat region 14a and the second flat region 14b and on the outer peripheral side of the second flat region 14b. 14a and the 1st convex area | region 14c (henceforth the 1st convex area | region 14c) and the 2nd convex area | region 14d (henceforth outer peripheral part convex area | region 14d) which protruded rather than the 2nd flat area | region 14b are formed. .

A manufacturing method and an inspection method of the semiconductor device having the above electrode structure will be described with reference to FIGS.
As shown in FIG. 2A, a plurality of semiconductor integrated circuit devices 10 (hereinafter referred to as semiconductor chips 10) having semiconductor integrated circuit elements on a main surface are formed on a semiconductor substrate (semiconductor wafer) 1, A plurality of electrode pads 2 (2a, 2b) are formed in the region of the semiconductor chip 10. 2a is an electrode pad used in a later burn-in test, and 2b is another electrode pad.

  Next, as shown in FIG. 2B, an insulating film (passivation film) 3 made of silicon nitride is formed on the entire surface of the wafer, and an opening 3a is formed on the electrode pads 2a and 2b. A protrusion 11 is formed.

  Next, as shown in FIG. 2C, Ni and Au are laminated in this order on the electrode pads 2a and 2b by the electroless plating method to form the protruding electrodes 4 (4a and 4b). 4a is a protruding electrode formed on the electrode pad 2a and used for the burn-in test, and 4b is a protruding electrode formed on the electrode pad 2b. When the electroless plating method is used, the metal Ni and Au grow isotropically from the metal surfaces of the electrode pads 2a and 2b, so that the protruding electrodes 4a and 4b follow the shape of the surface of the electrode pads 2a and 2b, Along with the first flat region 14a and the second flat region 14b described above, a first convex region 14c and an outer peripheral convex region 14d based on the stepped portions of the annular protrusion 11 and the insulating film 3 are formed.

  Next, as shown in FIG. 2D, the probe 12 is brought into contact with the protruding electrodes 4a and 4b to perform an electrical characteristic test. Then, the semiconductor chip is classified into a semiconductor chip 10a determined to be defective and a semiconductor chip 10b determined to be non-defective.

  Next, as shown in FIG. 2E, a non-conductive coating for electrically separating the semiconductor chip 10a from the common wiring is formed on the protruding electrode 4a used in the burn-in test of the semiconductor chip 10a determined to be defective. 6 is formed. At this time, as shown in an enlarged view in FIG. 3, the nonconductive film 6 is formed only on the first flat region 14a on the protruding electrode 4a.

  Next, as shown in FIG. 2F, the burn-in test is performed by bringing the burn-in probe 13 into contact with the protruding electrodes 4a of the defective and non-defective semiconductor chips 10a and 10b. The burn-in probe 13 is designed to be in contact with the first flat region 14a.

  Next, as shown in FIG. 2G, solder bumps 5 as external connection terminals are formed by printing solder paste on the protruding electrodes 4a and 4b and then melting them. Similarly, the solder bumps 5 are also formed on the defective and non-defective semiconductor chips 10a and 10b.

Finally, as shown in FIG. 2H, the semiconductor chips 10a and 10b are divided by dicing.
According to the above method, since the above-described electrode structure is formed, the electrical characteristic inspection can be performed on the concavo-convex protruding electrode 4, the contact resistance during probing can be reduced, and the electrode pad 2 can be formed under the electrode pad 2. Damage can be avoided. Since the first convex region 14c exists between the first flat region 14a and the second flat region 14b on the upper surface of the protruding electrode 4, the nonconductive film 6 can be formed only in the first flat region 14a. Therefore, the semiconductor chip 10a determined to be defective in the electrical characteristic inspection can be electrically disconnected from the common wiring, and the burn-in test can be performed in a lump in the wafer state, and the protrusion on which the nonconductive film 6 is formed. It is possible to stably form the solder bump 5 on the electrode 4a. The first convex region 14 c of the protruding electrode 4 forms an annular protrusion 11 at the same time as forming an opening 3 a that exposes the electrode pad 2 from a protective film (passivation film) 3 that covers the semiconductor substrate 1 and the electrode pad 2. Can be formed by following the protrusions 11 only by forming, so that the number of steps is not increased.

  That is, it is possible to perform the electrical property inspection, the burn-in test, and the formation of the solder bump 5 without damaging the electrode pad 2 collectively in the wafer state, and the solder bump 5 with little damage during mounting. It is possible to manufacture a semiconductor device having the above efficiently and inexpensively.

  The material of the electrode pad 2 is not limited to the above-described Al, and for example, Cu or the like may be used. The material of the insulating film 3 is not limited to silicon nitride, but may be silicon oxide. The protruding electrode 4 functions as a UBM of an external connection terminal made of solder, which will be described later, and is not limited to the two-layer structure made of Ni and Au, but the adhesion between the solder and the electrode pad 2 and the wettability with the solder. For example, a three-layer structure of Ti, Cu, and Ni may be used. The method for forming the solder bumps 5 is not limited to the printing method, and a ball mounting method in which a solder ball is placed and melted after a flux is applied to the entire surface may be used. The annular protrusion 11 is not limited to the same material as that of the insulating film 3 and may be any material that can form protrusions, and may be an insulating material such as polyimide or a metal material such as Al or Cu.

FIG. 4A is a plan view showing an electrode structure of a semiconductor device according to the second embodiment of the present invention, and FIG. 4B is a cross-sectional view taken along the line BB ′ in FIG. 4A of the electrode structure. It is.
This electrode structure is different from that of the first embodiment in that an annular groove 15 is formed on the upper surface of the electrode pad 2 exposed from the opening 3a of the insulating film 3 (projection 11). Not) Thus, on the upper surface of the protruding electrode 4 formed over the electrode pad 2, the groove 15, and the stepped portion of the insulating film 3, the first flat region 14 a located at the center thereof and the first flat region 14 a A second flat region 14b located in the vicinity of the outer peripheral portion and an outer peripheral convex region 14d on the outer peripheral side of the second flat region 14b are formed, and a part of the second flat region 14b is imitated to the groove 15 An annular first concave region 14e is formed.

A manufacturing method and an inspection method of the semiconductor device having the above electrode structure will be described with reference to FIGS.
As in the first embodiment, as shown in FIG. 5A, a plurality of semiconductor chips 10 having semiconductor integrated circuit elements on the main surface are formed on a semiconductor substrate (semiconductor wafer) 1, and each semiconductor A plurality of electrode pads 2 (2a, 2b) are formed in the region of the chip 10.

Next, as shown in FIG. 5B, an insulating film (passivation film) 3 made of silicon nitride is formed on the entire surface of the wafer, and an opening 3a is formed on the electrode pads 2a and 2b.
Next, as shown in FIG. 5C, an annular groove 15 is formed in the electrode pad 2a by dry etching. Here, the groove 15 was formed only in the electrode pad 2a used for the burn-in test.

  Next, as shown in FIG. 5D, Ni and Au are laminated in this order on the electrode pads 2a and 2b by the electroless plating method to form the protruding electrodes 4 (4a and 4b). By using the electroless plating method, the metals Ni and Au grow isotropically from the metal surfaces of the electrode pads 2a and 2b, and the first flat region 14a, the second flat region 14b, and the outer peripheral convex region described above. A first concave region 14e based on the annular groove 15 is formed together with 14d.

  Next, as shown in FIG. 5E, the probe 12 is brought into contact with the protruding electrodes 4a and 4b to perform an electrical characteristic test. Then, the semiconductor chip is classified into a semiconductor chip 10a determined to be defective and a semiconductor chip 10b determined to be non-defective.

  Next, as shown in FIG. 5F, a non-conductive coating for electrically separating the semiconductor chip 10a from the common wiring is used for the protruding electrode 4a used in the burn-in test of the semiconductor chip 10a determined to be defective. 6 is formed. At this time, as shown in an enlarged view in FIG. 6, the non-conductive film 6 is formed only on the first flat region 14a on the protruding electrode 4a and the second flat region 14b including the first concave region 14e. The nonconductive film 8 is prevented from being formed in the partial convex region 14d.

Next, as shown in FIG. 5G, the burn-in test is performed by bringing the burn-in probe 13 into contact with the protruding electrodes 4a and 4b of the defective and non-defective semiconductor chips 10a and 10b.
Next, as shown in FIG. 5H, solder bumps 5 as external connection terminals are formed by printing a solder paste on the protruding electrodes 4a and 4b and then melting them. Similarly, the solder bumps 5 are also formed on the defective and non-defective semiconductor chips 10a and 10b.

Finally, as shown in FIG. 5 (i), the semiconductor chips 10a and 10b are divided by dicing.
According to the above method, as in the first embodiment, since the above-described electrode structure is formed, an electrical property inspection can be performed on the concavo-convex protruding electrode 4, and the contact resistance during probing is reduced. In addition, damage under the electrode pad 2 can be avoided. Since the upper surface of the protruding electrode 4a includes the first concave region 14e that is recessed from the first flat region 14a and the second flat region 14b, the non-conductive film 6 is formed only in these regions 14a, 14b, and 14e. Therefore, the semiconductor chip 10a determined to be defective in the electrical characteristic inspection can be electrically separated from the common wiring, and the burn-in test can be performed in a lump in the wafer state, and the non-conductive film 6 is formed. It is possible to form the solder bump 5 on the protruding electrode 4a. Since the first concave region 14e of the protruding electrode 4a is formed by the annular groove 15 formed by etching the electrode pad 2a, the adhesion of the protruding electrode 4a electrode pad 2a can be further strengthened.

  That is, it is possible to perform the electrical property inspection, the burn-in test, and the formation of the solder bump 5 without damaging the electrode pad 2 collectively in the wafer state, and the solder bump 5 with little damage during mounting. It is possible to manufacture a semiconductor device having the above efficiently and inexpensively.

FIG. 7A is a plan view showing an electrode structure of a semiconductor device according to the third embodiment of the present invention, and FIG. 7B is a cross-sectional view taken along the line CC ′ in FIG. 7A of the electrode structure. It is.
This electrode structure is different from that of the first embodiment in that a plurality of protrusions 16 made of the same material as the insulating film 3 are not formed on the electrode pad 2 exposed from the opening 3a of the insulating film 3. Further, the upper electrode pad 17 made of Al is formed on the electrode pad 2, the protrusion 16, and a part of the insulating film 3, and the protrusion electrode 4 is formed on the upper electrode pad 17. Is a point. The plurality of protrusions 16 are arranged so as to pass through the protrusions 16 when an arbitrary straight line is assumed from the center of the surface of the electrode pad 2 toward the outer periphery. That is, the plurality of protrusions 16 are arranged at 360 ° around the center of the upper surface of the electrode pad 2 while being positioned on the outer periphery of the inner periphery.

  As a result, the upper electrode pad 17 formed over the electrode pad 2, the protrusion 16, and a part of the insulating film 3, and the protrusion electrode 4 formed thereon are formed on the protrusion 16 and the insulating film 3. The part placed on is convex. That is, on the upper surface of the protruding electrode 4, a first flat region 14a located at the center thereof, a second flat region 14b surrounding the first flat region 14a and located near the outer peripheral portion, and a second flat region 14b An outer peripheral convex region 14d on the outer peripheral side is formed, and a substantially annular first convex region that follows the plurality of discontinuous protrusions 16 between the first flat region 14a and the second flat region 14b. 14c is formed.

FIG. 8A is a plan view showing an electrode structure of a semiconductor device according to the fourth embodiment of the present invention, and FIG. 8B is a sectional view taken along the line DD ′ in FIG. 8A of the electrode structure. It is.
This electrode structure is different from that of the first embodiment in that an electrode pad 2 made of Al is formed on the semiconductor substrate 1 with a depression 18 in the center, and the semiconductor substrate 1 and electrode An insulating film 3 made of silicon nitride and an insulating film 19 made of polyimide are formed on the peripheral edge of the pad 2, and the electrode pad 2 exposed from the opening 19 a of the insulating film 19 covering the inner peripheral edge of the insulating film 3. A plurality of protrusions 20 made of the same material as that of the insulating film 19 are disposed on the electrode pad 2 including the depression 18b, the protrusion 20 and the peripheral portion of the electrode pad 2 in a discontinuous and substantially annular shape. The protruding electrode 4 is formed over the step portion of the insulating film 19 placed on the substrate. The protrusions 20 are arranged on the electrode pad 2 on the outer peripheral side of the recess 18 with an interval of about 4 μm therebetween, and the protrusion electrode 4 is formed with a thickness of about 5 μm.

  Thus, on the upper surface of the protruding electrode 4, the first flat region 14 a located in the center thereof, the second flat region 14 b surrounding the first flat region 14 a and located in the vicinity of the outer peripheral portion, and the second flat region The outer peripheral convex region 14d on the outer peripheral side of 14b is formed, and the first flat region 14a and the second flat region 14b are more convex than the first flat region 14a and the second flat region 14b. A convex region 14c is formed, and a third flat region 16f that is recessed from the first flat region 14a is formed at the center of the first flat region 14a itself. The first convex region 14 c is substantially annular because the interval between the protrusions 20 is set smaller than the thickness of the protruding electrode 4.

  Even with the electrode structure of the semiconductor device according to the third or fourth embodiment described above, it is possible to perform an electrical property inspection without damaging the electrode pad 2, and a protrusion or Due to the unevenness, the non-conductive film 6 can be easily prevented from flowing on the semiconductor chip 10a determined to be defective in the electrical property inspection during the burn-in test, and the burn-in test electrode can be formed from the common wiring. It can be electrically disconnected. Since the metal surface is exposed at the outer peripheral portion of the protruding electrode 4, the solder bumps 5 are formed all together in the wafer state regardless of the presence or absence of a defective chip on which the nonconductive film 6 is formed. Thus, the solder bump 5 can be formed.

  The present invention is not limited to the above-described embodiment, and can be appropriately changed within the scope of the present invention.

  According to the present invention, when manufacturing a semiconductor device having an external connection terminal, an electrical characteristic inspection and a batch burn-in test in a wafer state can be performed without damaging the electrode pads. Since the connection terminals can be formed in a lump in the wafer state, a miniaturized and highly integrated semiconductor device can be manufactured at low cost and with high reliability.

The elements on larger scale which show the electrode structure of the semiconductor device concerning the 1st Embodiment of this invention Sectional drawing which shows the manufacturing method and inspection method of a semiconductor device with the electrode of the electrode structure of FIG. Sectional drawing which shows the state which formed the nonconductive film in the middle of the process of FIG. The elements on larger scale which show the electrode structure of the semiconductor device concerning the 2nd Embodiment of this invention Sectional drawing which shows the manufacturing method and inspection method of a semiconductor device with the electrode of the electrode structure of FIG. Sectional drawing which shows the state which formed the nonconductive film in the middle of the process of FIG. The partially expanded view which shows the electrode structure of the semiconductor device concerning the 3rd Embodiment of this invention The partially expanded view which shows the electrode structure of the semiconductor device concerning the 3rd Embodiment of this invention Partial enlarged view showing the electrode structure of a conventional semiconductor device Sectional drawing which shows the state which formed the nonconductor film in the middle of the manufacturing process of the semiconductor device with the electrode of the electrode structure of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Electrode pad 3 Insulating film 4 Protruding electrode 5 Solder bump 6 Nonconductive film
10 Semiconductor chip
11 Annular projection
12 Probe
13 Burn-in probe
14a First flat region
14b Second flat region
14c First convex region
14d Perimeter convex area
14e First concave area
14f Second concave area
15 Annular groove
16 Protrusion
18 depression
19 Insulating film
20 Protrusion

Claims (18)

  A plurality of electrode pads formed on a semiconductor substrate, and a protruding electrode formed on the electrode pad, wherein the protruding electrode includes a first flat region and a first flat region located in a central portion of the upper surface And a convex region located between the first flat region and the second flat region.   A plurality of electrode pads formed on a semiconductor substrate, and a protruding electrode formed on the electrode pad, wherein the protruding electrode includes a first flat region and a first flat region located in a central portion of the upper surface And a concave region located in at least one of the first flat region and the second flat region.   The semiconductor device according to claim 1, wherein a concave region is included in at least one of the first flat region and the second flat region.   4. The semiconductor device according to claim 1, wherein the protruding region of the protruding electrode is formed based on a protruding portion disposed on at least one of the electrode pad and the electrode pad. 5.   The semiconductor device according to claim 4, wherein the convex portion is an annular convex portion.   5. The plurality of convex portions are arranged so as to intersect at least one convex portion when an arbitrary straight line from the center portion of the upper surface of the electrode pad toward the outer peripheral portion is assumed. A semiconductor device according to 1.   5. The semiconductor device according to claim 4, wherein the plurality of convex portions are arranged in an annular shape with a space smaller than the height of the protruding electrode between each other.   The semiconductor device according to claim 2, wherein the concave region of the protruding electrode is formed based on a concave portion provided on an upper surface of the electrode pad.   The semiconductor device according to claim 8, wherein the recess is an annular groove formed on an upper surface of the electrode pad.   The semiconductor device according to claim 4, wherein the convex portion is made of an insulating material.   The semiconductor device according to claim 1, wherein at least one of the electrode pads is formed on a semiconductor element formation region.   The semiconductor device according to claim 1, wherein an external connection terminal is formed on the electrode pad. Forming a plurality of electrode pads on a semiconductor substrate;
Forming a convex portion of a predetermined shape on the electrode pad;
An electrode material is disposed on the electrode pad including the convex portion, and a first flat region located in the upper surface center portion and a second flat surface surrounding the first flat region and located in the vicinity of the outer peripheral surface of the upper surface. Forming a protruding electrode having a flat region, and a convex region located between the first flat region and the second flat region;
Performing electrical property inspection of the semiconductor element in contact with the protruding electrode;
Performing a burn-in test in contact with the protruding electrode after the electrical property inspection;
And a step of forming external connection terminals on the protruding electrodes after the burn-in test. Forming a plurality of electrode pads on a semiconductor substrate;
Forming a recess having a predetermined shape on the electrode pad;
An electrode material is disposed on the electrode pad including on the recess,
A first flat region located in the center of the upper surface, a second flat region surrounding the first flat region and located near the outer periphery of the upper surface, the first flat region, and the second flat region. Forming a protruding electrode having a recessed region located in at least one region;
Performing electrical property inspection of the semiconductor element in contact with the protruding electrode;
Performing a burn-in test in contact with the protruding electrode after the electrical property inspection;
And a step of forming external connection terminals on the protruding electrodes after the burn-in test. Forming a plurality of electrode pads on a semiconductor substrate;
Forming convex and concave portions of a predetermined shape on the electrode pad;
An electrode material is disposed on the electrode pad including the convex portion and the concave portion, and is positioned in the vicinity of the upper surface outer peripheral portion surrounding the first flat region and the first flat region located in the center portion of the upper surface. A second flat region, a convex region located between the first flat region and the second flat region, and at least one of the first flat region and the second flat region. Forming a protruding electrode having a recessed region located;
Performing electrical property inspection of the semiconductor element in contact with the protruding electrode;
Performing a burn-in test in contact with the protruding electrode after the electrical property inspection;
And a step of forming external connection terminals on the protruding electrodes after the burn-in test.   The step of forming a convex portion having a predetermined shape on the electrode pad is performed simultaneously with the step of forming an insulating film covering the main surface of the semiconductor substrate so that at least a part of the upper surface of the electrode pad is exposed. The method for manufacturing a semiconductor device according to claim 13, wherein the semiconductor device is manufactured.   17. The method of manufacturing a semiconductor device according to claim 13, wherein the process up to the step of forming the external connection terminal is performed in a wafer state, and is thereafter divided into individual pieces. A method for inspecting a semiconductor device according to any one of claims 1 to 12,
Conducting electrical property inspection of a plurality of semiconductor devices formed on a semiconductor wafer in contact with the protruding electrode on the uppermost layer, a semiconductor device determined to be defective by the electrical property inspection is a convex region of the protruding electrode for burn-in test By disposing insulating resin only in the central region surrounded by at least one of the concave regions, it is electrically disconnected from the common wiring, and then the probe electrode is brought into contact with the central region of the protruding electrodes of the plurality of semiconductor devices. And performing a burn-in test in a lump.

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