JP2008026360A - Method for driving display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving method capable of surely performing the expansion of discharge to a display cell in selection erasure address discharge within a selection cell in the caseof driving a display panel in which each pixel cell made into a selection structure of a display cell and a selection cell. <P>SOLUTION: In an address period of a subfield when a selection erasure address stroke is performed, a scanning pulse of positive polarity superposed on a first scanning base potential of negative polarity is superposed on one row electrode of a row electrode pair, and an image data pulse meeting the other of the row electrode pair is applied to a column electrode. In addition, a second scanning base potential of positive polarity is applied to the other row electrode of the row electrode pair to generate the selection erasure address discharge between the column electrode and the one row electrode within the selection cell. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for driving a display panel such as a plasma display panel.

  In recent years, a plasma display device equipped with a surface discharge type AC plasma display panel as a large and thin color display panel has attracted attention. Further, as such a surface discharge type AC plasma display panel, a display panel is known in which a pixel cell carrying each pixel is composed of a selected cell and a display cell (see, for example, Patent Document 1). Such a display panel includes a front substrate and a rear substrate that are arranged to face each other with a discharge space interposed therebetween, a plurality of row electrode pairs provided on the inner surface of the front substrate, and a row electrode pair on the inner surface of the rear substrate. And a plurality of arranged column electrodes. A pixel cell PC including a display cell C1 and a selection cell C2 is formed at each intersection of the row electrode pair and the column electrode. In the case of driving such a display panel, in each of the plurality of subfields SF in each field display period, a reset process R for performing a reset discharge for setting the wall charge state of each pixel cell to an initial state, and each pixel cell The address process W for determining the state as one of the lighted cell state and the lighted cell state and the sustain process I for repeatedly discharging only the discharge cells in the lighted cell state are executed, and the first first time in one field display period. The reset process R is executed prior to the address process W only in the subfield SF1.

  In the reset process R of the first subfield SF1, the column electrode D is relatively negative and a positive reset pulse is applied to the row electrodes Y and X forming a pair of row electrodes, thereby the column electrode D in the selected cell C2. And the first row electrode Y generate a reset discharge. In the address process W of the subfield SF1, a potential of 0 volt is applied to the column electrode D to which the pixel cell PC belongs for the pixel cell PC to be set in the lighted cell state, and a positive scan pulse SP is generated. Applied to the row electrode Y. Thus, an address discharge for selective writing occurs between the column electrode D and the row electrode Y in the selected cell C2.

In the pixel cell PC (lighted cell) to be lit, when the first sustain pulse IP _Y and the address pulse AP are applied in synchronization with the first sustain pulse IP _Y, between the column electrode D and the row electrode Y in the selected cell C2. Discharge occurs. By simultaneous writing discharge by the sustain pulse and the address pulse AP, a negative wall charge is formed on the column electrode D in the selected cell C2, and a positive wall charge is formed on the row electrode Y. . The polarity of the wall charges on the row electrode Y is reversed. Further, the write discharge is expanded to the display cell C1 through the gap r, so that positive wall charges are formed on the row electrode Y in the display cell C1, and also on the second row electrode X. Negative wall charges are formed.

  In each of the subfields subsequent to the second subfield SF2, the wall charge state is set to a state in which selective discharge is unlikely to occur immediately before the selective erasure address process is executed. In the selective erasure address process, one row of the row electrode pair is set. By applying a positive scanning pulse superimposed on a positive base potential to the electrode Y and applying a positive base potential to the other row electrode X, an address discharge for selective erasure due to a high voltage occurs in the selected cell C2. I am doing so.

In the sustain process I, the positive address pulse AP is applied to all the column electrodes D, and the negative sustain pulses IP _Y and IP _X are alternately applied to all the row electrodes Y and X simultaneously. Each time the sustain pulse IP _Y or IP _X is applied, a sustain discharge is generated between the row electrodes X and Y in the display cell C1.
JP-A-2005-107428

  However, in the driving method disclosed in Patent Document 1, it is desired that address discharge for selective erasure easily occurs in each of the subfields after the second subfield SF2 and that the address margin can be improved.

  Therefore, the problem to be solved by the present invention includes the above-mentioned drawbacks as an example. In the case where each pixel cell drives a display panel having a separation structure of a display cell and a selection cell, It is an object of the present invention to provide a driving method capable of reliably extending discharge to a display cell in selective erasure address discharge.

  The driving method according to claim 1 is a front substrate and a rear substrate facing each other across a discharge space, a plurality of row electrode pairs constituting a display line on the inner surface of the front substrate, and a dielectric layer covering the row electrode pairs, A plurality of column electrodes arranged on the inner surface of the back substrate so as to intersect the row electrode pairs, and at each intersection of the row electrode pairs and the column electrodes, a display cell, a light shielding layer, and a secondary layer A plurality of display panels each including an address period and a sustain period are formed according to pixel data for each pixel based on an input video signal. A display panel driving method for driving each unit display period composed of sub-fields of a plurality of sub-fields, wherein the selective write address process is executed in the address period of the first sub-field in the unit display period, and the first sub-field is The selective erasure address process is executed in each address period of the subfield group that follows, and the column electrode side has a relatively negative polarity in the address period of the subfield in which the selective erasure address process is performed. A positive scan pulse superimposed on a negative first scan base potential is applied to one row electrode, a pixel data pulse corresponding to the pixel data is applied to the column electrode, and the other of the row electrode pairs is applied. A second scanning base potential having a positive polarity is applied to the row electrode to cause a selective erasure address discharge between the column electrode and the one row electrode in the selected cell.

  In the present invention, a positive scan pulse superimposed on a negative first scan base potential is applied to one row electrode in the address period of a subfield in which a selective erase address process is performed, and pixel data is applied to a column electrode. A corresponding pixel data pulse is applied, and a positive second scanning base potential is applied to the other row electrode. Therefore, an electric field is generated by the application of the second scanning base potential, the selective discharge in the selected cell is sufficiently expanded in the display cell, and a significant improvement in the selective erase margin is expected. As a result, the erasure of the wall charges in the display cell C1 is surely executed, so that the lit state of the pixel cell that should be in the erased state is prevented.

  FIG. 1 is a diagram showing a configuration of a plasma display device to which a driving method of the present invention is applied. This plasma display device includes a PDP 50 as a plasma display panel and a drive control circuit 54 that drives and controls the PDP 50 according to an input video signal.

  The PDP 50 includes a column electrode driver 55, a first row electrode driver 510, a second row electrode driver 520, and a display electrode formation unit DPE.

In the display electrode forming portion DPE, strip-like column electrodes (address electrodes) D _{1 to} D _m extending in the column direction (vertical direction) of the display screen are formed. Further, in the display electrode forming portion DPE, strip-like row electrodes X _{1 to} X _n and row electrodes Y _{1 to} Y _n respectively extending in the row direction (left and right direction) of the display screen are respectively shown in FIG. , XY are arranged alternately and in numerical order. Each pair of adjacent row electrodes, that is, each of the row electrode pair (X ₁ , Y ₁ ) to the row electrode pair (X _n , Y _n ) is a first display line to an nth display in the PDP 50. It corresponds to the line. A pixel cell PC serving as a pixel is formed in each intersection of each display line and the column electrodes D _{1 to} D _m , that is, in a unit light emitting region surrounded by a one-dot chain line in FIG.

  2 to 4 are diagrams showing a part of the structure of the display electrode forming portion DPE.

  FIG. 2 is a plan view of the PDP 50 viewed from the display surface side. 3 is a cross-sectional view seen from the line VV shown in FIG. 2, and FIG. 4 is a cross-sectional view seen from the line WW shown in FIG.

  As shown in FIG. 2, the row electrode Y includes a bus electrode Yb (a main body portion of the row electrode Y) extending in the row direction (left-right direction) of the display screen, and a plurality of transparent electrodes Ya connected to the bus electrode Yb. Consists of The transparent electrode Ya is made of a transparent conductive film such as ITO, and is disposed at a position corresponding to each column electrode D on the bus electrode Yb. The transparent electrode Ya extends in a direction orthogonal to the bus electrode Yb, and has one end and the other end that are wide as shown in FIG. That is, the transparent electrode Ya can be regarded as a protruding electrode protruding from the main body of the row electrode Y. The row electrode X includes a bus electrode Xb (a main body portion of the row electrode X) extending in the row direction (left-right direction) of the display screen and a plurality of transparent electrodes Xa connected to the bus electrode Xb. The bus electrode Xb is made of, for example, a black metal film. The transparent electrode Xa is made of a transparent conductive film such as ITO, and is disposed at a position corresponding to each column electrode D on the bus electrode Xb. The transparent electrode Xa extends in a direction perpendicular to the bus electrode Xb, and one end thereof has a wide shape as shown in FIG. That is, the transparent electrode Xa can be regarded as a protruding electrode protruding from the main body of the row electrode X. As shown in FIG. 2, the wide portions of the transparent electrodes Xa and Ya are arranged opposite to each other with a discharge gap g having a predetermined length. That is, the transparent electrodes Xa and Ya as protruding electrodes protruding from the main body portions of the paired row electrodes X and Y are arranged to face each other via the discharge gap g. The bus electrodes Yb and Xb are each composed of a black light-shielding conductive layer BE and a main conductive layer ME as shown in FIG.

  The row electrode Y composed of the transparent electrode Ya and the bus electrode Yb and the row electrode X composed of the transparent electrode Xa and the bus electrode Xb are arranged on the inner surface of the front transparent substrate 10 that serves as the display surface of the PDP 50 as shown in FIG. Is formed. Further, a dielectric layer 11 is formed on the back surface of the front transparent substrate 10 so as to cover the row electrodes X and Y. A black or dark light shielding layer SHD is formed on the front transparent substrate side facing each of the selected cells C2 (described later). Dielectric layer raised portions 12 projecting from the dielectric layer 11 toward the back side are formed at positions corresponding to the selected cells C2 (described later) on the surface of the dielectric layer 11. The dielectric layer raised portion 12 is formed in a region indicated by a two-dot chain line in FIG. 2 when viewed from the display surface side of the PDP 50. The surface of the dielectric layer raised portion 12 and the surface of the dielectric layer 11 where the dielectric layer raised portion 12 is not formed are covered with a protective layer MG made of MgO (magnesium oxide). A plurality of column electrodes D extending in a direction perpendicular to the bus electrodes Xb and Yb are arranged in parallel with a predetermined gap on the back substrate 13 arranged in parallel to the front transparent substrate 10. ing. A white column electrode protective layer (dielectric layer) 14 that covers the column electrode D is formed on the back substrate 13. On the column electrode protective layer 14, a partition wall 15 including a first horizontal wall 15A, a second horizontal wall 15B, and a vertical wall 15C is formed. The first horizontal wall 15A is formed to extend in the row direction (left-right direction) of the display surface at a position on the column electrode protective layer 14 facing the bus electrode Yb. The second horizontal wall 15B is formed to extend in the row direction (left-right direction) of the display surface at a position on the column electrode protective layer 14 facing the bus electrode Xb. The vertical wall 15C is formed to extend in a direction orthogonal to the bus electrode Xb (Yb) at each position between the transparent electrodes Xa (Ya) arranged at equal intervals on the bus electrode Xb (Yb). ing.

  The heights of the first horizontal wall 15A, the second horizontal wall 15B, and the vertical wall 15C are not so high as to reach the surface of the dielectric layer 11, as shown in FIGS. Therefore, as shown in FIG. 3, there is a gap r between the second lateral wall 15B and the dielectric layer raised portion 12 in which the discharge gas can flow. However, the dielectric layer raised portion 12 is provided on the surface of the dielectric layer 11 at a portion facing the first horizontal wall 15A as shown in FIG. The flow of the discharge gas is blocked by the first lateral wall 15A and the dielectric layer raised portion 12.

  A region surrounded by the first horizontal wall 15A and the vertical wall 15C (a region surrounded by an alternate long and short dash line in FIG. 2) is a pixel cell PC serving as a pixel. As shown in FIGS. 2 and 3, the pixel cell PC is divided into a display cell C1 and a selection cell C2 by the second horizontal wall 15B.

A secondary electron emission material layer 30 is formed in a region (including the side surfaces of the vertical wall 15C, the first horizontal wall 15A, and the second horizontal wall 15B) corresponding to the selected cell C2 on the column electrode protective layer 14. The secondary electron emission material layer 30 is a layer made of a high γ material having a low work function (for example, 4.2 eV or less) and a high so-called secondary electron emission coefficient. Examples of the material used as the secondary electron emission material layer 30 include alkaline earth metal oxides such as MgO, CaO, SrO, and BaO, alkali metal oxides such as Cs ₂ O, fluorides such as CaF ₂ and MgF _{2, and the} like. There are TiO ₂ , Y ₂ O ₃ , or materials whose secondary electron emission coefficient is increased by crystal defects or impurity doping, diamond-like thin films, carbon nanotubes, and the like.

  On the other hand, in the region corresponding to the display cell C1 on the column electrode protective layer 14 (including the side surfaces of the vertical wall 15C, the first horizontal wall 15A, and the second horizontal wall 15B), the phosphor layer 16 is formed as shown in FIG. Has been. There are three types of phosphor layers 16: a red phosphor layer that emits red light, a green phosphor layer that emits green light, and a blue phosphor layer that emits blue light, and the assignment is determined for each pixel cell PC.

  A discharge space filled with a discharge gas exists between the secondary electron emission material layer 30 and the phosphor layer 16 and the dielectric layer 11.

  Thus, the display cell C1 includes the pair of row electrodes X and Y that bear the display line, and the phosphor layer 16. On the other hand, the selected cell C2 includes a row electrode Y of the pair of row electrodes that bears the display line, a row electrode X of the pair of row electrodes that bears a display line adjacent to the display surface above the display line, A secondary electron emission material layer 30. In the display cell C1, as shown in FIG. 2, a wide portion formed at one end of the transparent electrode Xa of the row electrode X, and a wide portion formed at one end of the transparent electrode Ya of the row electrode Y Are arranged opposite to each other via the discharge gap g. On the other hand, in the selected cell C2, the wide portion formed at the other end of the transparent electrode Ya is included, but the transparent electrode X is not included. Further, as shown in FIG. 3, the discharge spaces of the pixel cells PC adjacent to each other in the vertical direction of the display surface (the horizontal direction in FIG. 3) are formed by the first horizontal wall 15A, the dielectric layer raised portion 12, and the protective layer MG. Blocked. On the other hand, the discharge spaces of the display cell C1 and the selected cell C2 belonging to the same pixel cell PC communicate with each other through a gap r as shown in FIG. In addition, the discharge spaces of the selected cells C2 that are adjacent to each other in the left-right direction of the display surface are blocked by the dielectric layer raised portion 12 and the first horizontal wall 15A, but the display cells C1 that are adjacent to each other in the left-right direction of the display surface. Each discharge space communicates with each other. Thus, each of the pixel cells PC is composed of the display cell C1 and the selection cell C2 whose discharge spaces communicate with each other.

  In order to suppress the interference of discharge between display cells C1 adjacent to each other in the left-right direction of the display surface, a dielectric layer raised portion is provided so as to face the vertical wall partitioning the display cell C1, and The discharge spaces of the display cells C1 that are adjacent to each other in the direction may be substantially blocked.

First, the drive control circuit 54 converts the input video signal into, for example, 8-bit pixel data representing the luminance level for each pixel, and performs error diffusion processing and dither processing on the pixel data. For example, in the error diffusion process, first, the upper 6 bits of pixel data are used as display data, and the remaining lower 2 bits are used as error data. Then, the weighted addition of each error data of the pixel data corresponding to each peripheral pixel is reflected in the display data. With this operation, the luminance for the lower 2 bits in the original pixel is expressed in a pseudo manner by the peripheral pixels, and therefore, the display data for 6 bits smaller than 8 bits is equivalent to the pixel data for 8 bits. Brightness gradation expression is possible. Then, dither processing is performed on the 6-bit error diffusion processing pixel data obtained by the error diffusion processing. In the dither processing, a plurality of adjacent pixels are set as one pixel unit, and dither coefficients each having a different coefficient value are allocated and added to the error diffusion processing pixel data corresponding to each pixel in the one pixel unit. To obtain dither-added pixel data. According to the addition of the dither coefficients, when viewed in units of one pixel, it is possible to express a luminance corresponding to 8 bits even with only the upper 4 bits of the dither addition pixel data. Therefore, the drive control circuit 54, the upper 4 bits of the dither added pixel data as multi-gradation pixel data PD _S, 15 bits formed which from the first to 15th bits in accordance with data conversion table as shown in FIG. 5 To pixel drive data GD. Accordingly, pixel data that can represent 256 gradations in 8 bits is converted into 15-bit pixel drive data GD consisting of 16 patterns in total, as shown in FIG. Next, the drive control circuit 54, the pixel drive data GD ₁ of one screen, 1～GD _n, for each _m, separates these pixel driving data GD1, ₁ to GD _{n, m} each at the same bit digit with each other By
DB1: pixel drive data GD1, ₁ to GD _n, the first bit of the _m each
DB2: the pixel drive data GD1, ₁ ~GD _n, the second bit of the _m each
DB3: pixel drive data GD1, ₁ ~GD _n, third bit of _m each
DB4: pixel drive data GD1, ₁ ~GD _n, fourth bit of the _m each
DB 5: pixel drive data GD1, ₁ ~GD _n, the fifth bit of the _m each
DB 6: pixel driving data GD1, ₁ ~GD _n, sixth bit of the _m each
DB7: pixel drive data GD1, ₁ ~GD _n, seventh bit of _m each
DB8: pixel drive data GD1, ₁ ~GD _n, eighth bit of the _m each
DB9: pixel drive data GD1, ₁ ~GD _n, 9th bit of _m each
DB 10: pixel drive data GD1, ₁ ~GD _n, 10th bit of _m each
DB 11: pixel drive data GD1, ₁ ~GD _n, 11th bit of _m each
DB 12: pixel drive data GD1, ₁ ~GD _n, 12th bit of _m each
DB 13: pixel drive data GD1, ₁ ~GD _n, the 13th bit of _m each
DB 14: pixel drive data GD1, ₁ ~GD _n, 14th bit of _m each
DB 15: obtaining pixel drive data GD1, ₁ ~GD _n, the 15th bit such pixel drive data bit groups of _m each DB1～DB15.

  Note that each of the pixel drive data bit groups DB1 to DB15 corresponds to each of subfields SF1 to SF15 described later. The drive control circuit 54 supplies the pixel drive data bit group DB corresponding to each subfield to the column electrode driver 55 by one display line (m) for each subfield SF1 to SF15.

  Further, the drive control circuit 54 supplies various drive control signals for driving and controlling the PDP 50 according to the light emission drive sequence as shown in FIG. 6 to the column electrode driver 55, the first row electrode driver 510, and the second row electrode driver 520, respectively. To do.

  Here, the light emission driving sequence shown in FIG. 6 causes the following driving to be performed for each of the 15 subfields SF1 to SF15 within each unit display period (one field or one frame display period) in the video signal. is there.

In FIG. 6, in the first subfield SF1, the simultaneous reset process R, the selective write address process _WW, and the sustain process I are executed in order. In the subfield SF2, the reset process R _O , the sustain process I _P1 , the selective erase address process W _OR , the reset process R _E , the sustain process I _P2 , and the selective erase address process W _ER are executed in order. In each of the subfields SF3 to SF15, the reset process R _O , the sustain process I _P1 , the selective erase address process W _OR , the sustain process I, the reset process R _E , the sustain process I _P2 , and the selective erase address process W _ER are sequentially executed. To do.

  7 shows various drive pulses applied to the column electrode D, the row electrodes X and Y by the column electrode driver 55, the first row electrode driver 510, and the second row electrode driver 520, respectively, according to the light emission drive sequence shown in FIG. FIG. FIG. 7 shows only the operations in the first subfield SF1 and the subsequent subfields SF2 and SF3 in the subfields SF1 to SF15 shown in FIG.

First, in the simultaneous reset process R of the subfield SF1, the first row electrode driver 510 generates a positive reset pulse RP having a pulse waveform with a slow potential transition in the rising section as compared with a sustain pulse described later. This even-numbered row electrodes _{X 2, X 4, ····,} X n-2 and X _n, and the odd-numbered row electrodes _{Y 1, Y 3, Y 5} , ····, Y n- Applied to ₃ and Y _n-1 respectively. Further, in the simultaneous reset process R of the subfield SF1, the second row electrode driver 520 generates a similar reset pulse RP, which is output as odd-numbered row electrodes X ₁ , X ₃ , X ₅ ,. X _n-3 and X _n-1 , and even-numbered row electrodes Y ₂ , Y ₄ ,..., Y _n-2 and Y _n, respectively.

  In this way, in the simultaneous reset process R, the positive reset pulse RP having a waveform with a slow potential transition at the time of rising as shown in FIG. 7 is simultaneously applied to all the row electrodes X and Y of the PDP 50. In response to the application of the reset pulse RP, a weak reset discharge is generated in the row electrode Y and the column electrode D in the selected cell C2 of all the pixel cells PC. After the end of the reset discharge, a positive charge is formed on the column electrode D in the selected cell C2, and a negative charge is formed on the row electrode Y. Further, negative wall charges are formed on the row electrodes Y in the display cells C1, and negative wall charges are also formed on the row electrodes X. That is, by executing the simultaneous reset process R, all the pixel cells PC are initialized to the extinguishing mode in which charges having the same polarity are formed on the row electrodes X and Y in the display cell C1.

Next, in the selective write address process W _W of the subfield SF1, the first row electrode driver 510, as shown in FIG. 7, and its falling transition has a peak potential V1 of positive polarity having a gentle waveform A scan base pulse BP ⁺ (first scan base potential) is generated, which is generated by even-numbered row electrodes X ₂ , X ₄ ,..., X _n-2 and X _n , and odd-numbered row electrodes Y _1. , Y ₃ , Y ₅ ,..., Y _n-3 and Y _n-1 . Further, during this time, the first row electrode driver 510 generates a scan pulse SP (scanning potential) as shown in FIG. 7 in which a predetermined positive potential is superimposed on the peak potential V1 of the scanning base pulse BP ⁺ , and the odd-numbered , Y _n-3 and Y _n-1 are sequentially applied to the row electrodes Y ₁ , Y ₃ , Y ₅ ,.

Further, in the selective write address process W _W of the sub-field SF1, a second row electrode driver 520, scan and having a its falling transition is gradual waveform has a positive peak potential V1 as shown in FIG. 7 base pulse BP ⁺ occurs, the odd-numbered row electrodes X ₁ to _{this, X 3, X 5, ····} , X n-3 and X _n-1, and even-numbered row electrodes Y _2, Y _4, ..., applied to Y _n-2 and Y _n respectively. Further, during this period, the second row electrode driver 520 generates the scan pulse SP as shown in FIG. 7 in which the positive potential is superimposed on the peak potential V1 of the scan base pulse BP ⁺ , and the even-numbered row electrode Y ₂ , Y ₄ ,..., Y _n-2 and Y _n are sequentially applied alternatively.

During this time, the column electrode driver 55 converts each data bit in the pixel drive data bit group DB1 corresponding to the subfield SF1 into a pixel data pulse DP (DP _{1 to} DP _n ) having a pulse voltage corresponding to its logic level. For example, the column electrode driver 55 converts the pixel drive data bit of the logic level 0 that should cause the pixel cell PC to be set to the extinguishing mode, into a positive high voltage pixel data pulse DP, while the pixel cell PC For the logic level 1 pixel drive data bit to be set to the lighting mode, this is converted into a low voltage (0 volt) pixel data pulse DP. Then, the pixel data pulse DP is applied to the column electrodes D _{1 to} D _m by one display line (m) in synchronization with the application timing of the scanning pulse SP. In this application, the pixel data pulses DP _{1 to} DP _n−1 for the odd rows are sequentially applied, and then the pixel data pulses DP _{2 to} DP _n for the even rows are sequentially applied. At this time, a selection is made between the column electrode D and the row electrode Y in the selection cell C2 of the pixel cell PC to which the low-voltage (0 volt) pixel data pulse DP to be set to the lighting mode is applied simultaneously with the scanning pulse SP. Write address discharge occurs. In response to the selective write address discharge, a positive wall charge is formed on the column electrode D in the selected cell C2 of the pixel cell PC, and a negative wall charge is formed on the row electrode Y. . Further, negative wall charges are formed on the row electrodes Y in the display cells C1, and negative wall charges are also formed on the row electrodes X. On the other hand, since the pixel data pulse DP of low voltage (0 volt) is not applied to the pixel cell PC to be set in the extinguishing mode, the selective write address discharge as described above does not occur.

In the selective write address stage W _W, When the row electrodes Y ₁ to Y _n of the scan pulse SP to the applied is completed, the potential applied to the row electrodes X and Y by the scanning base pulse BP ⁺ is the peak potential V1 Gradually decreases to 0 volts.

Further, as shown in FIG. 7, the first row electrode driver 510 generates a wall charge adjustment pulse CP having a waveform that gradually reaches the negative peak potential −Ve from the 0 volt state, and outputs the wall charge adjustment pulse CP. row electrodes _{X 2, X 4, ····,} X n-2 and X _n, and the odd-numbered row electrodes _{Y 1, Y 3, Y 5} , ····, Y n-3 and Y _n-1 Apply to each. During this time, the second row electrode driver 520 also generates the wall charge adjustment pulse CP, which is output as odd-numbered row electrodes X ₁ , X ₃ , X ₅ ,..., X _n-3 and X _{n−. 1} and even-numbered row electrodes Y ₂ , Y ₄ ,..., Y _n−2 and Y _n .

In this way, immediately after the application of the scan base pulse BP ⁺ is completed, the wall charge adjustment pulse CP having the negative peak potential −Ve is applied to all the row electrodes X and Y. In response to the application of the wall charge adjustment pulse CP, a weak erasure discharge is generated in the selected cell C2 of each pixel cell PC to reduce the amount of wall charge. Due to the erasing discharge, surplus charges among the charges formed in the selected cell C2 by the selective write address discharge are erased. That is, in order to surely cause a write discharge in response to the application of a simultaneous write pulse AP, which will be described later, a part (by a predetermined amount) of wall charges remaining in the selected cell C2 at the immediately preceding stage is erased. That is, the wall charge amount is adjusted. Note that the column electrode driver 55 applies a constant positive potential as shown in FIG. 7 to all the column electrodes D during the falling period of the scan base pulse BP ⁺ and the wall charge adjustment pulse CP. Apply to.

After the application of the wall charge adjustment pulse CP, the first row electrode driver 510 generates a simultaneous write pulse AP having a negative peak potential as shown in FIG. 7 and outputs it to the odd-numbered row electrodes Y ₁ , Y ₁ . ₃ , Y ₅ ,..., Y _n−3 and Y _n−1 are applied simultaneously. Here, when the application operation of the simultaneous writing pulse AP by the first row electrode driver 510 is completed, the second row electrode driver 520 continues to apply the simultaneous writing pulse AP having a negative peak potential as shown in FIG. Is generated and applied to the even-numbered row electrodes Y ₂ , Y ₄ ,..., Y _n−2 and Y _n simultaneously. Note that the column electrode driver extends from the time when the potential of the scan base pulse BP ⁺ starts to decrease from the state of the peak potential V1 to the end of the application operation of the simultaneous write pulse AP by the second row electrode driver 520. 55 applies a constant positive potential as shown in FIG. 7 to all the column electrodes D.

  At this time, between the row electrode Y and the column electrode D in the selected cell C2 of the pixel cell PC in which the selective write address discharge is generated in each pixel cell PC in response to the application of the simultaneous write pulse AP. Write discharge is generated. That is, first, the write discharge as described above is simultaneously generated in the selected cells C2 of the pixel cells PC belonging to the odd display lines, and then the selected cells C2 of the pixel cells PC belonging to the even display lines are selected. The write discharge is generated all at once. Further, the write discharge expands into the display cell C1 through the gap r in each pixel cell PC, and a positive charge is formed on the row electrode Y in the display cell C1. That is, the pixel cell PC is set to the lighting mode in which charges having different polarities are formed on the row electrodes X and Y in the display cell C1. On the other hand, in the display cell C1 of the pixel cell PC in which the selective write address discharge has not been generated, the write discharge as described above is not generated, so that charges having the same polarity (negative polarity) are formed in the row electrodes X and Y, respectively. In other words, the light-off mode is maintained.

That is, according to the selective write address stage W _W, the simultaneous reset process R pixel cells PC are initialized to off-mode in selectively shifts to the lighting mode depending on the pixel data. The first row electrode driver 510 applies the simultaneous write pulse AP to the odd-numbered row electrodes Y ₁ , Y ₃ , Y ₅ ,..., Y _n-3 and Y _n−1. In order to prevent a reactive current flowing between the row electrodes X and Y in the selected cell C2, a pulse having the same polarity as the simultaneous write pulse AP is applied to the even-numbered pulse at the same timing as the simultaneous write pulse AP. The row electrodes X ₂ , X ₄ ,..., X _n-2 and X _n are applied simultaneously.

Here, in the sustain step I of the subfield SF1, the second row electrode driver 520 applies to the even-numbered row electrodes Y ₂ , Y ₄ ,..., Y _n-2 and Y _n as described above. simultaneously with the write pulse AP and the same timing, the odd-numbered row electrodes _{X 1, X 3, ····,} X n-3 and X _n-1 each negative sustain pulse IP _X as shown in FIG. 7 Are simultaneously applied. In response to the application of the sustain pulses IP _X, among the pixel cells PC each belonging to the odd display lines, the sustain discharge between the row electrodes X and Y within the display cell C1 of the pixel cell PC which is in the state of the lighting mode occurs Is done. Light emitted from the phosphor layer 16 in accordance with the sustain discharge is irradiated to the outside through the front transparent substrate 10.

Next, in the reset stroke R _{O of} each of the subfields SF2 to SF15, the first row electrode driver 510 increases the potential at the leading edge in proportion to the passage of time as shown in FIG. , Y _n-3 , Y _n-1 , and even-numbered row electrode X are applied to the reset pulse CRP having a sawtooth waveform to the number of odd-numbered row electrodes Y ₁ , Y ₃ , Y ₅ ,. ₂ , X ₄ ,..., X _n−2 and X _n are applied simultaneously. In response to the application of the reset pulse CRP, a weak reset discharge is generated in the row electrode Y and the column electrode D in the selected cell C2 of all the pixel cells PC belonging to each of the odd display lines, and a desired reset discharge is generated in the selected cell C2. An amount of wall charge is reformed.

In the sustain process I _P1 immediately after the reset process R _O , the first row electrode driver 510 applies the negative sustain pulse IP _Y to the odd-numbered row electrodes Y ₁ , Y ₃ , Y ₅ ,. the _{n-3, Y n-1} , at the same time to apply a negative polarity sustain pulse IP _X of the even-numbered row electrodes X _2, X _4, ····, the X _n-2 and X _n. The sustain pulse IP _Y is applied to the row electrodes Y ₁ , Y ₃ , Y ₅ ,..., Y _n-3 , Y _n-1 , and the sustain pulse IP _X is applied to the row electrodes X ₂ , X ₄ ,. While being applied to each of X _n−2 and X _n , the column electrode driver 55 applies a positive constant potential as shown in FIG. 7 to all the column electrodes D. In response to the application of the sustain pulse IP _Y or IP _X, sustain discharge is generated between the row electrodes X and Y in the display cell C1 of the pixel cells PC set to the state of the lighting mode. The light emitted from the phosphor layer 16 by the sustain discharge is irradiated to the outside through the front transparent substrate 10. Further, in response to the application of the sustain pulse IP _Y or IP _X , a weak erasing discharge for reducing the amount of wall charges is generated in the selected cell C2 of all the pixel cells PC belonging to the odd display line. By the erasing discharge, a part of the surplus charge among the charges formed in the selected cell C2 by the reset process R _O is erased. That is, in order to be reliably rise to selective erase address discharge in the selective erase address process W _OR to be described later, in the immediately preceding step, to remove the charge of the surplus remaining in the selected cell C2, a wall charge amount This adjustment is performed.

As described above, in the sustain process I _P1 , the sustain discharge is generated in the display cell C1 of the pixel cell PC in the lighting mode state, and the erase discharge for erasing the surplus charge remaining in the selected cell C2 is performed. It occurs in the selected cell C2.

In the next selective erase address process W _OR , the first row electrode driver 510 applies a scan base pulse BP ⁻ having a negative peak potential −V ₂ to the even-numbered row electrodes X ₂ , X ₄ , ····, X _n-2 and X _n, and the odd-numbered row electrodes _{Y 1, Y 3, Y 5} , ····, applied to the Y _n-3 and Y _n-1, respectively. Further, during this time, the first row electrode driver 510 applies the scan pulse SP as shown in FIG. 7 in which a positive polarity predetermined potential is superimposed on the peak potential (−V2) of the scan base pulse BP ⁻ to the odd-numbered row electrode. Y ₁ , Y ₃ , Y ₅ ,..., Y _n−3 and Y _n−1 are sequentially applied alternatively. Scanning base pulse BP ^- during application of the second row electrode driver 520, the odd-numbered sub-scan pulse SSP positive polarity row electrodes _{X 1, X 3, X 5} , ····, X n-3, X _n-1 and the even-numbered row electrodes Y ₂ , Y ₄ ,..., Y _n-2 and Y _n are applied simultaneously. The sub-scanning pulse SSP has a positive second scanning base potential V3. The column electrode driver 55 converts each data bit in the pixel drive data bit group DB (DB2 to DB15) corresponding to each subfield (SF2 to SF15) into a pixel data pulse DP having a pulse voltage corresponding to the logic level. Convert.

For example, the column electrode driver 55 converts the pixel drive data bit of the logic level 0 that should cause the pixel cell PC to be set to the extinguishing mode, into a positive high voltage pixel data pulse DP, while the pixel cell PC For the logic level 1 pixel drive data bit to be set to the lighting mode, this is converted into a low voltage (0 volt) pixel data pulse DP. Then, the pixel data pulses DP corresponding to the pixel cell PC belonging to the odd display lines among all the display lines, display line in synchronization with the application timing of the scanning pulse SP (m the number) per time to the column electrodes D ₁ ~ _Apply to D _m . At this time, between the column electrode D and the row electrode Y in the selected cell C2 of the pixel cell PC to which the low-voltage (0 volt) pixel data pulse DP to be set to the lighting mode is applied simultaneously with the scanning pulse SP. A selective erase address discharge is generated. In response to the selective erase address discharge, positive charges are formed on the column electrodes D in the selected cells C2, and negative charges are formed on the row electrodes Y. Then, the discharge expands into the display cell C1 through the gap r in the pixel cell PC, and negative charges are formed on the row electrodes Y and X in the display cell C1.

In this selective erasure address process _WOR , the pixel cells PC belonging to the odd-numbered display lines are changed from the off mode to the on mode. On the other hand, in each of the pixel cells PC belonging to the odd display line, the selective erase address discharge as described above is not generated in the selected cell C2 of the pixel cell PC to which the positive pixel voltage pulse DP is applied. Therefore, the pixel cell PC to which the positive high-voltage pixel data pulse DP is applied maintains the state (lighting mode or light-off mode) up to that point.

As described above, by executing the selective erase address process _WOR , each of the pixel cells PC belonging to the odd display line is set to one of the lighting mode and the non-lighting mode according to the pixel data.

Next, in the reset process R _{E of} each of the subfields SF2 to SF15, the second row electrode driver 520 causes the potential at the leading edge to rise in proportion to the passage of time as shown in FIG. , X _n-3 , X _n-1 , and even-numbered row electrode Y are applied to the reset pulse CRP having a sawtooth waveform that reaches the odd-numbered row electrodes X ₁ , X ₃ , X ₅ ,. ₂ , Y ₄ ,..., Y _n−2 and Y _n are applied simultaneously. In response to the application of the reset pulse CRP, a weak reset discharge is generated in the row electrode Y and the column electrode D in the selected cell C2 of all the pixel cells PC belonging to each of the even display lines. The desired amount of wall charge is reformed.

In the sustain process I _P2 immediately after the reset process R _E , the second row electrode driver 520 applies the negative sustain pulse IP _X to the odd-numbered row electrodes X ₁ , X ₃ , X ₅ ,. the _{n-3, X n-1} , at the same time to apply a negative polarity sustain pulse IP _Y of the even-numbered row electrodes Y _2, Y _4, ····, the Y _n-2 and Y _n. The sustain pulse IP _X is applied to the row electrodes X ₁ , X ₃ , X ₅ ,..., X _n-3 , X _n-1 , and the sustain pulse IP _Y is an even-numbered row electrode Y ₂ , Y ₄ ,. .., Y _n−2 and Y _n , the column electrode driver 55 applies a constant positive potential as shown in FIG. In response to the application of the sustain pulse IP _X or IP _Y, sustain discharge is generated between the row electrodes X and Y in the display cell C1 of the pixel cells PC set to the state of the lighting mode. The light irradiated from the phosphor layer 16 by the sustain discharge is irradiated to the outside through the front transparent substrate 10. Further, in response to the application of the sustain pulse IP _X or IP _Y , a weak erasing discharge for reducing the amount of wall charges is generated in the selected cells C2 of all the pixel cells PC belonging to the even display line. By this erasing discharge, a part of the electric charge that is excessive in the electric charge formed in the selected cell C2 by the reset process R _E is erased. That is, in order to ensure that a selective erasure address discharge is generated in a selective erasure address process W _ER described later, a wall charge amount that deletes an excess charge remaining in the selected cell C2 at the immediately preceding stage. This adjustment is performed.

As described above, in the sustain process I _P2 , the sustain discharge is generated in the display cell C1 of the pixel cell PC in the lighting mode state, and the erase discharge for erasing the surplus charge remaining in the selected cell C2 is performed. It occurs in the selected cell C2.

In the next selective erase address process W _ER , the second row electrode driver 520 applies the scan base pulse BP ⁻ having the negative peak potential −V 2 as shown in FIG. 7 to the even-numbered row electrodes Y ₂ , Y _4, is applied · · · ·, Y _n-2 and Y _n, and the odd-numbered row electrodes _{X 1, X 3, X 5} , ····, the X _n-3 and X _n-1, respectively. Further, during this time, the second row electrode driver 520 applies the scan pulse SP as shown in FIG. 7 in which the positive potential is superimposed on the peak potential (−V2) of the scan base pulse BP ⁻ to the even-numbered row electrode. Y ₂ , Y ₄ ,..., Y _n-2 and Y _n are sequentially applied alternatively. The scan base pulse BP ^- during the application, the first row electrode driver 510, odd-numbered row electrodes Y ₁ positive polarity sub-scanning pulse SSP (second scan base voltage _{V3), Y 3, Y 5} , · .., Y _n-3 and Y _{n-1 and} even _- numbered row electrodes X ₂ , X ₄ ,..., X _n-2 and X _n are applied simultaneously. The column electrode driver 55 converts each data bit in the pixel drive data bit group DB (DB2 to DB15) corresponding to each subfield (SF2 to SF15) into a pixel data pulse DP having a pulse voltage corresponding to the logic level. Convert.

For example, the column electrode driver 55 converts the pixel drive data bit of the logic level 0 that should cause the pixel cell PC to be set to the extinguishing mode, into a positive high voltage pixel data pulse DP, while the pixel cell PC For the logic level 1 pixel drive data bit to be set to the lighting mode, this is converted into a low voltage (0 volt) pixel data pulse DP. Then, the pixel data pulses DP corresponding to the pixel cell PC belonging to the even display lines among all the display lines, display line in synchronization with the application timing of the scanning pulse SP (m the number) per time to the column electrodes D ₁ ~ _Apply to D _m . At this time, between the column electrode D and the row electrode Y in the selected cell C2 of the pixel cell PC to which the low-voltage (0 volt) pixel data pulse DP to be set to the lighting mode is applied simultaneously with the scanning pulse SP. A selective erase address discharge is generated. In response to the selective erase address discharge, positive charges are formed on the column electrodes D in the selected cells C2, and negative charges are formed on the row electrodes Y. Then, the discharge expands into the display cell C1 through the gap r in the pixel cell PC, and negative charges are formed on the row electrodes Y and X in the display cell C1. Therefore, at this time, the pixel cells PC belonging to the odd-numbered display lines shift from the extinguishing mode to the lighting mode. On the other hand, in each of the pixel cells PC belonging to the even display line, the selective erasure address discharge as described above is not generated in the selected cell C2 of the pixel cell PC to which the positive pixel voltage pulse DP is applied. Therefore, the pixel cell PC to which the positive high-voltage pixel data pulse DP is applied maintains the state (lighting mode or light-off mode) up to that point.

As described above, by executing the selective erasure address process W _ER , each of the pixel cells PC belonging to the even display line is set to one of the lighting mode and the non-lighting mode according to the pixel data.

In the sustain process in the subfield SF3 and later is carried out immediately after completion of the selective erase address process W _OR I, the second row electrode driver 520, the sustain pulse IP _X of odd-numbered row electrodes X having a negative peak potential ₁ , X ₃ , X ₅ ,..., X _n-3 , and X _n−1 , and at the same time, a sustain pulse IP _Y having a negative peak potential is applied to the even-numbered row electrodes Y ₂ , Y _4. ,..., Y _n-2 and Y _n are applied to each. Next, the first row electrode driver 510 applies a sustain pulse IP _Y having a negative peak potential to odd-numbered row electrodes Y ₁ , Y ₃ , Y ₅ ,..., Y _n-3 , and Y _{n. -1} and simultaneously, a sustain pulse IP _X having a negative peak potential is applied to each of the even-numbered row electrodes X ₂ , X ₄ ,..., X _n-2 , and X _n . The application of the sustain pulse is repeated alternately. In response to the application of the sustain pulse IP _Y or IP _X , a sustain discharge is generated between the row electrodes X and Y in the display cell C1 of the pixel cell PC in the lighting mode, and the phosphor layer is accompanied by this sustain discharge. Light irradiated from 16 is irradiated to the outside through the front transparent substrate 10.

The drive control circuit 54 executes the drive shown in FIGS. 6 and 7 based on 16 types of pixel drive data GD as shown in FIG. According to such driving, as shown in FIG. 5, a write address discharge is first generated in each pixel cell PC in the first subfield SF1 except when the luminance level 0 is expressed (first gradation) ( This pixel cell PC is set to the lighting mode. Thereafter, the selective erase address discharge is generated only by the selective erase address process W _OR (or W _ER ) of one subfield of each of the subfields SF2 to SF15 (indicated by black circles), and then the pixel cell PC is turned off. Set to mode. In other words, each pixel cell PC is set to the lighting mode in each of the continuous subfields corresponding to the intermediate luminance to be expressed, and the light emission associated with the sustain discharge is repeated for the number of times assigned to each of these subfields. Occur (indicated by white circles). At this time, the luminance corresponding to the total number of light emission associated with the sustain discharge generated in one field is visually recognized. Therefore, according to the 16 types of light emission patterns by the 1st to 16th gradation driving as shown in FIG. 5, the intermediate for 16 gradations corresponding to the total number of sustain discharges generated in each of the subfields indicated by white circles. Luminance is expressed.

Here, in the plasma display device shown in FIG. 1, the pixel cell PC which carries each pixel of the PDP 50 is constructed by the display cell C1 and the selection cell C2 as shown in FIGS. The sustain discharge related to the display image is generated in the display cell C1, while the reset discharge and the address discharge accompanied by the light emission not related to the display image are mainly generated in the selected cell C2. . At this time, the selected cell C2 has a black or dark light shielding layer as shown in FIG. 3 in order to reduce the amount of light emitted along with various discharges as described above passing through the front transparent substrate 10 and leaking outside. An SHD and a light-shielding conductive layer BE are provided. That is, since a part of the light emitted in response to the reset discharge and address discharge generated in the selected cell C2 is blocked by the light-shielding conductive layer BE, the contrast of the display image, particularly the dark contrast can be increased. become. Further, in the selected cell C2, a secondary electron emission material layer 30 is provided on the back substrate 13 side as shown in FIG. The secondary electron emission material layer 30 has good γ characteristics for emitting secondary electrons during discharge in which the formation surface becomes a cathode. Therefore, in the selective write address process W _W of the first subfield SF1, and at the same time applying a scan pulse SP having a positive polarity as shown in FIG. 7 to the row electrodes Y, applying a pixel data pulse DP of 0 volt to the column electrodes D By doing so, the column electrode D is set relatively on the cathode side to generate an address discharge. As a result, the secondary electron emission material layer 30 formed in the selected cell C2 becomes the cathode side, so that secondary electrons can be effectively emitted from the secondary electron emission material layer 30 and the selection is made. The address discharge is surely generated in the cell C2. In the simultaneous reset process R of the first subfield SF1, the address discharge is performed in order to prevent erroneous address discharge between the row electrode Y and the column electrode D other than the row electrode Y to which the scan pulse SP is applied. Similarly, a reset discharge is caused between the row electrode and the column electrode. When a reset discharge is generated between the row electrode Y and the column electrode D, a positive wall charge is formed on the column electrode D and a negative wall charge is formed on the row electrode Y in the selected cell C2. . In such a state of wall charge formation, in order to cause an address discharge in the selected cell C2 by applying a positive scan pulse SP, it is necessary to set the scan pulse SP to a high voltage. In other words, when a positive wall charge is formed on the column electrode D and a negative wall charge is formed on the row electrode Y in the selected cell C2, a relatively high voltage is not applied between the column electrode D and the row electrode Y. As long as no discharge occurs, erroneous discharge is prevented.

Further, when the selective erasure address process (W _OR , W _ER ) is performed in each of the subfields SF2 to SF15, a series of processes as described below are executed immediately before that.

That is, first, in the reset process (R _O , R _E ), a weak reset discharge is generated in the selected cell C2 by applying a positive reset pulse CRP as shown in FIG. The wall charges in the selected cell C2 are regenerated. Next, in the sustain process (I _P1 , I _P2 ), the sustain discharge is performed in the display cell C1 by the last sustain pulse IP _X or IP _Y applied immediately before the selective erase address process (W _OR , W _ER ). A weak erasing discharge is generated in the selected cell C2 to be generated and to reduce the amount of wall charges. At this time, due to the erasing discharge, a part of the surplus charge among the charges formed in the selected cell C2 by the reset process (R _O , R _E ) is erased. That is, in order to surely cause the selective erasure address discharge in the selective erasure address process _WOR or _WER , the wall charge that deletes the surplus charge remaining in the selected cell C2 at the immediately preceding stage. The amount is adjusted.

Therefore, according to such driving, even if the electric charge remaining in the selected cell C2 is interfered by the sustain discharge generated in the display cell C1, it is immediately before the selective erase address process (W _OR , W _ER ). In each selected cell C2, an appropriate amount of wall charge is reformed. Accordingly, in the selective erasure address process (W _OR , W _ER ) of each subfield, each pixel cell PC can be reliably set to a state (lit cell state or unlit cell state) according to the pixel data. .

Further, according to such driving, an electric field is generated by applying the sub-scanning pulse SSP in the selective erasure address processes W _OR and W _ER , the selective discharge in the selected cell C 2 is expanded in the display cell C 1, and the selection margin ( Selective erasure margin) is expected to improve significantly. Thereby, the erasing of the wall charges in the display cell C1 is surely executed.

Further, the odd-numbered row electrodes Y ₁ , Y ₃ , Y ₅ ,..., Y _n-3 and Y _n−1 to which the scan pulse SP is applied immediately before the selective erase address process W _OR have negative polarity. sustain pulse IP _Y is applied, the even-numbered row electrodes Y _2, Y ₄ to which the scan pulse SP is applied immediately before the selective erase address process W _ER, · · · ·, negative electrode Y _n-2, and Y _n Since the characteristic sustain pulse IP _Y is applied, the state of the wall charges immediately before the selective erasing address process W _OR , W _ER can be made easy to cause address discharge.

Further, in the selective erasure address processes W _OR and W _ER , the second scan base potential V3 applied to the row electrode X as compared with the first scan base potential −V2 of the scan base pulse BP ⁻ applied to the row electrode Y. Therefore, the selective erasure discharge in the selected cell C2 is sufficiently expanded to the display cell C1, and the wall charge in the display cell C1 is surely erased.

  As described above, according to the present invention, an electric field is generated by the application of the second scanning base potential in the selective erase address process, and the selective discharge in the selected cell is sufficiently expanded in the display cell, thereby improving the selective erase margin. Therefore, the wall charge in the display cell is surely erased. Therefore, the continuation of the lighting state of the pixel cell that should be in the erased state is prevented.

It is a figure which shows the structure of the plasma display apparatus as a display apparatus by this invention. It is the top view which looked at a part of structure of the display electrode formation part DPE in PDP50 shown by FIG. 1 from the display surface side. It is a figure which shows the cross section on the VV line | wire shown by FIG. It is a figure which shows the cross section on the WW line shown by FIG. It is a figure which shows the light emission drive pattern based on the conversion table of pixel data, and the pixel drive data GD obtained by this pixel data conversion table. It is a figure which shows an example of the light emission drive sequence in the plasma display apparatus shown by FIG. It is a figure which shows the various drive pulses applied to PDP according to the light emission drive sequence shown in FIG. 6, and its application timing.

Explanation of symbols

50 PDP
54 drive control circuit 55 address driver 510 first row electrode driver 520 second row electrode driver C1 display cell C2 selection cell DPE display electrode formation portion PC pixel cell

Claims (11)

A front substrate and a rear substrate facing each other with a discharge space interposed therebetween, a plurality of row electrode pairs constituting display lines on the inner surface of the front substrate and a dielectric layer covering the row electrode pairs, and the rows on the inner surface of the rear substrate A plurality of column electrodes arranged to intersect with the electrode pairs, and a display cell, a light shielding layer, and a secondary electron emission layer are provided at each intersection of the row electrode pair and the column electrode A display panel in which a unit light emitting area composed of a selected cell is formed is displayed in a unit display period consisting of a plurality of subfields each including an address period and a sustain period according to pixel data for each pixel based on an input video signal A display panel driving method for driving every time,
Performing a selective write address process in the address period of the first subfield within the unit display period, and performing a selective erase address process in each address period of the subfield group following the first subfield;
In the address period of the subfield in which the selective erasing address process is performed, the positive electrode superimposed on the first scanning base potential having a negative polarity on one row electrode of the row electrode pair in a relation that the column electrode side is relatively negative. And applying a positive second scan base potential to the other row electrode of the row electrode pair, applying a positive scan pulse, applying a pixel data pulse corresponding to the pixel data to the column electrode, and applying a positive second scan base potential to the other row electrode of the row electrode pair A display panel driving method, wherein a selective erasure address discharge is generated between the column electrode and the one row electrode in a cell.   2. The display panel driving method according to claim 1, wherein a negative sustain pulse is applied to the row electrode pair in the sustain period.   3. The negative sustain pulse is applied to the one row electrode on the side to which the scan pulse is applied, immediately before an address period of a subfield in which the selective erase address process is executed. Driving method of display panel.   Immediately before the address period of the first subfield of the unit display period, a reset pulse is applied between one row electrode constituting the row electrode pair and the column electrode so that the column electrode is relatively negative. 2. The method of driving a display panel according to claim 1, further comprising a reset period in which a reset discharge is generated in the selected cell when applied.   2. The display panel driving method according to claim 1, wherein the light shielding layer is formed on the front substrate side in the selected cell.   2. The display panel driving method according to claim 1, wherein the secondary electron emission layer is formed on the back substrate side in the selected cell.   2. The display panel driving method according to claim 1, wherein a phosphor layer is formed only in the display cell among the display cell and the selected cell.   The display cell includes a portion where the one row electrode constituting the row electrode pair and the other row electrode are opposed to each other through a first discharge gap in a discharge space, and the selected cell is the column electrode 2. The display panel driving method according to claim 1, further comprising a portion where the first row electrode and the first row electrode face each other with a second discharge gap in the discharge space. The one row electrode and the other row electrode constituting the row electrode pair are respectively arranged in a column direction from the main body portion via the first discharge gap for each unit light emitting region and a main body portion extending in the row direction. And a protruding portion that protrudes,
The first discharge cell includes a portion where the projecting portion is opposed to the first discharge gap in the discharge space, and the second discharge cell has the column electrode and the main body of the one row electrode in the discharge space. The display panel driving method according to claim 1, further comprising a portion opposed to each other through the second discharge gap. The display panel includes a partition wall including a vertical wall section that divides a discharge space of adjacent unit light emitting areas in a row direction and a horizontal wall section that partitions in a column direction, the discharge space of the display cells in the unit light emitting area, and the selection. A partition wall that partitions the discharge space of the cell,
The discharge space of the selected cell is closed by the discharge space of the adjacent unit light emitting region and the partition, and the discharge space of the display cell in the unit light emitting region and the discharge space in the selected cell communicate with each other. The display panel driving method according to claim 1, wherein:   2. The display panel driving method according to claim 1, wherein the discharge spaces of the display cells in the unit light emitting regions adjacent to each other in the row direction communicate with each other.

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