JP2008024411A - Elevator controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To maintain the interchangeability of each constituent member for a long time without changing the hardware and the software of a peripheral member of a flash ROM including a program of a CPU even if the change of specifications such as the block size of the flash ROM becomes necessary due to a use for a long time. <P>SOLUTION: A flash ROM interface circuit 13 is inserted between a bus line 4 and the flash ROM 8a. The flash ROM interface circuit 13 has such functions that access to a block by the block size B<SB>B</SB>of the flash ROM 8a when a block access demand of a basic block size B<SB>A</SB>set in the CPU 5 is inputted into the flash ROM 8a from the CPU 5 and converts an access response obtained from the flash ROM 8a into an access response of the basic block size B<SB>A</SB>to feed it into the CPU 5. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an elevator control device that controls the operation of an elevator installed in a building such as a building in accordance with a predetermined control operation program and various setting data.

  In an elevator system including one or a plurality of elevators incorporated in a building such as a building, a hall call is registered by a button operation by a user of a hall call registration device installed in an elevator hall on each floor. When the hall call is registered, the hall call is assigned to, for example, one elevator having the shortest response time from among the plurality of elevators. As a result, the elevator car moves to the floor where the hall call is registered and opens the door. When the passenger gets into the elevator car and designates the going floor with the button of the car call registration device provided in the car, the door is closed and the elevator car starts moving to the designated floor.

  An elevator control device including, for example, a computer incorporated in the above-described elevator system controls the basic operation of the above-described elevator according to a predetermined control operation program and various setting data.

  On the other hand, with the advancement of electronics technology, the above-described elevator control apparatus has adopted a microcomputer in which a CPU, ROM, RAM, various interfaces, various input / output circuits, etc. are mounted on a printed wiring board. (See Patent Document 1).

  And the control operation program mentioned above is written in ROM of the elevator control apparatus which consists of this microcomputer. Then, the CPU sequentially reads and executes the control operation program and various setting data written in the ROM by a program written in hardware in advance. Furthermore, in recent years, the storage location of the control operation program has changed from the conventional ROM to the flash ROM.

  FIG. 7 is a schematic diagram showing a schematic configuration of an elevator control device including the microcomputer described above.

  A CPU (Central Processing Unit) 5, a bus control unit 6, an SRAM 7, a flash ROM 8, an EEPROM 9, an input / output circuit 10, and a serial bus line 4 including an address bus 1, a data bus 2, and a plurality of control buses 3a and 3b. An input / output circuit 11 and the like are connected.

  The bus control unit 6 performs control so that data does not collide with each of the buses 1, 2, 3a, and 3b. In the SRAM 7, various variable data necessary for controlling the operation of each elevator is stored. The variable data includes, for example, the current position of each elevator, an unanswered hall call registered by each hall call registration device, an unanswered car call registered by each car call registration device, and the like.

  The flash ROM 8 stores various setting data such as the aforementioned control operation program and various parameters necessary for elevator control. Further, other data is set in the EEPROM 9.

  A drive signal is applied from the input / output circuit 10 to a drive circuit for a hoist that actually moves each elevator up and down, and a signal indicating the state of the elevator is input to the input / output circuit 10. Furthermore, a hall call and a car call are input to the serial input / output circuit 11 as a serial signal from the hall call device on each floor and the car call registration device of each elevator. Further, a monitoring center of an elevator management company is connected to the serial input / output circuit 11 via a communication line.

As is well known, the flash ROM 8 is an electrically rewritable ROM. In addition to being able to read, write, and erase data (or instructions) byte by byte, it is shown in FIG. As described above, data (or instructions) can be read, written, and erased in units of blocks 12. The block size (address width) B _A of each block 12 can be arbitrarily set according to the specification of the flash ROM 8.

  In this elevator control apparatus, the case where the CPU 5 performs elevator control will be described as an example. In general, the CPU of the microcomputer designates each address of the ROM in order, for example, in accordance with a program (access program) preset in itself, and executes each instruction of the program stored in the address. Read sequentially and execute the instruction.

  Therefore, also in the elevator control device of FIG. 7, when the CPU 5 accesses the flash ROM 8 according to its own program, the address AD indicating the data to be accessed or the write position is output to the address bus 1 and the read signal (RD) Alternatively, a write signal (WE) is output to the control bus 3a. Then, the bus control unit 6 specifies the flash ROM 8 to be accessed from the address AD output to the address bus 1, and a CS (chip select) signal is output to the flash ROM 8 via the control bus 3b.

  In the case of the read signal (RD), the flash ROM 8 specified by the CS (chip select) signal reads the data stored at the input address AD and outputs it to the data bus 2. In the case of the write signal (WE), the data DA output to the data bus 2 is written to the input address AD.

In this case, when data is written by designating the block 12 in the flash ROM 8, the CPU 5 designates the head address of the block 12 and writes the data with the write signal (WE) output. If a plurality of power data DA is output to the data bus 2, a plurality of data DA is written to each address in the designated block 12 in the flash ROM 8 at a time. Data reading and data erasing in block units are performed in the same procedure.
Japanese Patent Laid-Open No. 2004-210506

  However, as described above, the elevator control apparatus in which the flash ROM 8 storing the control operation program for controlling the basic operation of the elevator also has the following problems to be improved.

  That is, the software mounting method using the flash ROM 8 is a very general software mounting method. However, since the flash ROM 8 needs to be incorporated into an elevator control device for controlling the operation of the elevator and used for a long period of time, the flash ROM 8 needs to be a compatible part in consideration of the service life of the parts. .

  However, as with other general electronic parts, the flash ROM 8 has been changed in specification or production has been discontinued, and the same parts, fully compatible parts, or parts having upward compatibility are often not available. .

  In such a situation, the specifications differ from the conventional parts that have been used so far, but new parts that ensure the functions of the conventional parts are adopted, and the parts around this part correspond to the specifications of the new parts. By exchanging with a new part having the specification to be used, long-term operation has been secured in the apparatus in which this part is incorporated.

For example, the block size B _A (address width) of each block 12 in the flash ROM 8 shown in FIG. 8 is set in the CPU program that accesses the flash ROM 8 and the bus control unit 6 that controls the CPU access. Therefore, when the flash ROM 8 is replaced with a new flash ROM having a different block size B _A (address width) for each block 12, the program of the CPU 5 is changed and the circuit of the bus control unit 6 is changed to support the new flash ROM. It is necessary to read, write and erase.

  However, as described above, it is expected that the life of the components of the flash ROM 8 will be exhausted a plurality of times within the period of use of the elevator control device over a long period of several tens of years. In other words, a large amount of cost, labor, and time are required to change the hardware specifications and software specifications of the peripheral members of the flash ROM including the CPU program.

  Also, as mentioned above, elevators have a long product life and need to provide a long-term compatible elevator control system, and long-term compatibility to maintain elevator control systems already on the market There is a need to continue to create a unique elevator control system.

  In addition, there are special additional specifications for each elevator and the software is often different, and it is impossible to change the software in accordance with a new elevator control device. Therefore, the control operation program and various setting data written in the flash ROM may be rewritten. In such a case, parts may be replaced with a new flash ROM having a new specification.

  The present invention has been made in view of such circumstances, and even if specification changes such as the block width of the flash ROM that stores the control operation program for controlling the operation of the elevator occur, the CPU program is included. It is an object of the present invention to provide an elevator control device that can maintain compatibility of components over a long period of time without changing hardware and software of peripheral members of the flash ROM and can also reduce maintenance costs. To do.

  The present invention is applied to an elevator control device that controls the operation of an elevator based on a predetermined control operation program and various setting data. In order to solve the above problems, in the present invention, a block in which a control operation program and various setting data are written to the bus line via at least the CPU, the bus control unit, and the flash ROM interface circuit. The flash ROM interface circuit connects the flash ROM that can be accessed in units. When a block access request of the basic block size set in the CPU is input from the CPU to the flash ROM, the flash ROM interface circuit accesses the flash ROM with the block size of the flash ROM. The access response obtained from the flash ROM is converted into the access response of the basic block size and sent to the CPU.

  In the elevator control apparatus configured as described above, the useful life of the currently incorporated flash ROM is exhausted, and the same control is performed on the flash ROM having a block size different from the block size (basic block size) of the flash ROM. Even if an operation program is written and incorporated in the elevator controller, the access request to the flash ROM in which the CPU designates a block of the basic block size based on the program set in the CPU is not changed. It is converted into an access request designating a block of a size, and the changed flash ROM is correctly accessed.

  Therefore, even if specification changes such as the block size of the flash ROM that stores the control operation program and various setting data occur, the hardware and software of the peripheral members of the flash ROM including the CPU program are changed. Therefore, compatibility of each component can be maintained over a long period of time, and maintenance costs can be reduced.

  Further, a flash ROM interface circuit of an elevator control device according to another invention includes code conversion means for converting a code of an instruction input via a bus line into a code of the same instruction in the flash ROM.

  Accordingly, even if the instruction code used in the writing / reading control unit of the replaced flash ROM is changed, it is not necessary to convert the instruction code on the CPU side.

  Further, the CPU of the elevator control device of another invention has a wait function for temporarily stopping its own processing operation. The flash ROM interface circuit has wait function instruction means for sending a wait function execution instruction to the CPU during an access period in which a block for the flash ROM is designated.

  Furthermore, the CPU of the elevator control apparatus of another invention is provided with a watch dog timer for monitoring a time interval between its own processing operations. The flash ROM interface circuit includes a watchdog timer stop instruction means for instructing the CPU to stop the timing operation of the watchdog timer during an access period in which a block for the flash ROM is designated.

  In the present invention, even if the specification change such as the block size of the flash ROM for storing the control operation program and the like occurs, the hardware and software of the peripheral members of the flash ROM including the CPU program are changed. In addition, the compatibility of each component can be maintained over a long period of time.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic diagram showing a schematic configuration of an elevator control apparatus according to an embodiment of the present invention. The same parts as those of the conventional elevator control apparatus shown in FIG. 7 are denoted by the same reference numerals, and detailed description of the overlapping parts is omitted.

  A CPU (Central Processing Unit) 5, a bus control unit 6, an SRAM 7, a flash ROM interface circuit 13, an EEPROM 9, an input / output circuit with respect to a bus line 4 including an address bus 1, a data bus 2, and a plurality of control buses 3a and 3b. 10, a serial input / output circuit 11 and the like are connected. The flash ROM interface circuit 13 is connected to a flash ROM 8a.

As shown in FIG. 2, a plurality of blocks 12a are formed in the flash ROM 8a. As in the conventional flash ROM 8 shown in FIGS. In addition to being able to read, write, and erase for each byte, data (or instructions) can be read, written, and erased in units of block 12a. However, the block size (address width) B _B of each block 12a is different from the block size (address width) B _A of the block 12 in the conventional flash ROM 8 shown in FIG. In this embodiment, the block size (address width) B _B of the block 12 a is set to ½ of the block size (address width) B _A of the block 12 in the conventional flash ROM 8. In the flash ROM 8a, a control operation program for controlling the operation of each elevator and various setting data are written as in the conventional flash ROM 8.

  The specifications of the CPU (central processing unit) 5, bus control unit 6, SRAM 7, EEPROM 9, input / output circuit 10, serial input / output circuit 11 and the like are the CPU (central processing unit) of the conventional elevator control device shown in FIG. 5 is the same as the bus control unit 6, SRAM 7, EEPROM 9, input / output circuit 10, and serial input / output circuit 11.

Therefore, the program for accessing the flash ROM set in the CPU 5 is such that, for example, when a block is designated and the flash ROM is accessed, the block size is first connected to the bus line 4 of the elevator control device. The access process is executed assuming that the block size B _A of the block 12 of the flash ROM 8 is the same. In the embodiment, the block size B _A set in the program of the CPU 5 is the basic block size.

Therefore, in this state, CPU 5 via the bus control unit 6, the flash ROM8a block size is a specification change to the new block size B _B, can not enforce access to the specified block. Therefore, the flash ROM interface circuit 13 sends an access request to the flash ROM designating a block of the basic block size B _A input via the bus line 4 to a new block size B currently incorporated in the elevator controller. _It is converted into an access request for the flash ROM 8a in which the _B block 12a is formed, and is sent to the flash ROM 8a.

  FIG. 3 is a diagram showing a flow of signals, data, and instructions exchanged with the CPU 5, the bus control unit 6, the flash ROM interface circuit 13, and the flash ROM 8a in the elevator control device of FIG.

  A program 14 for accessing the flash ROM 8 a and the EEPROM 9 is written in the CPU 5. Further, a watchdog timer 15 is connected to the CPU 5 for monitoring the time interval between its own processing operations. The CPU 5 is provided with a wait control unit 16 that temporarily stops (waits) its own processing operation based on the interruption of a ready signal from the outside.

  In the flash ROM interface circuit 13, an instruction determination unit 17, a block correspondence memory 18, a code conversion unit 19, a wait control instruction unit 20, a watchdog timer control unit 21, a reading unit 22, a writing unit 23, a block writing unit 24, a block erase unit 25, a status detection unit 26, and the like.

Block 12a of the block size B _B described above is formed in the flash ROM8a. The flash ROM 8a can be accessed for writing and erasing in units of the block 12a, but can also be accessed for reading, writing and erasing in units of bytes specifying individual addresses. Further, the above-described write / read control unit 28 is provided in the flash ROM 8a.

  The write / read control unit 28 performs writing and reading with respect to the actual memory array 27 in which each block 12a is formed, and also writes the writing result (writing completion status) and the erasing result (erasing completion status) as data. The data is transmitted from the terminal 34 to the flash ROM interface circuit 13 via the data bus (ROM DA).

The block correspondence memory 18 in the flash ROM interface circuit 13 stores the relationship between the reference block size B _A set in the program 14 of the CPU 5 and the block size B _B of the flash ROM 8a currently connected. Yes.

  The instruction determination unit 17 includes a control bus (R / D) from the CPU 5, a write signal (FRD) input via the bus control unit 6, a CS (chip select) signal designating itself, and an address AD of the address bus 1. Based on the data DA of the data bus 2, the type of the input access (command) is determined. Specifically, a read instruction in units of bytes specifying the address AD, a write instruction in units of bytes specifying the address AD and write data, a write in units of blocks specifying the top address of the block and a plurality of write data It is determined that the instruction, block start address, and a plurality of erase data (null data) are designated as a block unit erase instruction.

  The code conversion unit 19 uses the code of each instruction adopted by the write / read control unit 28 of the flash ROM 8a currently connected, and the CPU 5 and the bus control unit 6, that is, the previous flash ROM 8 When the code of each instruction in the read / write control unit does not match, the instruction code input from the bus control unit 6 is converted into the code of the instruction adopted in the currently connected flash ROM 8a, Send to flash ROM 8a.

  For example, a code [00] read instruction is converted into a code [55] read instruction, a code [01] write instruction is converted into a code [66] write instruction, and the code [10] is erased. The instruction is converted into an erase instruction with code [77].

  The wait control instruction unit 20 cuts off the ready (RADY) signal to the CPU 5 during the execution period of the write instruction in which the flash ROM interface circuit 13 designates the block to the flash ROM 8a and the erase instruction in which the block is designated. Then, the wait control unit 16 in the CPU 5 is operated to suppress the CPU 5 from proceeding to the next step.

  Similar to the wait control instruction unit 20 described above, the watchdog timer control unit 21 performs a watchdog operation on the CPU 5 during the execution period of the write command designating the block and the erase command designating the block with respect to the flash ROM 8a. The timer 15 is instructed to stop the timing operation. As described above, since the CPU 5 is not performing processing during the long processing period for the flash ROM 8a, it is possible to prevent the time value of the watch dog timer 15 from exceeding an allowable value and making an abnormality determination.

  4, 5, and 6 are flowcharts showing the overall operation including the reading unit 22, the writing unit 23, the block writing unit 24, and the block erasing unit 25 in the flash ROM interface circuit 13.

  When the CPU 5 accesses the flash ROM 8a, the address AD indicating the data to be accessed or the write position is output to the address bus 1, and the read signal (RD) or the write signal (WE) is output to the control bus 3a. Then, the bus control unit 6 specifies the flash ROM 8a to be accessed from the address AD output to the address bus 1, and outputs an FCS (chip select) signal to the flash ROM interface circuit 13 of the flash ROM 8a via the control bus 3b. At the same time, the read signal (FRD) or the write signal (FWE) from the CPU 5 is relayed to the flash ROM interface circuit 13 via the control bus 3a.

  When the flash ROM interface circuit 13 specified by the FCS (chip select) signal in the control bus 3b receives the read signal (FRD) or the write signal (FWE) from the control bus 3a (step S1), the instruction determination unit 17 Is activated to determine the type of the access command input from the CPU 5 this time. Specifically, it is determined whether the read command is a byte unit, a write command is a byte unit, a write command is a block unit, or an erase command is a block unit (S2).

  When the access command is a read command in byte units (S3), the read unit 23 applies the address AD input from the address bus 1 to the address terminal 31 of the flash ROM 8a as a read address, and reads (read enable) signal. (ROMRD) is applied to the RD terminal 32, and a CS signal (ROMCS) is applied to the CS terminal 33 (S4).

  Then, the writing / reading control unit 28 of the flash ROM 8a operates to read the data at the corresponding address in the flash ROM 8a and transmit it from the data terminal 34 to the flash ROM interface circuit 13. The reading unit 23 transmits the data DA input from the flash ROM 8a to the CPU 5 via the data bus 2 (S5).

  When the input access command is a write command in units of bytes (S6), the writing unit 23 applies the address AD input from the address bus 1 as a write address to the address terminal 31 of the flash ROM 8a, and the data bus 2 is applied as data to the data terminal 34 of the flash ROM 8a, a write (write enable) signal (ROMWE) is applied to the W terminal 35, and a CS signal (ROMCS) is applied to the CS terminal 33. (S7).

  Then, the write / read control unit 28 of the flash ROM 8a operates to write the data DA to the corresponding address in the flash ROM 8a, and transmit the write completion status from the data terminal 34 to the flash ROM interface circuit 13. Specifically, 1-bit “status register” for 1 address of “1” indicating completion of normal writing is transmitted.

  When receiving the write completion status, the status detection unit 26 of the flash ROM interface circuit 13 transmits the write completion to the CPU 5 via the data bus 2 (S8).

When the input access instruction is a block-unit write instruction designating a block (S9), the block writing unit 24 sets the basic block size B _A designated by the address bus 1 in S10 of FIG. After the block address and write (WE) signal are sent to the address terminal 31 and WE (write) terminal 35 of the flash ROM 8a, a plurality of data contained in this block are continuously sent to the data terminal 34 of the flash ROM 8a. (S10).

  Then, the write / read control unit 28 of the flash ROM 8a sequentially writes each input data DA from the designated address to each address AD, and the data DA is normally written to each address. A write result of “1” and “0” in the case of abnormality is sequentially output from the data terminal 34 to the flash ROM interface circuit 13 as a status register.

  At the same time, the block writing unit 24 of the flash ROM interface circuit 13 transmits incomplete block writing to the CPU 5 (S11). Further, the watchdog timer control unit 21 instructs the CPU 5 to stop the time counting operation of the watchdog timer 15. Further, the weight control instruction unit 20 blocks the ready (RADY) signal to the CPU 5 and operates the weight control unit 16 in the CPU 5 to suppress the CPU 5 from proceeding to the next step (S12).

The status detection unit 26 reads the status register for each address sequentially output from the write / read control unit 28 of the flash ROM 8a (S13), and the block size B _B (address width) set in the currently connected flash ROM 8a. When the number of status registers corresponding to “1” is obtained (S14), writing of each data to one block 12a included in the basic block size B _A specified by the address bus 1 is completed. In S15, if there is unwritten data among all data included in the basic block size B _A sent to the flash ROM 8a, the process returns to S12.

  When the writing to all the data sent to the flash ROM 8a in S15 is completed, the stop of the timing operation of the watchdog timer control unit 21 output to the CPU 5 is released (S16). Further, the CPU 5 is notified of the completion of block writing (S17). Finally, the wait control instruction unit 20 sends a ready (RADY) signal to the CPU 5 to release the wait state of the wait control unit 15 of the CPU 5 (S18).

  In S19 of FIG. 4, when the input access command is a block unit erase command designating a block, the block erase unit 25 transmits incomplete block erase to the CPU 5 in S20 of FIG. 6 (S20). . Further, the watchdog timer control unit 21 instructs the CPU 5 to stop the time counting operation of the watchdog timer 15. Further, the weight control instruction unit 20 blocks the ready (RADY) signal to the CPU 5 and operates the weight control unit 16 in the CPU 5 to suppress the CPU 5 from proceeding to the next step (S21).

The address of the block having the basic block size B _A designated by the address bus 1 and the write (WE) signal are sent to the address terminal 31 and the WE (write) terminal 35 of the flash ROM 8a and then included in this block. A plurality of erased data (0 or null data) to be transmitted are continuously transmitted to the data terminal 34 of the flash ROM 8a (S22).

  Then, the writing / reading control unit 28 of the flash ROM 8a sequentially writes the erasure data inputted sequentially from the designated address to each address AD, and when the erasure data is normally written to each address, “ In the case of abnormality, the erase result of “0” is sequentially output from the data terminal 34 to the flash ROM interface circuit 13 as a status register.

The status detector 26 of the flash ROM interface circuit 13 reads the status register for each address sequentially output from the write / read controller 28 of the flash ROM 8a (S23), and the block set in the currently connected flash ROM 8a. When the number of "1" status registers corresponding to the size B _B (address width) is obtained (S24), each data for one block 12a included in the basic block size B _A designated by the address bus 1 is obtained. since erasing is completed, at S25, if there data unerased out of all data included in the basic block size B _a that sent to the flash ROM8a, it returns to S21.

  When the erasure of all data sent to the flash ROM 8a in S25 is completed, the stop of the timing operation of the watchdog timer control unit 21 output to the CPU 5 is released (S26). Further, the CPU 5 is notified of the completion of block erase (S27). Finally, the wait control instruction unit 20 sends a ready (RADY) signal to the CPU 5 to release the wait state of the wait control unit 15 of the CPU 5 (S28).

  In the elevator control device configured as described above, even if the block size B of the flash ROM 8 is changed due to a specification change due to the component life during a long period of use, for example, The elevator control device can be continuously used without changing the program of the CPU 5 for each elevator system that is stored and read and executed by the CPU 5.

  Even if the instruction code of the flash ROM changes, it is possible to continue using the elevator control device without changing the program of the CPU 5 described above. Furthermore, even if the block size or instruction code of the flash ROM changes, the method of sending an incomplete notification to the CPU 5 cannot be handled because the access to the flash ROM is controlled by time management due to the configuration of the program executed by the CPU 5. Even in this case, the elevator controller can be continuously used without changing the program of the CPU 5.

  Furthermore, even when the access to the flash ROM is a time management control, the watchdog timer 15 is cleared. Therefore, the elevator controller can be automatically restored even when access to the flash ROM becomes abnormal.

The schematic diagram which shows schematic structure of the elevator control apparatus concerning one Embodiment of this invention. The figure which shows the structure of the flash ROM incorporated in the elevator control apparatus of the embodiment The block diagram which shows the structure of the flash ROM interface circuit integrated in the elevator control apparatus of the embodiment Flowchart showing the operation of the flash ROM interface circuit incorporated in the elevator control device of the same embodiment Flowchart showing the operation of the flash ROM interface circuit incorporated in the elevator control device of the same embodiment Flowchart showing the operation of the flash ROM interface circuit incorporated in the elevator control device of the same embodiment Schematic diagram showing the schematic configuration of a conventional elevator control device The figure which shows the structure of the flash ROM incorporated in the elevator control apparatus

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Address bus, 2 ... Data bus, 3a, 3b ... Control bus, 4 ... Bus line, 5 ... CPU, 6 ... Bus control part, 8, 8a ... Flash ROM, 9 ... EEPROM, 10 ... I / O circuit, 11 ... Serial input / output circuit, 12, 12a ... Block, 13 ... Flash ROM interface circuit, 14 ... Program, 15 ... Watchdog timer, 16 ... Wait control unit, 17 ... Instruction determination unit, 18 ... Memory for block, 19 ... Code Conversion unit, 20 ... wait control instruction unit, 21 ... watchdog timer control unit, 22 ... reading unit, 23 ... writing unit, 24 ... block writing unit, 25 ... block erasing unit, 26 ... status detection unit, 28 ... Write / read control unit, 31 ... address terminal, 32 ... RD end, 33 ... CS terminal, 34 ... data terminal, 35 ... WE terminal

Claims (4)

In an elevator control device that controls the operation of an elevator based on a predetermined control operation program and various setting data,
A flash ROM that can be accessed in block units in which the control operation program and various setting data are written is connected to the bus line via at least a CPU, a bus control unit, and a flash ROM interface circuit.
The flash ROM interface circuit, when a block access request of the basic block size set in the CPU is input from the CPU to the flash ROM, performs access with the block size of the flash ROM, and from the flash ROM An elevator control device, wherein an access response obtained is converted into an access response of the basic block size and sent to a CPU.   2. The elevator control apparatus according to claim 1, wherein the flash ROM interface circuit includes code conversion means for converting a code of an instruction input via the bus line into a code of the same instruction in the flash ROM. The CPU has a wait function for temporarily stopping its own processing operation,
3. The elevator control according to claim 1, wherein the flash ROM interface circuit includes wait function instruction means for sending a wait function execution instruction to the CPU during an access period designating a block for the flash ROM. apparatus. The CPU includes a watchdog timer that monitors a time interval between its processing operations,
2. The flash ROM interface circuit includes watchdog timer stop instructing means for instructing the CPU to stop the timing operation of the watchdog timer during an access period in which a block for the flash ROM is designated. Or the elevator control apparatus of 2.

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