JP2001357000A - Storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To connect a slave device having an interface different from that of a master device to the master device. SOLUTION: A command received from the master device 1 is converted into a command group for instructing data transfer to the slave device 4 by using a data table 8 formed in a control part 3 of a storage device 2, the command group is registered in a command table 9 and the slave device 4 is instructed to transfer data by using the command table 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an external storage device in a control system.

[0002]

2. Description of the Related Art Conventionally, when an external storage device used in a control system has been discontinued and the interface between the newly adopted storage device and the system does not match, the system interface is used. The part had to be redesigned and remodeled.

[0003]

However, in the conventional method as described above, in the case of adding a storage device to an existing system, or in the case of replacement due to a failure, two types of interfaces coexist, It was a big problem because the system had to be remodeled.

Therefore, it has been a problem to provide the same interface even when the storage device changes.

[0005]

In order to solve the above-mentioned problems, the invention according to claim 1 stores and transfers data transferred from a host device based on an instruction from a host device. In a storage device that reads data and transfers the data to a higher-level device, a controller of the storage device temporarily receives the command from the higher-level device and transmits and receives the data, and temporarily stores the data. A buffer memory, a lower device processing unit for performing data transfer according to a predetermined transfer instruction between the buffer memory and a lower device as storage means, and a central unit that decodes the command received by the upper device processing unit and provides a transfer instruction. A central processing unit, a first memory for storing a program of the central processing unit, and data as a work area when the central processing unit executes the program. And a second memory for storing the command received from the higher-level device, based on a data table stored in the first memory in advance, for the lower-level device. The command is converted into a command group for instructing the transfer, and registered as a command table on the second memory, and the command table is used to instruct the lower-level device to transfer data.

According to the present invention, a lower device having an interface different from that of the higher device can be connected to the higher device.

According to a second aspect of the present invention, in the storage device according to the first aspect, the buffer memory in the control unit of the storage device includes a first buffer memory and a second buffer memory. A data comparison processing unit configured to compare data temporarily stored in the first buffer memory and the second buffer memory, and to transfer data transferred from the upper device to a lower device. In the storing operation, the data stored in the first buffer memory for temporarily storing the data and the data stored in the lower-level device and read out and temporarily stored in the second buffer memory are stored. In the operation of comparing the obtained data by the data comparison processing unit and transferring the data stored in the lower device to the upper device, the data is stored in the lower device. The data is twice read out respectively stored in the first buffer memory and a second buffer memory, and comparing by the comparison unit the data stored in both buffer memories.

According to the present invention, the reliability of data can be improved by comparing the data stored in the two buffer memories.

According to a third aspect of the present invention, in the storage device according to the second aspect, a small computer system interface is employed as an interface of a higher-level device, and a PC-ATA card is employed as a lower-level device. Features.

According to the present invention, it is possible to obtain a flash memory storage device having a small computer system interface for a host device.

According to a fourth aspect of the present invention, in the storage device according to the second aspect, a small computer system interface is adopted as an interface of a higher-level device, and a PC-AT is used as an interface with a lower-level device.
An interface in which a parity bit is added to the A interface is adopted.

According to the present invention, it is possible to obtain a storage device having a small computer system interface to a host device and having high data reliability.

According to a fifth aspect of the present invention, in the storage device according to the second aspect, a small computer system interface is adopted as an interface of a higher-level device, and a PC-AT is used as an interface with a lower-level device.
An interface in which an error correction code is added to the A interface is adopted.

According to the present invention, it is possible to obtain a storage device having a small computer system interface for the host device and having high data reliability.

[0015]

FIG. 1 is a configuration diagram of a system showing an embodiment of the present invention.

In FIG. 1, reference numeral 7 denotes a system, and 1 denotes a higher-level device which is connected to the system 7 and controls the interface 5 with the external storage device 2.

For example, it is assumed that a magneto-optical disk is used as the external storage device 2. Storage devices, such as magneto-optical disks, are undergoing dramatic technological innovation, have a short product life cycle, and are often discontinued.

In such a case, the storage device must be switched to an alternative storage device. However, since the magneto-optical disk has a mechanically movable part and requires regular maintenance, the storage device after the switching is mechanically movable. It is assumed that a semiconductor memory device having no part is selected.

For example, a personal computer (hereinafter referred to as P
It is assumed that the card is to be switched to a flash memory card (hereinafter referred to as an ATA card) compliant with the ATA standard.

In this case, the interface of the magneto-optical disk complies with the small computer system interface (hereinafter referred to as SCSI), while the PC
-Since the interface of the ATA card complies with the PC-ATA standard, simple replacement is not possible.

To solve this problem, a control unit 3 is provided in FIG.
ATA interface 6 with C-ATA card 4 is SC
The data is converted into the SI interface 5 so that the host device 1 looks as if the storage device of the SCSI interface is connected.

FIG. 2 is a block diagram showing the internal configuration of the storage device 2 according to the embodiment of the present invention. 2, the control unit 3 of the storage device 2 is connected to the host device 1 via the SCSI bus 5, and the PC-ATA card 4, which is the lower device, is connected to the control unit via the ATA bus 6 inside the storage device 2. 3 is connected.

The control section 3 is constituted by the following devices.

A central processing unit (hereinafter abbreviated as CPU) 31 controls the storage device 2.

Reference numeral 32 denotes a SCSI processing unit (upper device processing unit)
And is connected to the CPU 31 via the CPU bus 311.
It receives a command from the host device 1 and transmits and receives data to and from the host device 1.

Reference numeral 33 denotes an ATA processing unit (lower device processing unit)
Then, a command is transmitted to the PC-ATA card 4, which is a lower-level device, and data is transmitted and received to and from the PC-ATA card 4.

Numeral 34 denotes a direct memory access (hereinafter D)
MA), between the SCSI processing unit (upper device processing unit) 32 and the buffer memory A36 or the buffer memory B37, or between the ATA processing unit (lower device processing unit) and the buffer memory A36 or the buffer memory B
DMA transfer of data is performed between the CPU 37 and the CPU 37 via a DMA bus 310 in accordance with a transfer instruction from the CPU 31.

Numeral 35 denotes a data comparison processing unit which compares the data stored in the buffer memory A36 with the data stored in the buffer memory B37.

Reference numeral 36 denotes a buffer memory A, and 37 denotes a buffer memory B.
Transfer data is temporarily stored between the cards 4.

Reference numeral 38 denotes a read-only memory (hereinafter abbreviated as ROM) as a first memory, which stores a program for the CPU 31.

Reference numeral 39 denotes a random access memory (hereinafter abbreviated as RAM) as a second memory, which is used as a work area.

In the control unit 3, a command from the host device 1 is received by the SCSI processing unit 32, and the received SCSI command is converted into a PC-ATA command by the CPU 31, and is transmitted via the ATA processing unit 33 to the PC which is a lower device. −
Sent to ATA card.

The conversion from the SCSI command to the PC-ATA command is performed by the CPU 31 using the ROM as the first memory.
38 using the data table stored in PC-ATA.
The command is converted into a command, registered as a command table in the RAM 39 serving as a second memory, and the data is transferred to and from a lower-level device using the command table.

FIG. 3 shows that the SCSI command is transmitted from the PC-ATA.
It is an example of a table used when converting to a command.

FIGS. 3 and 8 show data tables in which correspondence between SCSI commands and PC-ATA commands and data necessary for conversion are registered.

FIGS. 3 and 9 show command tables.
The PC-ATA command converted by the data table is registered including parameters. The CPU 31 sends the lower-level device PC-ATA card 4 to the PC-ATA card 4 as shown in FIG.
9 may be executed.

The interface of the SCSI bus 5 connecting the host device 1 and the SCSI processing unit 32 includes an 8-bit data line, a 1-bit parity bit, BSY,
It has control lines such as ATN, and the operation phases include bus free, selection, message out, command,
Transitions are made in seven stages: data-in or data-out, status, message-in, and bus-free.

FIG. 4 and FIG. 5 are sequence charts of the read transfer process. In accordance with FIG. 4 and FIG.
A read transfer process for reading data from the ATA card 4 will be described.

Since a plurality of storage devices 2 may be connected to the host device 1, a selection operation is required. That is, in order to connect to the desired storage device 2 in the bus free phase, the host
The ID number (for example, 2 7 bits = 1) and the storage device 2
Is placed on the SCSI bus and a selection operation is performed (step S101).

On the other hand, the SCSI processing unit 32
A response is made as BSY = 1 among the control lines of the I bus 5 (step S102).

After the selection phase is completed, the host device 1
Is set in step S101 to set the logical unit number 0 of the storage device 2 and the connection.
ATN = 1 among the control lines, and the SCSI processing unit 32
To the message-out phase.

In the message out phase, the host device 1 sends a message on the SCSI bus 5 (step S103). The sent message is SCS
The message is received by the I processing unit 32, and the message out phase ends. The SCSI processing unit 32 transitions to the next command phase.

In the command phase, the host device 1 reads out data from the PC-ATA card 4 and uses Read Extended as an operation code.
A command byte including the command is transmitted to the SCSI processing unit 32 (Step S104).

The completion of the reception of the command byte by the SCSI processing unit 32 is notified to the CPU 31 by an interrupt signal (step S105), and the CPU 31 reads the command from the SCSI processing unit 32 (step S106).

The received command byte contains the operation code, the top logical block address (hereinafter abbreviated as LBA), and the number of transfer LBAs.

The command byte received here is SCS
CPU 31 is based on the data table 8 previously created on the ROM 38, which is the first memory, so that the received head LBA and transfer LB
The number of A is converted into the number of head sectors and the number of transfer sectors of the PC-ATA card 4 as the lower-level device, and as a command group for the PC-ATA card 4, the RAM 3 as the second memory
Register on 9 This is the command table 9.

The CPU 31 sets a read sector command in the ATA processing section 33 based on the command table 9 (step S107). The ATA processing unit 33 issues a read sector command to the PC-ATA card 4,
The head sector and the number of transfer sectors are written in the command register (step S108).

Thus, the PC-ATA card 4 starts a read sector command operation.

In order to confirm that the PC-ATA card 4 is ready for data transfer, the CPU 31 performs a status confirmation operation on the ATA processing unit 33 (step S10).
9). As a result, the status register is read from the PC-ATA card 4 (step S110), and the status is confirmed.

When the PC-ATA card 4 is ready for data transfer, the CPU 31 starts data transfer.
The setting and activation of DMA are performed for the DMA processing unit 34, and the setting and activation of DMA are also performed for the ATA processing unit 33 (step S111).

The read data of the PC-ATA card 4 is
The data is DMA-transferred (read) to the buffer memory A36 via the ATA bus 6, the ATA processing unit 33, and the DMA processing unit 34 (step S112).

The end of operation after data transfer is confirmed by the CPU 3
1 performs a status check operation on the ATA processing unit 33 (step S113), and the PC-ATA card 4
From the status register (step S11).
4) The operation completion status is confirmed.

Next, from step S107 to step S1
The same operations up to 14 are executed by changing the buffer memory for writing the read sector command to the buffer memory B37.

That is, the CPU 31 sets a read sector command in the ATA processing unit 33 based on the command table 9 (step S115). ATA processing unit 33
Writes the read sector command, the leading sector, and the number of transfer sectors into the command register for the PC-ATA card 4 (step S116).

Thus, the PC-ATA card 4 starts a read sector command operation.

In order to confirm that the PC-ATA card 4 is ready for data transfer, the CPU 31 performs a status confirmation operation on the ATA processing unit 33 (step S11).
7). As a result, the status register is read from the PC-ATA card 4 (step S118), and the status is confirmed.

When the PC-ATA card 4 is ready for data transfer, the CPU 31 starts data transfer.
The setting and activation of DMA are performed for the DMA processing unit 34, and the setting and activation of DMA are also performed for the ATA processing unit 33 (step S119).

The read data of the PC-ATA card 4 is
The data is DMA-transferred (read) to the buffer memory B37 via the ATA bus 6, the ATA processing unit 33, and the DMA processing unit 34 (step S120).

The end of operation after data transfer is confirmed by the CPU 3
1 performs a status check operation on the ATA processing unit 33 (step S121), and the PC-ATA card 4
From the status register (step S12).
2), the status of the operation completion is confirmed.

The ATA bus 6 which is an interface of the PC-ATA card 4 has no parity bit. Therefore, in order to guarantee the data on the transmission of the ATA bus 6, the data read to the buffer memories A36 and B37 are compared.

When the CPU 31 instructs the data comparison processing unit 35 to set and activate a compare (step S123), the data comparison processing unit 35 sets the buffer memory A3.
6 and the buffer memory B37 at the same time to read data and compare the data (steps S126 and S127).

During this time, the CPU 31 operates the SCSI processing unit 32
Is instructed to start the data phase (step S124), the SCSI processing unit 32 transitions to the data in phase.

The CPU 31 prepares the DMA processing unit 34 and the SCSI processing unit 32 for data transfer in the data in phase.
Is set for DMA (step S125).

Completion of the compare process is determined by an interrupt signal
The PU 31 is notified (step S128) and the CPU 31
Confirms the status (step S12).
9), determine the normality and end the compare process.

When preparations for data transfer to the host device 1 are completed, the CPU 31 starts DMA transfer to start data transfer.
DMA activation is performed on the processing unit 34 and the SCSI processing unit 32 (step S130).

The read data temporarily stored in the buffer memory A 36 is transferred (read) to the higher-level device 1 via the DMA processing unit 34, the SCSI processing unit 32, and the SCSI bus 5 (step S131).

The end of operation after data transfer is confirmed by the SCSI
The processing unit 32 notifies the CPU 31 with an interrupt signal (step S132).

After the data transfer (read) is completed, the CPU 31
Starts the status and message-in to the SCSI processing unit 32 (step S133). The SCSI processing unit 32 transitions to the next status phase.

In the status phase, the host device 1 reads the status from the SCSI processing section 32 (step S134).

When the host device 1 reads the status,
The SCSI processing unit 32 makes a transition to the last message-in phase. In the message-in phase, the host device 1 reads a read command completion message from the SCSI processing unit 32 (step S135). As a result, the SCSI processing unit 32 releases the signal line of the SCSI bus 5 and enters the bus free phase.

The end of the operation of the message in phase is confirmed by the SCSI processing unit 32 notifying the CPU 31 with an interrupt signal (step S136), and the read operation ends.

Next, an operation (write operation) of writing data from the host device 1 to the PC-ATA card 4 will be described.

Similarly to the read operation, in order to connect to the storage device 2 in the bus free phase, the host device 1 connects the SCSI-ID number of the host device 1 (for example, 2 7 bits = 1) and the SCSI of the storage device 2. -Place an ID number (for example, 2 to the power of 0 bit = 1) on the SCSI bus 5 and execute a selection operation (step S201).

On the other hand, the SCSI processing unit 32
A response is made as BSY = 1 among the control lines of the I bus 5 (step S202).

After the selection phase is completed, the host device 1
Is set in step S201 to set the logical unit number 0 of the storage device 2 and the connection.
Out of the control lines, ATN = 1 and the SCSI processing unit 32
To the message-out phase.

In the message out phase, the host device 1 sends a message on the SCSI bus 5 (step S203). The transmitted message data is received by the SCSI processing unit 32, the message out phase ends, and the SCSI processing unit 32 transitions to the next command phase.

In the command phase, the host device 1
In order to write data to the C-ATA card 4, a command byte including a Write Extended command as an operation code is transmitted to the SCSI processing unit 32 (step S204).

The completion of the reception of the command byte by the SCSI processing section 32 is notified to the CPU 31 by an interrupt signal (step S).
205), the CPU 31 reads a command from the SCSI processing unit 32 (step S206).

The received command byte includes the operation code, the head LBA, and the number of transfer LBAs.

The command byte received here is SCS
CPU 31 is based on the data table 8 created in advance in the ROM 38, which is the first memory, and the received LBA and transfer LBA
The number is converted into the number of head sectors and the number of transfer sectors of the PC-ATA card 4, which is a lower-level device, and as a command group for the PC-ATA card 4, a RAM 39 serving as a second memory is converted.
Register above. This is the command table 9.

The CPU 31 erases the corresponding area in advance in order to write data to the PC-ATA card 4 based on the command table 9. That is, ATA
The erase sector command is set for the processing unit 33 (step S207).

The ATA processing section 33 is a PC-ATA card 4
Erase sector command,
The erase start sector and the number of erase sectors are written (step S208).

Thus, the PC-ATA card 4 starts an erase sector command operation.

During this time, the CPU 31 sets the SCSI processing unit 32
By instructing the SCS to start the data phase,
Next, the I processing unit 32 is shifted to the data out phase (step S209).

The CPU 31 makes DMA settings for the DMA processing unit 34 and the SCSI processing unit 32 in preparation for data transfer in the data out phase (step S210).

The end of the operation of the erase sector command is confirmed as follows. That is, when the CPU 31 performs a status confirmation operation on the ATA processing unit 33 (step S211), the status register is read from the PC-ATA card 4 (step S212), and the status of the operation completion is confirmed.

When preparation for data transfer from the host device 1 is completed, the CPU 31 starts DMA transfer to start data transfer.
DMA activation is performed on the processing unit 34 and the SCSI processing unit 32 (step S213).

The write data of the host device 1 is transferred (written) to the buffer memory A 36 via the SCSI bus 5, the SCSI processing section 32, and the DMA processing section 34 (step S214).

The end of operation after data transfer is confirmed by the SCSI
The processing is performed by the processing unit 32 notifying the CPU 31 with an interrupt signal (step S215).

The CPU 31 sets a write sector command in the ATA processing section 33 based on the command table 9 (step S216).

The ATA processing section 33 is a PC-ATA card 4
Then, the write sector command, the leading sector, and the number of transfer sectors are written in the command register (step S217).

Thus, the PC-ATA card 4 starts a write sector command operation.

The preparation for data transfer in the PC-ATA card 4 is confirmed as follows. That is, CP
The U-31 performs a status confirmation operation on the ATA processing unit 33 (step S218), and thereby the PC-ATA
The status register is read from the card 4 (step S219), and the status is confirmed.

When the preparation for data transfer is completed in the PC-ATA card 4, the CPU 311 sets and activates the DMA in the DMA processing unit 34 in order to start the data transfer, and also instructs the ATA processing unit 33 to start DMA. The DMA is set and activated (step S220).

The write data temporarily stored in the buffer memory A 36 is transferred to the DMA processing unit 34, the ATA processing unit 33,
DM to PC-ATA card 4 via ATA bus 6
A data transfer (write) is performed (step S221).

The end of operation after data transfer is confirmed as follows. That is, the CPU 31 performs a status confirmation operation on the ATA processing unit 33 (step S22).
2), the status register is read from the PC-ATA card 4 (step S223), and the status of the operation completion is confirmed.

The CPU 31 sets a read sector command in the ATA processing section 33 based on the command table 9 (step S224). The ATA processing unit 33
The read sector command, the leading sector, and the number of transfer sectors are written to the command register for the C-ATA card 4 (step S225).

Thus, the PC-ATA card 4 starts a read sector command operation.

In order to confirm that the data transfer of the PC-ATA card 4 is ready, the CPU 31 performs a status confirmation operation to the ATA processing section 33 (step S22).
6). The status register is read from the PC-ATA card, and the status is confirmed (step S22).
7).

When preparation for data transfer of the PC-ATA card 4 is completed, the CPU 31 starts data transfer.
DMA setting and activation are performed for the DMA processing unit 34, and A
DMA setting and activation are also performed for the TA processing unit 33 (step S228).

The read data of the PC-ATA card 4 is
The DMA data is transferred (read) to the buffer memory B37 via the ATA bus 6, the ATA processing unit 33, and the DMA processing unit 34 (step S229).

The end of operation after data transfer is confirmed as follows. That is, the CPU 31 performs a status check operation on the ATA processing unit 33 (step S23).
0), the status register is read from the PC-ATA card 4 (step S231), and the status of the operation completion is confirmed.

The ATA bus 6, which is an interface of the PC-ATA card 4, has no parity bit. Therefore, in order to guarantee data on the transmission of the ATA bus 6,
The data in the buffer memory A36 written from the host device 1 is compared with the data written in the PC-ATA card 4 and read out to the buffer memory B37 again.

The CPU 31 instructs the data comparison processing unit 35 to set and activate a compare (step S).
232), and the data comparison processing unit 35
6 and the buffer memory B37 at the same time to read data and compare the data (steps S233 and S234).

Completion of the compare process is determined by an interrupt signal by the CPU 3.
1 (step S235), and the CPU 31 checks the status (step S236), thereby determining the normality and terminating the compare process.

After the end of the compare process, the CPU 31
Status activation and message-in activation are performed for the I processing unit 32 (step S237). The SCSI processing unit 32 transitions to the next status phase.

In the status phase, the host device 1
Reads the status from the SCSI processing unit 32 (step S238).

When the host device 1 reads the status,
The SCSI processing unit 32 makes a transition to the last message-in phase. In the message-in phase, the host device 1 reads a read command completion message from the SCSI processing unit 32 (step S239).

The SCSI processing unit 32 releases the signal line of the SCSI bus 5 and enters the bus free phase.

The end of the operation of the message in phase is confirmed by the SCSI processing unit 32 notifying the CPU 31 with an interrupt signal (step S240), and the write operation ends.

As described above, one embodiment of the present invention has been described.

In the present embodiment, the SCSI interface is assumed as the interface with the higher-level device, and the PC-ATA interface is assumed as the interface with the lower-level device. However, the present invention is not limited to such an interface. Any combination of interfaces may be used.

In this embodiment, a standard PC-ATA card is used as a lower-level device. However, a large-capacity dedicated flash memory board may be used. In this case, the reliability can be improved by adding a parity bit to the ATA bus, and the reliability can be further improved by adding an error correction code.

[0114]

According to the present invention, even when the manufacture of an existing storage device is stopped for some reason, a storage device having a different interface is adopted as a succeeding storage device, and a command conversion or the like is performed by the control unit. This has the effect of enabling storage devices with different interfaces to be connected to existing systems.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a system according to an embodiment of the present invention.

FIG. 2 is a block diagram of a control unit.

FIG. 3 is a configuration diagram of a data table and a command table.

FIG. 4 is a sequence chart in a read transfer process.

FIG. 5 is a sequence chart in a read transfer process.

FIG. 6 is a sequence chart in a write transfer process.

FIG. 7 is a sequence chart in a write transfer process.

[Explanation of symbols]

 Reference Signs List 1 upper device 2 storage device 3 controller 4 lower device (PC-ATA card) 5 SCSI bus 6 ATA bus 7 system 31 CPU 32 SCSI processing unit 33 ATA processing unit 34 DMA processing unit 35 data comparison processing unit 36 buffer memory A 37 Buffer memory B 38 ROM 39 RAM

Claims (5)

[Claims] 1. A storage device for storing data transferred from a higher-level device based on a command from a higher-level device, reading the stored data, and transferring the read data to a higher-level device.
A control unit of the storage device, a high-order device processing unit that receives an instruction from the high-order device and transmits and receives the data, a buffer memory that temporarily stores the data, and a low-order buffer as the buffer memory and the storage unit. A lower-level device processing unit that performs data transfer between devices according to a predetermined transfer instruction, a central processing unit that decodes the command received by the higher-level device processing unit and provides a transfer instruction, and stores a program for the central processing device. A first memory, and a second memory for storing data as a work area when the central processing unit executes the program, wherein the central processing unit stores the instruction received from the higher-level device in advance. Based on the data table stored in the first memory, the data is converted into a command group for instructing the lower-level device to transfer data, and Register as command table on the second memory, storage device, characterized by a transfer instruction of data to the lower device by the command table. 2. The buffer memory in the control unit of the storage device, comprising: a first buffer memory and a second buffer memory;
A data comparison processing unit for comparing data temporarily stored in the buffer memory and the second buffer memory, and in the operation of storing the data transferred from the upper device in the lower device, the data is temporarily stored in the lower device. The data stored in the first buffer memory and the data stored in the lower-level device and read out and temporarily stored in the second buffer memory are stored in the data comparison processing unit. In the operation of comparing and transferring the data stored in the lower device to the higher device, the data stored in the lower device is read twice and stored in the first buffer memory and the second buffer memory, respectively. 2. The storage device according to claim 1, wherein the data stored in both buffer memories are compared by the data comparison processing unit. 3. The storage device according to claim 2, wherein a small computer system interface is used as an interface of the host device, and a PC-ATA card is used as a host device. 4. The apparatus according to claim 2, wherein a small computer system interface is adopted as an interface of the host device, and an interface obtained by adding a parity bit to a PC-ATA interface is adopted as an interface with the host device. Storage device. 5. The small computer system interface as an interface of a higher-level device, and an interface obtained by adding an error correction code to a PC-ATA interface as an interface with a lower-level device. Storage device.