JP2008022330A - Information reproducing apparatus and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information reproducing apparatus and electronic equipment, wherein low power consumption is attained by continuing decode processing or the like without wasting correct data. <P>SOLUTION: The information reproducing apparatus 10 includes: a first buffer 20 for storing input packets; an error detection section 30 for attaching error information obtained as a result of detecting an error of the input packet to the input packet and storing the error information to the first buffer 20 together with the input packet; an error analysis section 40 for detecting the error of the packet on the basis of the error information; a reproduction data generating section 50 for generating reproduction data on the basis of the packet stored in the first buffer 20; a second buffer 22 for storing the reproduction data; and a decoder 60 for decoding the reproduction data stored in the second buffer 22. When the error analysis section 40 detects an error, the second buffer 22 stores dummy data in place of the reproduction data. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an information reproducing apparatus and an electronic device.

  In terrestrial digital broadcasting that appears in place of analog terrestrial broadcasting, there are expectations for the provision of various new services in addition to improving the quality of images and audio. One of the services newly provided by the introduction of terrestrial digital broadcasting is so-called “one-segment broadcasting” as a service for mobile terminals. In “1-segment broadcasting”, digital modulated waves modulated by the QPSK (Quadrature Phase Shift Keying) modulation method are multiplexed by the OFDM (Orthogonal Frequency Division Multiplexing) modulation method, so that stable broadcast reception is possible even when the mobile terminal is moving. Is possible.

  An example of such a mobile terminal is a mobile phone. When a reception function of “1-segment broadcasting” is added to a cellular phone, a separation process of a transport stream in which video data and audio data after compression processing are multiplexed and data decoding processing after the separation processing are performed. At this time, communication is performed between the processing unit that performs the decoding process of the video data and the processing unit that performs the decoding process of the audio data, and the video data and audio data after the decoding process are reproduced in synchronization.

  As a technique for reproducing this digital broadcast, for example, in Patent Document 1, an error correction unit is provided in front of a transport stream DMUX that separates packets from a transport stream in order to notify the user that reception is impossible. Discloses a technique for obtaining a change in the reception level from the frequency of errors detected in the section. This makes it easier to recognize that the reception level has deteriorated due to rain or the like.

Further, in Patent Document 2, log information is added to the beginning and end positions of a packet by a log generation circuit, and a CPU (Central Processing Unit) reads out the log information before and after each packet when processing the packet. A system that can acquire status information is disclosed.
JP 2000-115654 A JP 2000-156705 A

  By the way, data to be decoded is received as a transport stream in which TS (Transport Stream) packets are continuous and assembled into PES (Packet Elementary Stream) packets, and then ES (Elementary Stream) data from the PES packets. Is taken out and used for synchronous reproduction processing. Therefore, if the ES data is separated from the TS packet, there is no relationship between them, and if an error is detected in the TS packet, it is difficult to identify the location where the error occurred in the ES data to be decoded, On the rear stage side, the decoding process must be stopped immediately. In this case, the decoding process may be stopped despite the correct data. Furthermore, if only the presence or absence of error detection is notified to the decoder side, the decoding process may be stopped despite the possibility of correct decoding.

  Also, once the decoding process is interrupted, the writing process and reading process at the time of restarting become complicated, and the management of the memory for buffering TS packets and ES data becomes complicated.

  In particular, in “terrestrial digital broadcasting” such as “1-segment broadcasting”, a broadcast signal is transmitted as a radio wave signal, so that a normal reception signal is not always obtained. Therefore, it is easily affected by external factors, and if the decoding process is interrupted whenever an error occurs, memory management becomes complicated and power consumption increases.

  Note that the above problem is not only when an error occurs, but also when starting a series of decoding processes again when searching for the first picture of an image sequence.

  The present invention has been made in view of the technical problems as described above, and an object of the present invention is to reproduce information for reducing power consumption by continuing decoding processing without wasting correct data. It is to provide an apparatus and an electronic device.

In order to solve the above problems, the present invention
A first buffer in which input packets are stored;
An error detection unit for adding error information obtained as a result of detecting an error in the input packet to the input packet and storing the error information together with the input packet in the first buffer;
Based on the error information, an error analysis unit that detects an error of the packet;
A reproduction data generation unit for generating reproduction data based on the packet stored in the first buffer;
A second buffer in which the reproduction data is stored;
A decoder for decoding the reproduction data stored in the second buffer,
The present invention relates to an information reproducing apparatus that stores dummy data in the second buffer instead of the reproducing data when an error is detected by the error analyzing unit.

  In the present invention, when an error in the input packet is detected and the content of the error is analyzed, and it is determined that an error has occurred in the input packet, it is replaced with the reproduction data that should be buffered originally. Dummy data is stored in the second buffer. When the decoder performs a decoding process on the data read from the second buffer, it is determined that the decoder is dummy data, so that even if an error occurs in the input packet, the decoder There is no need to interrupt the decoding process. As a result, the management of the memory for buffering the reproduction data can be simplified. When the input packet is extracted from the radio signal, it is expected that the frequency of error in the input packet will increase. Therefore, it is not necessary to interrupt the decoding process frequently every time an error occurs. In addition, an increase in power consumption due to unnecessary decoding processing or the like can be suppressed.

In the information reproducing apparatus according to the present invention,
A dummy data control unit for storing the dummy data in the second buffer;
The dummy data control unit
Dummy data having a size corresponding to the free capacity of the second buffer can be stored in the second buffer.

In the information reproducing apparatus according to the present invention,
When a dummy code is inserted or added to the normal code string to be distinguished from a given prohibited code and stored in the second buffer,
The dummy data is
The normal code string may be the same data as the code string immediately before the dummy code is inserted.

  According to any one of the above inventions, for example, the start code emulation process can be used in the decoder without adding a new decoding process. Even if an error is detected in the input packet, it is not necessary to interrupt the decoding process unnecessarily.

In the information reproducing apparatus according to the present invention,
The dummy data control unit
When an error is detected by the error analysis unit, dummy data having a data size greater than or equal to the maximum read data size of the second buffer can be written to the second buffer one or more times.

  According to the present invention, it is ensured that the read position does not overtake the write position in the second buffer when the decoder reads data from the second buffer. As a result, access control to the second buffer can be simplified.

In the information reproducing apparatus according to the present invention,
The error analysis unit
Determining whether a first or second error has occurred based on error information added to the packet stored in the first buffer;
If it is determined that the first error has occurred, dummy data can be stored in the second buffer instead of the reproduction data.

  According to the present invention, since dummy data is stored according to the type of error, it is possible to avoid a situation where the decoding process is interrupted even though there is a possibility that decoding can be performed correctly. .

In the information reproducing apparatus according to the present invention,
A first TS (Transport Stream) packet for generating video reproduction data, a second TS packet for generating audio reproduction data, and a third TS other than the first and second TS packets Including a separation processing unit for extracting TS packets from the transport stream;
The first buffer comprises:
A first storage area for storing the first TS packet; a second storage area for storing the second TS packet; and a third storage area for storing the third TS packet; Have
The second buffer comprises:
A fourth storage area in which the video reproduction data is stored; and a fifth storage area in which the audio reproduction data is stored;
The decoder
A video decoder that performs video decoding processing for generating video playback data based on the first TS packet read from the first storage area, and stores the playback data in the fourth storage area When,
An audio decoder that performs audio decoding processing for generating audio reproduction data based on the second TS packet read from the second storage area, and stores the reproduction data in the fifth storage area Including
Playback data can be output from at least one of the fourth and fifth storage areas.

In the information reproducing apparatus according to the present invention,
The video decoder reads the first TS packet from the first storage area independently of the audio decoder, performs the video decoding process based on the first TS packet,
The audio decoder can read the second TS packet from the second storage area independently of the video decoder, and perform the audio decoding process based on the second TS packet.

  According to any one of the above inventions, it is possible to provide an information reproducing apparatus capable of reproducing video and audio data from a TS using a decoder having a small capacity and a small processing capacity. .

In the information reproducing apparatus according to the present invention,
When reproducing only the video data of the video data and audio data, stop the operation of the audio decoder,
When only the audio data is reproduced from the video data and audio data, the operation of the decoding device can be stopped.

  According to the present invention, further reduction in power consumption of the information reproducing apparatus can be realized.

The present invention also provides
The present invention relates to an electronic device including any one of the information reproducing apparatuses described above.

The present invention also provides
Any one of the information reproducing devices described above;
The present invention relates to an electronic apparatus including a host that instructs the information reproduction apparatus to start at least one of the video decoding process and the audio decoding process.

The present invention also provides
Tuner,
Any one of the above information reproducing apparatuses to which a transport stream from the tuner is supplied;
The present invention relates to an electronic device including a host that instructs the information reproduction apparatus to start at least one of the video decoding process and the audio decoding process.

  According to any one of the above-described inventions, it is possible to provide an electronic apparatus including an information reproducing apparatus that continuously reduces decoding without wasting correct data and achieves low power consumption.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Information Reproducing Device FIG. 1 is a block diagram showing a configuration example of the information reproducing device according to this embodiment. The information reproducing apparatus is not limited to the configuration shown in FIG. 1, and various modifications such as omitting some of the components or adding other components are possible.

  The information reproducing apparatus 10 receives a transport stream (hereinafter referred to as TS) from a digital tuner (not shown). This TS is stream data in which TS packets (packet data in a broad sense) are multiplexed, and is defined by, for example, the MPEG-2 system (ISO / IEC 13818-1). Then, the information reproducing apparatus 10 performs a decoding process on this TS. More specifically, the information reproducing apparatus 10 performs a decoding process on the TS packet extracted from the TS. The information reproducing apparatus 10 is connected to an output unit (for example, a display unit or a speaker). Then, the decoded data is transferred to, for example, a display unit (output unit in a broad sense) and displayed as an image, or output to a speaker (output unit in a broad sense) and output as sound.

  For example, data to be decoded is received as a transport stream in which TS packets are continuous, assembled into PES (Packet Elementary Stream) packets, and then ES (Elementary Stream) data is extracted from the PES packets. It is used for synchronized playback processing. Therefore, if the ES data is separated from the TS packet, there is no relationship between them, and if an error is detected in the TS packet, it is difficult to identify the location where the error occurred in the ES data to be decoded, On the latter stage side, the decoding process must be stopped immediately, and the decoding process may be stopped even though the data is correct. Furthermore, once the decoding process is interrupted, the management of the memory for buffering TS packets and ES data becomes complicated.

  Therefore, when the information reproducing apparatus 10 generates ES data as reproduction data from the input TS packet, buffers the ES data, and outputs the ES data to the decoder, the information reproducing apparatus 10 detects the TS packet error and details the error. In accordance with the analysis result, dummy data is buffered instead of ES data that will be buffered if no error is detected. Therefore, when an error is detected in the TS packet, dummy data is supplied to the decoder. At this time, if the decoder that performs the decoding process on the dummy data can determine that the dummy data is invalid, the data is not reproduced with incorrect data. Therefore, even if an error is detected in the TS packet, there is no need to interrupt the decoding process unnecessarily. As a result, management of the memory for buffering ES data can be simplified.

  For example, when a radio signal is transmitted as in “one segment broadcasting”, a normal reception signal is not always obtained. Therefore, according to this embodiment, it is not necessary to interrupt the decoding process every time an error occurs, and an increase in power consumption can be suppressed.

  In this embodiment, the information reproducing apparatus 10 includes the first and second buffers 20 and 22, the error detecting unit 30, the error analyzing unit 40, the reproducing data generating unit 50, and the decoder 60. Can be included. The first buffer 20 stores input TS packets. This TS packet is a packet separated from the TS. The error detection unit 30 adds error information obtained as a result of detecting an error in the input TS packet to the TS packet, and stores the error information together with the TS packet in the first buffer 20. The error analysis unit 40 detects an error in the TS packet based on the error information added by the error detection unit 30. The reproduction data generation unit 50 generates ES data as reproduction data based on the TS packet stored in the first buffer 20. This ES data is stored in the second buffer 22. The decoder 60 performs a decoding process on the ES data stored in the second buffer 22. Then, when an error is detected by the error analysis unit 40, the information reproducing apparatus 10 stores dummy data in the second buffer 22 instead of ES data as reproduction data.

  Further, the information reproducing apparatus 10 can further include a dummy data control unit 70. The dummy data control unit 70 generates dummy data and stores the dummy data in the second buffer 22. More specifically, the dummy data control unit 70 stores dummy data having a size corresponding to the free capacity of the second buffer 22 in the second buffer 22.

  One of a plurality of storage areas provided in the memory 80 is allocated to each of the first and second buffers 20 and 22, and each of the first and second buffers 20 and 22 is allocated to the allocated storage area. The buffer function may be realized.

1.1 Dummy Data The decoder 60 determines that the dummy data is invalid data and prevents the output unit from reproducing erroneous data. Therefore, it is desirable that the decoder 60 performs a start code detection process and uses a code used in the emulation countermeasure process performed to distinguish the start code from a normal code. That is, it is desirable that the dummy data of this embodiment is a part of the start code monitored in the emulation countermeasure process.

  FIG. 2 is an explanatory diagram of emulation performed on the start code in the present embodiment.

  The start code is a synchronization code of stream data that is a bit stream. In the stream data, various control codes are embedded in addition to normal content codes. Therefore, in order to distinguish the content code contained in the stream data from the start code, emulation processing is performed on the content code which is a normal code, and the code after emulation processing is set in the stream data and transmitted. It is like that.

  For example, it is assumed that “000001” is defined as the start code. When the stream data is “000001”, it cannot be determined whether the code is the content code “000001” or the start code. Therefore, a dummy code is added or inserted to the content code on the stream data generation side, and the start code and the content code are easily distinguished on the stream data reception side.

  In the above case, when the start code is set in the stream data on the stream data generation side, “03” is inserted into the start code to be “000001001”. Accordingly, the stream data receiving side must recognize that the start code is “000001” when “000001001” is detected. Processing for performing such recognition is performed in the decoder 60.

  FIG. 3 shows a flowchart of an operation example of the start code emulation process of FIG.

  The decoder 60 includes a CPU (not shown), reads a program stored in a memory (not shown), and executes a process corresponding to the program so that the process shown in FIG. 3 can be performed.

  The decoder 60 detects the presence / absence of read data from the second buffer 22 (step S10). When read data is detected in step S10 (step S10: Y), the read data from the second buffer 22 is stored in the built-in buffer (step S11). Then, the decoder 60 issues an instruction to update the read pointer RP of the internal buffer (step S12), and performs a start code detection process (step S13).

  The decoder 60 detects whether or not “000003” is included in the read data (step S14). When it is detected that “000003” is included in the read data (step S14: Y), “03” is deleted from the read data (step S15), and a detection flag that is initialized when the decoder 60 starts processing Is set (step S16). Then, the decoder 60 instructs to update the read pointer RP of the built-in buffer (step S17), and monitors the next read data (return).

  If no read data is detected in step S10 (step S10: N), or if it is detected in step S14 that “000003” is not included in the read data (step S14: N), the process returns to step S10 (return). ).

  As described above, the decoder 60 inserts or adds “03” (given dummy code) into the normal code string and stores it in the second buffer 22 in order to distinguish it from the start code (given prohibited code). In this case, it is possible to perform processing for detecting the presence or absence of “03” in the data read from the second buffer 22.

  FIG. 4 is an explanatory diagram showing an example of the operation result of the start code emulation process of FIG.

  As described above, when the detection flag is set to “1” and the data stored in the built-in buffer of the decoder 60 is “000001”, it can be determined as a normal code. On the other hand, when the detection flag is not set and the data stored in the built-in buffer of the decoder 60 is “000001” in the state of “0”, it can be determined as a start code.

  As described above, even when a start code for controlling stream data is included, it is not necessary to buffer stream data during processing by performing emulation processing. The dummy data is preferably the same data as the code string (“0000” in FIG. 2) immediately before the dummy code (“03” in FIG. 2) is inserted in the normal code string. By doing so, the decoder 60 can handle the dummy data in the same way as “0000” during the start code emulation process during the previous decoding process without adding a new decoding process. Therefore, even if an error is detected in the TS packet, there is no need to interrupt the decoding process unnecessarily.

  Next, dummy data writing processing in the present embodiment will be described.

  FIG. 5 is an explanatory diagram of the second buffer.

  The information reproducing apparatus 10 monitors various pointers in a control unit (not shown) in order to manage access processing to the second buffer 22. That is, the control unit manages the read pointer RP, the write pointer WP, and the dummy data write pointer WPd of the second buffer 22. More specifically, the read pointer RP is updated when the reading process is performed by the control unit, and the write pointers WP and WPd are updated when the writing process is performed. The read pointer RP is a pointer for specifying a storage area for read data from the second buffer 22. The write pointer WP is a pointer for specifying a storage area in which data is written in the second buffer 22. The dummy data write pointer WPd is a pointer for specifying a storage area in which dummy data is written in the second buffer 22. The dummy data write pointer WPd may be managed in common as the write pointer WP.

  FIG. 6 shows a flowchart of an example of the dummy data writing process of the information reproducing apparatus 10.

  The information reproducing apparatus 10 includes a CPU (not shown), and can perform the processing shown in FIG. 6 by reading a program stored in a memory (not shown) and executing processing corresponding to the program.

  When the reproduction data generation unit 50 of the information reproduction apparatus 10 detects that an error has occurred in the TS packet based on the error information added to the TS packet read from the first buffer 20, The dummy data control unit 70 is instructed to write dummy data to the second buffer 22.

  The dummy data control unit 70 of the information reproducing apparatus 10 first writes the above-described dummy data in units of 184 bytes based on an instruction from the reproduction data generating unit 50 (step S20). That is, writing is performed in units of the maximum size of the payload of the TS packet.

  Then, the dummy data control unit 70 determines whether or not a prescribed amount of dummy data has been written (step S21). This prescribed amount is a size corresponding to the free capacity of the second buffer 22. When it is determined that the prescribed amount of dummy data has not been written (step S21: N), the dummy data control unit 70 determines whether or not the second buffer 22 is full (step S22).

  When it is determined in step S22 that the second buffer 22 is not full (step S22: N), the process returns to step S20. When it is determined in step S22 that the second buffer 22 is full (step S22: Y), the decoder 60 of the information reproducing apparatus 10 decodes the ES data read from the second buffer 22. Processing is performed (step S23), and the process returns to step S22.

  On the other hand, when it is determined in step S21 that a prescribed amount of dummy data has been written (step S21: Y), the dummy data control unit 70 stops writing dummy data (step S24). Then, the decoder 60 performs a decoding process on the ES data read from the second buffer 22 (step S25).

  After the decoding process, the information reproducing apparatus 10 determines whether or not the read pointer RP of the second buffer 22 has reached the dummy data position designated by the dummy data write pointer WPd (step S26). When the read pointer RP has not reached the dummy data position (step S26: N), the process returns to step S25 and the decoding process is continued.

  When it is determined in step S26 that the read pointer RP has reached the dummy data position (step S26: Y), the series of dummy data writing processing is ended (END).

  When it is determined that the read pointer RP has reached the dummy data position (step S26: Y), for example, the decoder 60 can search for an IDR (Instantaneous Decoding Refresh) picture that searches for the first picture of the image sequence. . In this case, the decoding process for generating image data for one screen while referring to the preceding and subsequent image data is refreshed.

  FIG. 7 shows a flowchart of a processing example for determining the write data size of dummy data.

  The size corresponding to the specified amount in step S21 of FIG. 6 can be determined by the process of FIG. 7 by the dummy data control unit 70.

  First, prior to the processing of FIG. 6, the dummy data control unit 70 acquires the start address and end address of the empty area of the second buffer 22 (step S30). Then, the dummy data control unit 70 obtains the free capacity size SZ of the second buffer 22 based on the start address and end address acquired in step S30 (step S31).

  Subsequently, the free space size SZ is divided by 32 to obtain the number of bytes BT (step S32), and the count number CNT corresponding to a predetermined amount is obtained. More specifically, it is determined whether or not BT × (CNT-1) is greater than a specified amount (step S33), and when it is determined that BT × (CNT-1) is equal to or less than the specified amount (step S33). : N), the count number CNT is incremented (step S34), and the process returns to step S33.

  When it is determined in step S33 that BT × (CNT-1) is larger than the prescribed amount (step S33: Y), processing for obtaining the number N of dummy data writes for the unit amount is performed. More specifically, it is determined whether or not 184 × CNT is equal to or less than N × BT (step S35). When it is determined that 184 × CNT is larger than N × BT (step S35: N), N is incremented (step S36), and the process returns to step S35.

  When it is determined in step S35 that 184 × CNT is equal to or less than N × BT (step S35: Y), N at this time is determined as the number of times of writing dummy data of a unit amount (step S37). End processing (END).

  Therefore, in step S21 of FIG. 6, it is possible to determine whether or not dummy data having a prescribed amount has been written based on whether or not 184-byte dummy data is written N times.

  As described above, in this embodiment, dummy data having a size corresponding to the free capacity of the second buffer 22 can be stored in the second buffer 22.

  It should be noted that the specified amount in step S21 in FIG. 6 and step S33 in FIG. 7 is desirably a data size that is equal to or larger than the maximum read data size of the second buffer 22. That is, when an error is detected by the error analysis unit 40, the dummy data control unit 70 sets dummy data having a data size equal to or larger than the maximum read data size of the second buffer 22 one or more times. It is desirable to write on. This ensures that the read pointer RP does not pass the write pointer WP (or the dummy data write pointer WPd) in the second buffer 22 when the decoder 60 reads data from the second buffer 22. The As a result, access control to the second buffer 22 can be simplified.

  Further, once the dummy data is written in the second buffer 22, it is desirable that the dummy data control unit 70 does not write the dummy data again in the second buffer 22 until the IDR picture is searched. By doing so, the pointer management of the second buffer 22 can be further simplified.

1.2 Error Detection In this embodiment, the error analysis unit 40 determines whether or not a first or second error has occurred based on error information added to the TS packet stored in the first buffer 20. The dummy data controller 70 replaces the ES data as the reproduction data with the second buffer 22 on condition that the dummy data control unit 70 determines that the first error has occurred by the error analysis unit 40. It is desirable to store in.

  Hereinafter, error detection in this embodiment will be described. In this embodiment, after the reproduction data generation unit 50 reassembles the TS packet into a PES (Packet Elementary Stream) packet, ES data is generated from the PES packet. In this case, if the ES data is separated from the TS packet, there is no relationship between them, and if an error is detected in the TS packet, it is difficult to specify the location of the error in the ES data. Then, the decoding process must be stopped immediately. Therefore, the decoding process may be stopped despite the correct data.

  For this reason, in this embodiment, error detection and error analysis are performed, and “no error”, “minor error occurrence”, or “fatal error occurrence” is determined according to the type of error analyzed. Then, the decoding process corresponding to the determined classification is performed. Thus, when an error is detected, the decoding process for the correct data can be continued without immediately stopping the decoding process on the subsequent stage side.

  Therefore, the error analysis unit 40 of the information reproducing apparatus 10 in FIG. 1 determines whether the first or second error has occurred based on the error information of the TS packet stored in the first buffer 20. . Here, the first error can be a fatal error, and the second error can be a minor error.

  Then, the dummy data control unit 70 replaces the ES data generated based on the TS packet in accordance with the first or second error determined by the error analysis unit 40 with the second buffer. 22. Further, the decoder 60 can perform decoding processing on the TS packet according to the first or second error determined by the error analysis unit 40. For example, the decoder 60 stops the decoding process when the occurrence of the first error is detected, searches for an IDR (Instantaneous Decoding Refresh) picture, and when the occurrence of the second error is detected, Processing for skipping the slice is performed, and decoding processing is performed on the data of the next slice. Here, a slice is a basic unit of encoding. For example, an I slice, a P slice, and a B slice can be mixed in a picture.

  For this reason, the error detection unit 30 detects an error in a fixed-length TS packet (packet data in a broad sense), adds error information indicating the presence or absence of an error in the TS packet to the TS packet, and adds the error information. The packet is stored in the first buffer 20. That is, not only TS packets from a digital tuner (not shown) are buffered in the first buffer 20, but TS packets and error information of the TS packets are buffered.

  Then, the reproduction data generation unit 50 reads the error information and the TS packet from the first buffer 20, and generates ES data unless a fatal error has occurred in the TS packet. When a fatal error has occurred in the TS packet when generating ES data from the TS packet, the dummy data control unit 70 stores dummy data in the second buffer 22 instead of the ES data. Based on the error information, the decoder 60 performs IDR picture search processing when a fatal error has occurred. At this time, since it is already embedded with dummy data, complicated management of the memory 80 can be eliminated. In addition, when a minor error has occurred, the decoder 60 performs processing for skipping the slice.

  The error detection unit 30 can have a function as a packet separation processing unit. In this case, the error detection unit 30 can separate a plurality of types of TS packets from the TS, and store the separated TS packets in a storage area previously assigned to each type of TS packet in the first buffer 20. . The first buffer 20 displays TS packets for setting PMT (Program Map Table) as program information, TS packets for setting NIT (Network Information Table) as network information, and character / caption information. TS packets for displaying BML (Broadcast Markup Language), TS packets for setting PSI / SI (Program Specific Information / Service Information), video TS packets for displaying images, Audio TS packets for outputting audio are stored in each storage area.

  A host (not shown) provided outside the information reproducing apparatus 10 analyzes PMT, NIT, character / caption information, BML, and PSI / SI based on the TS packet read from the first buffer 20. For example, the host analyzes the PMT, analyzes the packet identifier (PID) of the video TS packet and the audio TS packet, and the host notifies the error detection unit 30 of the PID. In response to this, the packet separation means (not shown) of the error detection unit 30 refers to the PID set by the host and performs the process of separating each TS packet as described above from the TS from the digital tuner. At this time, the host can perform predetermined error processing by referring to the error information added to the TS packet stored in each storage area of the first buffer 20.

  That is, the reproduction data generation unit 50 reads at least one of the video TS packet and the audio TS packet stored in the first buffer 20, analyzes the TS header, and outputs a PES (Packet Elementary Stream) packet. It is possible to generate and analyze the PES header of the PES packet to generate ES (Elementary Stream) data after deleting the PES header. This ES data is written into the second buffer 22 and decoded by the decoder 60.

  FIG. 8 is an explanatory diagram of error information added to the TS packet in the present embodiment.

  As described above, the error detection unit 30 that can function as a packet separation processing unit can separate a TS packet from a TS when a TS from a digital tuner (not shown) is input. The separated TS packet is a fixed-length packet having a length of 188 bytes. The error detection unit 30 performs a predetermined type of error detection process on the TS packet, and generates the detection process result as error information having a 4-byte length. The error detection unit 30 performs processing for storing, in the first buffer 20, packet data having a length of 192 bytes, in which 4-byte error information is added to an 188-byte TS packet to be subjected to error detection processing.

  FIG. 9 shows a detailed explanatory diagram of the error information of FIG.

  In the error information in the present embodiment, an error status indicating the presence / absence of an error is set as an error detection processing result in a predetermined bit of 4 bytes (= 32 bits). In FIG. 9, the error status is set in the 29th to 24th bits and the 19th to 16th bits.

  FIG. 10 illustrates an example of the content of the error status in FIG.

  In the 16th bit of the error information, an error status indicating whether or not there is a PMT table_id error is set. More specifically, in the 16th bit, when the TS packet is a PMT packet, when the table_id specified by the data structure of the PMT packet is not 0x02 ("0x" indicates a hexadecimal number), a table_id error is displayed. It is determined that it has occurred and “1” is set.

  In the 17th bit of the error information, an error status indicating the presence / absence of a PMT section_syntax_indicator error is set. More specifically, in the 17th bit, when the TS packet is a PMT packet, if the section_syntax_indicator specified by the data structure of the PMT packet is not 0x01, it is determined that a section_syntax_indicator error has occurred and “1” is set. Is set.

  In the 18th bit of the error information, an error status indicating the presence / absence of a PMT current_next_indicator error is set. More specifically, in the 18th bit, when the TS packet is a PMT packet, if the current_next_indicator specified by the data structure of the PMT packet is not 0x01, it is determined that a current_next_indicator error has occurred and “1” is set. Is set.

  In the 19th bit of the error information, an error status indicating the presence / absence of a PMT section_number error is set. More specifically, in the 19th bit, when the TS packet is a PMT packet, if the section_number specified by the data structure of the PMT packet is not 0x00, it is determined that a section_number error has occurred and “1” is set. Is set.

  An error status indicating the presence or absence of a tuner error is set in the 24th bit of the error information. More specifically, in the 24th bit, it is determined that a tuner error has occurred when an RS (Read Solomon) code error from the digital tuner is set, and “1” is set. An RS code error occurs, for example, when error correction using an RS code is impossible.

  In the 25th bit of the error information, an error status indicating the presence / absence of a synchronization byte mismatch error is set. More specifically, in the 25th bit, when the synchronization byte of the TS packet is different from the predetermined synchronization byte, it is determined that a synchronization byte mismatch error has occurred and “1” is set.

  In the 26th bit of the error information, an error status indicating whether there is a cyclic redundancy check (CRC) error is set. More specifically, in the 26th bit, when a CRC error is detected when the TS packet is a PMT packet, it is determined that a CRC error has occurred and “1” is set.

  In the 27th bit of the error information, an error status indicating whether or not the TS packet size is insufficient is set. More specifically, in the 27th bit, when the TS packet size is less than 188 bytes, it is determined that the TS packet size is insufficient, and “1” is set.

  In the 28th bit of the error information, an error status indicating whether TS packet size is over is set. More specifically, in the 28th bit, when the size of the TS packet is 189 bytes or more, it is determined that the TS packet size is over and “1” is set.

  In the 29th bit of the error information, another write request occurred in the first buffer 20 (or the second buffer 22) during the write request to the first buffer 20 (or the second buffer 22). An error status indicating whether or not is set. For example, the error detection unit 30 adds error information indicating that another write request to the first buffer 20 has occurred during the write request for writing the packet data to the first buffer 20 to the packet data. It can be said. While the error detection unit 30 is writing the TS packet and the error information to the first buffer 20, for example, another block has made a write request to the first buffer 20 or the second buffer 22. Sometimes “1” is set. This indicates that when processing TSs that arrive one after another, the processing of each unit cannot catch up, and it cannot be guaranteed that the write data to the first buffer 20 that has received two write requests is complete. The error status is set to “1” in order to leave the determination of whether or not to continue the decoding process of the TS packet to the subsequent stage.

  For example, when at least one of the 16th bit, the 17th bit, the 18th bit, and the 19th bit is “1”, it is desirable to discard the TS packet to which the error information including the error status is added. This is because the TS packet to be separated by the error detection unit 30 is determined by the host that analyzes the PMT, so it is not necessary to analyze the PMT even when the content of the PMT is incomplete, and the TS packet is discarded. This is because waiting for the next incoming PMT is more likely to be reproduced with a normal TS packet, and control can be simplified.

  Note that it is not necessary to detect all the error statuses shown in FIG. 10, and at least one error is detected from table_id, section_syntax_indicator, current_next_indicator, and section_number in the data structure of the PMT, and error information indicating the presence / absence of the error is included in the packet data. May be added.

  Incidentally, the error information generated in the error detection unit 30 is preferably stored in the storage area of the first buffer 20 so as to be read prior to packet data to which the error information is added.

  FIG. 11 shows an explanatory diagram of the storage status of error information and TS packets in the first buffer 20 in the present embodiment.

  An address value is assigned to the first buffer 20, and each storage area in which the TS packet is stored is specified by the address value. Here, for example, it is assumed that the reproduction data generation unit 50 reads TS packets and error information in order from a storage area having a small address value to a storage area having a large address value.

  At this time, it is desirable to store the error information in the present embodiment in the storage area of address 0 having a small address value, and store the TS packet to which the error information is added in the storage areas of addresses 1 to 47 having a large address value. Thus, for each TS packet, by storing error information in the storage area of the address value rather than the storage area of the TS packet, for example, the reproduction data generation unit 50 or the host first reads out the error information and detects the error. What is necessary is just to distinguish. For example, when it is determined to discard a TS packet, the process of reading error information of the next TS packet may be performed without reading a TS packet stored in a storage area having a large address value thereafter.

  FIG. 12 shows an example of timing for adding error information in the present embodiment.

  A 204 byte transmission TSP (Transport Stream Packet) is input to the information reproducing apparatus 10 from the digital tuner. The transmission TSP is stream data in which a TS packet having a length of 188 bytes and a parity bit of an RS code having a length of 16 bytes are multiplexed.

  For example, when a transmission TSP is input to the information reproducing apparatus 10 at time TG1, the error detection unit 30 starts an error detection process. Further, the error detection unit 30 starts a process of separating the TS packet corresponding to the PID set by the host, and performs a process of storing the separated TS packet in the first buffer 20 after time TG2.

  Then, when the next transmission TS is input at time TG10, the error information which is the error detection processing result started at time TG1 is read so that the reading order comes before the TS packet as shown in FIG. 1 buffer 20. In other words, prior to writing the packet data obtained as a result of the separation processing started at time TG10 into the first buffer 20, the error information added to the previous packet data is written into the first buffer 20. In this way, it is possible to easily detect the TS packet size shortage shown in FIG. 10 and to continue the process of adding error information to successive transmission TSPs without any processing delay.

  Thereafter, the TS packet and error information are similarly stored. At this time, in the first buffer 20, a TS packet for setting the PMT, a TS packet for setting the NIT, a TS packet for displaying character / caption information, a TS packet for displaying BML, TS packets for setting PSI / SI, video TS packets, and audio TS packets are stored in each storage area.

  Next, a processing example of the error analysis unit 40 that determines the first or second error corresponding to a fatal error or a minor error based on the error information detected as described above will be described.

  FIG. 13 shows a flowchart of a processing example of the error analysis unit 40.

  The error analysis unit 40 includes a CPU (not shown), reads a program stored in a memory (not shown), and executes a process corresponding to the program to perform the process shown in FIG.

  First, the error analysis unit 40 acquires the error status shown in FIG. 9 from the error information stored in the first buffer 20 (step S40). Then, the error analysis unit 40 analyzes the acquired error status.

  That is, based on the 27th bit data of the error status acquired in step S40, it is determined whether or not the TS packet size is insufficient (step S41). When it is determined in step S41 that the TS packet size is insufficient (step S41: Y), the error analysis unit 40 generates error occurrence information indicating that a fatal error has occurred in the TS packet (step S42). ).

  When it is determined in step S41 that the TS packet size is not insufficient (step S41: N), the error analysis unit 40 determines whether the TS packet size is over based on the 28th bit data of the error status. (Step S43). In step S43, when it is determined that the TS packet size is over (step S43: Y), the error analysis unit 40 generates error occurrence information indicating that a fatal error has occurred in the TS packet (step S42). ).

  When it is determined in step S43 that the TS packet size is not over (step S43: N), the error analysis unit 40 uses the first buffer 20 (second buffer) based on the 29th bit data of the error status. It is determined whether or not writing has occurred during the writing request to 22) (step S44). In step S44, when it is determined that writing has occurred during a write request to the first buffer 20 (second buffer 22) (step S44: Y), the error analysis unit 40 determines that the TS packet (ES Error occurrence information indicating that a fatal error has occurred in (data) is generated (step S42).

  In step S44, when it is determined that writing has not occurred during the write request to the first buffer 20 (second buffer 22) (step S44: N), the error analysis unit 40 indicates the error status. Based on the 24-bit data, it is determined whether or not there is an RS code error as a tuner error (step S45). When it is determined in step S45 that an RS code error has occurred (step S45: Y), the error analysis unit 40 determines whether an error count indicating the number of consecutive packets in which an RS code error has occurred exceeds a predetermined threshold. Is determined (step S46).

  When it is determined in step S46 that the error count has exceeded the threshold (step S46: Y), error occurrence information indicating that a fatal error has occurred in the TS packet (ES data) is generated (step S42). . On the other hand, when it is determined in step S46 that the error count does not exceed the threshold value (step S46: N), the error count is incremented (step S47), and a minor error occurs in the TS packet (the ES data). Error occurrence information indicating that the error has occurred is generated (step S48).

  14A to 14C are explanatory diagrams of error occurrence information based on RS code errors. Here, it is assumed that the threshold value in step S46 is 3.

  FIG. 14A shows an error status indicating whether or not an RS code error has occurred in the error information added to the TS packet. The error analysis unit 40 monitors the error status shown in FIG. Then, the error analysis unit 40 can obtain an error count as a count result of counting error information for each packet by counting predetermined bits of the error status. More specifically, the error analysis unit 40 obtains an error count indicating the number of packets in which RS code errors have continuously occurred. This error count is initialized when a TS packet in which no RS code error has occurred is input.

  When such an error count exceeds the threshold “3”, it is determined that a fatal error has occurred, and when it does not exceed the threshold “3”, it is determined that a minor error has occurred.

  That is, the error analysis unit 40 can determine the occurrence of a fatal error or a minor error based on the count result obtained by counting error information for each packet. Then, error information is monitored for each packet, and when an error occurs continuously for the number of packets exceeding a given threshold, the occurrence of a fatal error is detected. The occurrence of a minor error can be detected when it occurs.

  For example, in FIG. 14A, since an RS code error has occurred continuously for 6 packets, the error analysis unit 40 determines that a fatal error has occurred and generates error occurrence information. Further, for example, in FIG. 14B, since an RS code error has occurred continuously for two packets, the error analysis unit 40 determines that a minor error has occurred and generates error occurrence information. Such error occurrence information is generated in units of packets, for example.

  Returning to FIG.

  When it is determined in step S45 that no RS code error has occurred (step S45: N), the error analysis unit 40 determines whether a synchronization byte mismatch has occurred based on the 25th bit data of the error status. It is determined whether or not (step S49). When it is determined in step S49 that a synchronization byte mismatch has occurred (step S49: Y), if there is another error factor (step S50: N), the error analysis unit 40 causes a fatal error in the TS packet. The error occurrence information indicating that has occurred is generated (step S42).

  When it is determined in step S49 that no synchronization byte mismatch has occurred (step S49: N), or when there is no other error factor in step S50 (step S50: Y), for example, the error detection unit 30 detects the PES header. When there is a next packet (step S51: Y), the process returns to step S40. In step S51, when there is no next packet (step S51: N), a series of processing ends (end).

  Similarly, in the processes following step S42 and step S48, when there is a next packet (step S51: Y), the process returns to step S40. In step S51, when there is no next packet (step S51: N), a series of processing ends (end).

  The error occurrence information generated by analyzing the error status by the error analysis unit 40 as described above is referred to by the reproduction data generation unit 50.

  FIG. 15 shows a flowchart of a processing example of the decoder 60.

  The decoder 60 includes a CPU (not shown), reads a program stored in a memory (not shown), and executes a process corresponding to the program so as to perform the process shown in FIG.

  First, the decoder 60 acquires error occurrence information generated by the error analysis unit 40 (step S60). When it is detected that a fatal error has occurred based on the error occurrence information (step S61: Y), IDR picture search processing (step S62) is performed, and a series of processing ends (end). ).

  On the other hand, when the occurrence of a fatal error is not detected based on the error occurrence information in step S61 (step S61: N), the decoder 60 determines whether or not a minor error has occurred based on the error occurrence information. Is determined (step S63). When it is detected that a minor error has occurred based on the error occurrence information (step S63: Y), a process of skipping to the next NAL (Network Abstraction Layer) unit is performed (step S64), and a series of processes End (end).

  In step S63, when it is detected that a minor error has not occurred based on the error occurrence information (step S63: N), the series of processing ends (end).

  As described above, the decoder 60 can perform the decoding process corresponding to the TS packet according to whether the error is a fatal error or a minor error determined by the error analysis unit 40. Therefore, even if the data is correct, the decoding process is not stopped, and the case where the decoding process is stopped despite the possibility of correct decoding can be eliminated.

2. Detailed Configuration Example Next, a detailed configuration example of the information reproducing apparatus in the present embodiment will be described. The information reproducing apparatus according to the present embodiment can reproduce digital terrestrial broadcasting.

2.1 Overview of 1-segment broadcasting In terrestrial digital broadcasting that appears in place of terrestrial analog broadcasting, there are high expectations for the provision of various new services in addition to improving the quality of images and audio.

  FIG. 16 is an explanatory diagram of the concept of digital terrestrial broadcast segments.

  In digital terrestrial broadcasting, a pre-assigned frequency band is divided into 14 segments, and broadcasting is performed using 13 segments SEG1 to SEG13. The remaining one segment is used as a guard band. Then, one segment SEGm out of 13 segments for broadcasting is allocated to the frequency band of broadcasting for mobile terminals.

  In one-segment broadcasting, a transport stream (Transport Stream: TS) in which video data, audio data, and other data (control data) encoded (compressed) are multiplexed is transmitted. More specifically, a Reed-Solomon error correction code is added to each packet of the TS, and then divided into layers, and convolutional coding and carrier modulation are performed in each layer. After layer synthesis, frequency interleaving and time interleaving are performed, and a pilot signal necessary for the receiving side is added to form an OFDM segment frame. The OFDM segment frame is subjected to inverse Fourier transform operation and transmitted as an OFDM signal.

  FIG. 17 is an explanatory diagram of TS.

  A TS is composed of a plurality of TS packet sequences as shown in FIG. The length of each TS packet is fixed to 188 bytes. Each TS packet has header information called a 4-byte TS header (TS header) added thereto, and includes a PID (Packet Identifier) serving as an identifier of the TS packet. One segment broadcast program is specified by PID.

  The TS packet includes an adaptation field, and is embedded with PCR (Program Clock Reference) and dummy data which are time information serving as a reference for synchronous reproduction of video data, audio data, and the like. The payload includes data for generating a PES (Packetized Elementary Stream) packet or section.

  FIG. 18 is an explanatory diagram of PES packets and sections.

  Each of the PES packet and the section is configured by the payload of each TS packet of one or a plurality of TS packets. The PES packet includes a PES header and a payload, and video data, audio data, or caption data is set as ES (Elementary Stream) data in the payload. In the section, program information such as video data set in the PES packet is set.

  Therefore, when a TS is received, first, it is necessary to analyze program information included in the section and specify a PID corresponding to the broadcast program. Then, video data and audio data corresponding to the PID are extracted from the TS, and the extracted video data and audio data are reproduced.

2.2 Mobile terminal A mobile terminal having a 1-segment broadcast receiving function requires processing such as packet analysis as described above. That is, such a mobile terminal is required to have a high processing capacity. Therefore, when a one-segment broadcast receiving function is added to a conventional mobile phone as a mobile terminal (electronic device in a broad sense), it is necessary to further add a processor or the like having a high processing capacity.

  FIG. 19 shows a block diagram of a configuration example of a mobile phone including a multimedia processing CPU in a comparative example of the present embodiment.

  In this cellular phone 900, the received signal received via the antenna 910 is demodulated, the telephone CPU 920 performs the incoming call processing, and the signal processed by the telephone CPU 920 is modulated and transmitted via the antenna 910. Sent. The telephone CPU 920 can read a program stored in the memory 922 and perform incoming call processing and outgoing call processing.

  When a desired signal is extracted from the received signal received via the antenna 930 via the tuner 940, a TS is generated by using the desired signal as an OFDM signal in the reverse procedure. The multimedia processing CPU 950 analyzes the TS packet from the generated TS, determines the PES packet and the section, and decodes video data and audio data from the TS packet of the desired program. The multimedia processing CPU 950 can read the program stored in the memory 952 and perform the above-described packet analysis processing and decoding processing. The display panel 960 performs display output based on the decoded video data, and the speaker 970 performs audio output based on the decoded audio data.

  In this way, the multimedia processing CPU 950 requires a very high processing capability. In general, a processor having a high processing capability has a high operating frequency and a large circuit scale.

  By the way, considering the bit rate of 1-segment broadcasting, most of the bandwidth is considered to be the bandwidth for video data and audio data, and the bandwidth for data broadcasting itself is narrowed. Accordingly, among the processes that can be realized by the multimedia processing CPU, it is necessary to always operate the multimedia processing CPU even though only the reproduction processing of video data and audio data may be required, resulting in an increase in power consumption. .

  Therefore, in this embodiment, a video decoder that performs video data decoding processing and an audio decoder that performs audio data decoding processing are provided independently, and the decoding processing is performed independently, thereby reducing the processing capability of each. You can adopt things. Furthermore, it is possible to flexibly reduce power consumption by appropriately stopping one of the operations of the video decoder and the audio data.

  Furthermore, since the video decoder and the audio decoder can be operated in parallel, the processing capability of each decoder can be reduced, and lower power consumption and cost can be realized.

  FIG. 20 shows a block diagram of a configuration example of a mobile phone including the information reproducing apparatus in the present embodiment. In FIG. 20, the same parts as those in FIG. 19 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The cellular phone 100 includes a host CPU (host in a broad sense) 110, a RAM (Random Access Memory) 120, a ROM (Read Only Memory) 130, a display driver 140, a DAC (Digital-to-Analog Converter) 150, an image processing IC ( Integrated Circuit) (information reproducing apparatus in a broad sense) 200 can be included. Further, the cellular phone 100 includes antennas 910 and 930, a tuner 940, a display panel 960, and a speaker 970.

  The host CPU 110 has a function of controlling the image processing IC 200 as well as the function of the telephone CPU 920 of FIG. The host CPU 110 reads a program stored in the RAM 120 or the ROM 130, and performs processing of the telephone CPU 920 in FIG. At this time, the host CPU 110 can use the RAM 120 as a work area.

  The image processing IC 200 receives, from the TS from the tuner 940, a video TS packet (first TS packet) for generating video data and an audio TS packet (second TS packet) for generating audio data. Extract and buffer in a shared memory (not shown). The image processing IC 200 includes a video decoder and an audio decoder (not shown) capable of controlling the operation stop independently of each other. The video decoder and the audio decoder decode the video TS packet and the audio TS packet, respectively. Video data and audio data are generated. The video data and the audio data are supplied to the display driver 140 and the DAC 150, respectively, while being synchronized. The host CPU 110 can instruct the image processing IC 200 to start the video decoding process and the audio decoding process. The host CPU 110 may instruct the image processing IC 200 to start at least one of video decoding processing and audio decoding processing.

  A display driver (driving circuit in a broad sense) 140 drives a display panel (electro-optical device in a broad sense) 960 based on video data. More specifically, the display panel 960 includes a plurality of scanning lines, a plurality of data lines, and a plurality of pixels, each pixel being specified by each scanning line and each data line. Crystal Display panel can be used. The display driver 140 has a function of a scanning driver that scans a plurality of scanning lines and a function of a data driver that drives a plurality of data lines based on the video data.

  The DAC 150 converts audio data that is a digital signal into an analog signal and supplies the analog signal to the speaker 970. The speaker 970 outputs sound corresponding to the analog signal from the DAC 150.

2.3 Image processing IC
FIG. 21 shows a block diagram of a configuration example of the image processing IC 200 of FIG. 20 as the information reproducing apparatus of the present embodiment.

  The image processing IC 200 includes a TS separation unit (separation processing unit) 210, a memory (shared memory) 220, a video decoder 230, and an audio decoder 240. The image processing IC 200 further includes a display control unit 250, a tuner I / F (Interface) 260, a host I / F 270, a driver I / F 280, and an audio I / F 290. The memory 220 has the function of the memory 80 of FIG. Accordingly, the memory 220 has the functions of the first and second buffers 20 and 22.

  That is, the first buffer has a first storage area in which the first TS packet is stored, a second storage area in which the second TS packet is stored, and a third storage area in which the third TS packet is stored. 3 storage areas. In addition, it can be said that the second buffer has a fourth storage area in which video reproduction data is stored and a fifth storage area in which audio reproduction data is stored.

  The TS separation unit 210 includes a video TS packet (first TS packet) for generating video data, an audio TS packet (second TS packet) for generating audio data, a video TS packet, and audio. Packets other than the TS packet for use (third TS packet) are extracted from the TS. The TS separation unit 210 can extract the first and second TS packets based on the analysis result of the host CPU 110 that analyzes the third TS packet once extracted from the TS. The TS separation unit 210 has the function of the error detection unit 30 in FIG. That is, the TS separation unit 210 can detect an error in each TS packet of the first to third TS packets, and add error information indicating the presence or absence of an error to each TS packet.

  The video decoder 230 reads the video TS packet from the storage area dedicated to the video TS packet in the storage area of the memory 220 and performs video decoding processing for generating video data based on the video TS packet. A reference timing for reproducing video data and audio data in synchronization is generated. The video decoder 230 has the function of the reproduction data generation unit 50 of FIG.

  The audio decoder 240 reads the audio TS packet from the storage area dedicated to the audio TS packet in the storage area of the memory 220 and performs audio decoding processing for generating audio data based on the audio TS packet.

  At least one of the video decoder 230 and the audio decoder 240 has the functions of the decoder 60 and the error analysis unit 40 in FIG. 1 may include a video decoder 230 and an audio decoder 240.

  The function of the dummy data control unit 70 in FIG. 1 can be realized by the TS separation unit 210, the video decoder 230, or the audio decoder 240.

  The display control unit 250 performs a rotation process for rotating the orientation of the image represented by the video data read from the memory 220 and a resizing process for reducing or enlarging the size of the image. The data after the rotation processing and the data after the resizing processing are supplied to the driver I / F 280. The display control unit 250 performs control to transfer the processed data to the driver I / F 280 in accordance with the display timing.

  The tuner I / F 260 performs an interface process with the tuner 940. More specifically, the tuner I / F 260 performs control to receive a TS from the tuner 940. Tuner I / F 260 is connected to TS separator 210. A tuner 940 connected to the tuner I / F 260 has a digital tuner function.

  The host I / F 270 performs interface processing with the host CPU 110. More specifically, the host I / F 270 controls data transmission / reception with the host CPU 110. The host I / F 270 is connected to the TS separation unit 210, the memory 220, the display control unit 250, and the audio I / F 290. A host CPU 110 connected to the host I / F 270 realizes a host function.

  The driver I / F 280 reads video data from the memory 220 via the display control unit 250 at a predetermined cycle, and supplies the video data to the display driver 140. The driver I / F 280 performs interface processing for transmitting video data to the display driver 140.

  The audio I / F 290 reads audio data from the memory 220 at a predetermined cycle and supplies the audio data to the DAC 150. The audio I / F 290 performs interface processing for transmitting audio data to the DAC 150.

  The display driver and the DAC in FIG. 21 can be used as an output unit.

  In such an image processing IC 200, the TS packet is extracted from the TS from the tuner 940 by the TS separator 210. The TS packet is stored in a pre-allocated storage area of the memory 220 as a shared memory. Then, the video decoder 230 and the audio decoder 240 respectively read out TS packets from dedicated storage areas allocated to the memory 220, generate video data and audio data, and display the synchronized video data and audio data with the display driver 140. And to the DAC 150.

  FIG. 22 is an operation explanatory diagram of the image processing IC 200 of FIG.

  22, the same parts as those in FIG. 21 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The memory 220 has first to eighth storage areas AR1 to AR8, and each storage area is assigned in advance. A TS packet separated by the TS separation unit 210 and error information as a result of error detection processing performed on the TS packet by the TS separation unit 210 are stored in each storage area.

  The first storage area AR1 stores the video TS packet (first TS packet) extracted by the TS separation unit 210 as a storage area dedicated to the video TS packet. The second storage area AR2 stores the voice TS packet (second TS packet) extracted by the TS separation unit 210 as a storage area dedicated to the voice TS packet. In the third storage area AR3, TS packets (third TS packets) excluding video TS packets and audio TS packets among the TS packets extracted by the TS separator 210 are stored. The first and second storage areas AR1 and AR2 can function as the first buffer 20 in FIG.

  The fourth storage area AR4 stores the video ES data generated by the video decoder 230 as a storage area dedicated to the video ES data. The fifth storage area AR5 stores the audio ES data generated by the audio decoder 240 as a storage area dedicated to the audio ES data. The fourth and fifth storage areas AR4 and AR5 can function as the second buffer 22 in FIG.

  In the sixth storage area AR6, a TS generated by the host CPU 110 is stored as TSRAW data. TSRAW data is set by the host CPU 110 instead of the TS from the tuner 940. Then, the TS separation unit 210 extracts a video TS packet, an audio TS packet, and other TS packets from the TS set as TSRAW data.

  In the seventh storage area AR7, video data after decoding by the video decoder 230 is stored. The video data stored in the seventh storage area AR7 is read by the display control unit 250 and used for video output by the display panel 960. The eighth storage area AR8 stores the audio data after the decoding process by the audio decoder 240. The audio data stored in the eighth storage area AR8 is provided for audio output by the speaker 970.

  The video decoder 230 includes a header deletion processing unit 232 and a video decoding processing unit 234. The header deletion processing unit 232 reads the video TS packet from the first storage area AR1, analyzes the TS header of the video TS packet, generates a PES packet (first PES packet), and then generates the PES header. The payload portion is stored in the fourth storage area AR4 of the memory 220 as video ES data. Then, the video decoder 230 including the header deletion processing unit 232 instructs the display control unit 250 to transfer image data in accordance with the display timing.

  The video decoding processing unit 234 reads video ES data from the fourth storage area AR4, Video data generated by performing decoding processing (video decoding processing in a broad sense) in accordance with the H.264 / AVC (Advanced Video Coding) standard is written to the seventh storage area AR7.

  The audio decoder 240 includes a header deletion processing unit 242 and an audio decoding processing unit 244. The header deletion processing unit 242 reads the audio TS packet from the second storage area AR2, analyzes the TS header of the audio TS packet, generates a PES packet (second PES packet), and then generates the PES header. The payload portion is stored as audio ES data in the fifth storage area AR5 of the memory 220. The audio decoding processing unit 244 generates audio ES data from the fifth storage area AR5, and performs decoding processing (audio decoding processing in a broad sense) in accordance with the MPEG-2 AAC (Advanced Audio Coding) standard. Audio data is written to the eighth storage area AR8.

  Then, the video decoder 230 reads the video TS packet (first TS packet) from the first storage area AR1, independently of the audio decoder 240, and performs the video decoding process based on the video TS packet. I do. Also, the audio decoder 240 reads the audio TS packet (second TS packet) from the second storage area AR2 independently of the video decoder 230, and performs the above audio decoding process based on the audio TS packet. Do. In this way, the video decoder 230 and the audio decoder 240 can be operated when the video and audio are output in synchronism, while only the video decoder 230 is operated and output when only the video is output. The operation of the decoder 240 can be stopped. When outputting only audio, only the audio decoder 240 can be operated to stop the operation of the video decoder 230.

  The host CPU 110 reads another TS packet (third TS packet) stored in the third storage area AR3, and generates a section from the TS packet. Then, various table information included in the section is analyzed. The host CPU 110 sets the analysis result in a predetermined storage area of the memory 220 and specifies it as control information for the TS separation unit 210. Thereafter, the TS separation unit 210 extracts TS packets from the tuner 940 according to the control information. On the other hand, the host CPU 110 can issue activation commands to the video decoder 230 and the audio decoder 240 separately. The video decoder 230 and the audio decoder 240 independently access the memory 220, read the analysis result of the host CPU 110, and perform a decoding process corresponding to the analysis result.

2.3.1 Reproduction Operation Next, an operation in the case of reproducing video data or audio data multiplexed on a TS in the image processing IC 200 as an information reproduction apparatus in the present embodiment will be described.

  FIG. 23 shows a flowchart of an operation example of reproduction processing by the host CPU 110. The host CPU 110 can perform the processing shown in FIG. 23 by reading a program stored in the RAM 120 or the ROM 130 and executing processing corresponding to the program.

  First, the host CPU 110 performs a broadcast reception start process (step S100). Thereby, video data or audio data of a desired program among a plurality of programs received as a TS can be extracted from the TS. Then, the host CPU 110 activates at least one of the video decoder 230 and the audio decoder 240 of the image processing IC 200.

  Thereafter, the host CPU 110 causes the video decoder 230 and the audio decoder 240 to perform decoding processing when reproducing video and audio. Alternatively, the host CPU 110 stops the operation of the audio decoder 240 and causes the video decoder 230 to perform decoding processing when reproducing only the video. Alternatively, when reproducing only audio, the host CPU 110 stops the operation of the video decoder 230 and causes the audio decoder 240 to perform decoding processing (step S101).

  Next, the host CPU 110 performs broadcast reception end processing (step S102), and ends a series of processing (end). As a result, the host CPU 110 stops the operation of each unit of the image processing IC 200.

2.3.2 Broadcast Reception Start Process Next, a process example of the broadcast reception start process shown in FIG. 23 will be described. Here, a case where video and audio are reproduced will be described.

  FIG. 24 shows a flowchart of an operation example of the broadcast reception start process of FIG. The host CPU 110 can perform the process shown in FIG. 24 by reading a program stored in the RAM 120 or the ROM 130 and executing a process corresponding to the program.

  First, the host CPU 110 activates the video decoder 230 and the audio decoder 240 of the image processing IC 200 (step S110). Thereafter, the host CPU 110 initializes the tuner 940 and sets given operation information (step S111). Then, the host CPU 110 also initializes the DAC 150 and sets given operation information (step S112).

  Thereafter, the host CPU 110 monitors reception of TS (step S113: N). When reception of the TS is started, in the image processing IC 200, the TS separation unit 210 separates the TS from the TS into the video TS packet, the audio TS packet, and the other TS packets as described above, and the separated TS packet. Is stored in a storage area of a memory 220 provided for exclusive use. For example, the host CPU 110 can detect reception of a TS by an interrupt signal generated on the condition that a TS packet is stored in the third storage area AR3 in the memory 220 of the image processing IC 200. Alternatively, the host CPU 110 can periodically determine whether the TS packet has been written by accessing the third storage area AR3 of the memory 220, thereby determining the reception of the TS.

  When reception of a TS is detected in this way (step S113: Y), the host CPU 110 reads a TS packet stored in the third storage area AR3 and generates a section. Then, PSI (Program Specific Information) / SI (Service Information: program arrangement information) included in the section is analyzed (step S114). This PSI / SI is defined by the MPEG-2 system (ISO / IEC 13818-1).

  PSI / SI includes NIT (Network Information Table) and PMT (Program Map Table). The NIT includes, for example, a network identifier for specifying which broadcasting station the TS is from, a service identifier for specifying the PMT, a service type identifier indicating the type of broadcast, and the like. In the PMT, for example, the PID of the video TS packet multiplexed in the TS and the PID of the audio TS packet are set.

  Therefore, the host CPU 110 extracts a service identifier for specifying the PMT from the PSI / SI, and can specify the PID of the received video TS packet and audio TS packet based on the service identifier (step S115). . Then, a predetermined storage in the memory 220 is provided so that the host CPU 110 can refer to the video decoder 230 and the audio decoder 240 for the PID corresponding to the program selected by the user of the mobile terminal or the PID corresponding to the predetermined program. An area (for example, the third storage area AR3) is set (step S116), and a series of processing ends (end).

  In this way, the video decoder 230 and the audio decoder 240 can perform decoding processing on the video TS packet and the audio TS packet while referring to the PID set in the memory 220.

  The host CPU 110 sets information corresponding to, for example, a service identifier for specifying the PMT in the TS separation unit 210 of the image processing IC 200. In this way, the TS separation unit 210 determines a section periodically received at a predetermined time interval, analyzes the PMT corresponding to the service identifier, and identifies the video TS specified by the PMT. Packets and TS packets for voice and other TS packets are extracted and stored in the memory 220.

  FIG. 25 is an operation explanatory diagram of the broadcast reception start process of the image processing IC 200 of FIGS. 21 and 22. In FIG. 25, the same parts as those in FIG. 21 or FIG.

  In FIG. 25, the seventh storage area AR7 is shared with the fourth storage area AR4, and the eighth storage area AR8 is shared with the fifth storage area AR5. In addition, PSI / SI, NIT, and PMT are stored in a predetermined storage area in the third storage area AR3.

  First, when TS is input from the tuner 940 (SQ1), the TS separation unit 210 stores a TS packet including PSI / SI in the memory 220 (SQ2). The TS separation unit 210 performs error detection processing, adds the result as error information, and stores the TS packet in the memory 220. At this time, the TS separation unit 210 can extract the PSI / SI itself of the TS packet and store it in the memory 220. Further, the TS separation unit 210 can extract the NIT from the PSI / SI and store it in the memory 220.

  The host CPU 110 reads PSI / SI, NIT, and PMT (SQ3), analyzes them, and identifies the PID corresponding to the program to be decoded. Then, the host CPU 110 sets information corresponding to the service identifier or PID corresponding to the program to be decoded in the TS separation unit 210 (SQ4). The host CPU 110 also sets the PID in a predetermined storage area of the memory 220 and refers to it during decoding processing by the video decoder 230 and the audio decoder 240. Here, the host CPU 110 can discard the TS packet based on the error information.

  The TS separation unit 210 extracts video TS packets and audio TS packets from the TS based on the set PID, and writes them to the first and second storage areas AR1 and AR2, respectively (SQ5).

  Thereafter, the video decoder 230 and the audio decoder 240 activated by the host CPU 110 sequentially read the video TS packet and the audio TS packet from the first and second storage areas AR1 and AR2 (SQ6), and perform video decoding processing and Perform audio decoding.

  At this time, in the next sequence, the host CPU 110, the video decoder 230, and the audio decoder 240 perform communication via command data.

2.3.3 Broadcast Reception End Process Next, an operation example of the broadcast reception end process shown in FIG. 23 will be described. Here, a case where video and audio are reproduced will be described.

  FIG. 26 shows a flowchart of a processing example of the broadcast reception end processing of FIG. The host CPU 110 can perform the process shown in FIG. 26 by reading a program stored in the RAM 120 or the ROM 130 and executing a process corresponding to the program.

  First, the host CPU 110 stops the video decoder 230 and the audio decoder 240 of the image processing IC 200 (step S120). In this case, the host CPU 110 issues a command to the image processing IC 200, and the image processing IC 200 stops the video decoder 230 and the audio decoder 240 using the decoding result of the control command.

  Thereafter, the host CPU 110 similarly stops the TS separation unit 210 (step S121). Then, the host CPU 110 stops the tuner 940 (step S122).

  FIG. 27 is an operation explanatory diagram of the broadcast reception end process of the image processing IC 200 of FIGS. 21 and 22. In FIG. 27, the same parts as those in FIG. 25 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  First, the host CPU 110 performs control to stop the operation of the display control unit 250, and stops the supply of video data to the display driver 140 (SQ10). Next, the host CPU 110 stops the operations of the video decoder 230 and the audio decoder 240 (SQ11), and then stops the operations in the order of the TS separation unit 210 and the tuner 940 (SQ12, SQ13).

2.3.4 Reproduction Process 2.3.4.1 Reproduction Process of Video Data Next, an operation example of the video decoder 230 that performs the reproduction process of the video data will be described.

  FIG. 28 shows a flowchart of an example of memory access operation of the video decoder 230 performed during the video decoding process.

  First, the video decoder 230 determines whether or not the first storage area AR1 provided as the video TS buffer is in an empty state (step S140). When there is no video TS packet to be read from the first storage area AR1, the state becomes empty.

  When it is determined in step S140 that the first storage area AR1 that is the video TS buffer is not empty (step S140: N), the video decoder 230 further includes a fourth storage area provided as a video ES buffer. It is determined whether or not AR4 is full (step S141). When no more video ES data can be stored in the fourth storage area AR4, the full state is entered.

  When it is determined in step S141 that the fourth storage area AR4 that is the video ES buffer is not full (step S141: N), the video decoder 230 reads the video TS packet from the first storage area AR1, It is detected whether or not the PID (specified PID) specified by the host CPU 110 in step S116 in FIG. 24 (step S142).

  When it is detected in step S142 that the PID of the video TS packet is the designated PID (step S142: Y), the video decoder 230 analyzes the TS header and the PES header (step S143), and the video ES data Are stored in a fourth storage area AR4 provided as a video ES buffer (step S144).

  Thereafter, the video decoder 230 updates the read pointer for specifying the read address of the first storage area AR1, which is a video TS buffer (step S145), and returns to step S140 (return).

  When it is detected in step S142 that the PID of the video TS packet is not the designated PID (step S142: N), the process proceeds to step S145. When it is determined in step S140 that the first storage area AR1 that is the video TS buffer is in an empty state (step S140: Y), or in step S141, the fourth storage area AR4 that is the video ES buffer. Is determined to be full (step S141: Y), the process returns to step S140 (return).

  The video ES data stored in the fourth storage area AR4 in this way is sent to the H.264 by the video decoder 230. The decoding process is performed according to the H.264 / AVC standard and is written as video data in the seventh storage area AR7.

  FIG. 29 is an operation explanatory diagram of the video decoder of the image processing IC 200 of FIGS. 21 and 22. In FIG. 29, the same parts as those in FIG. 25 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  In FIG. 29, the seventh storage area AR7 is shared with the fourth storage area AR4, and the eighth storage area AR8 is shared with the fifth storage area AR5. In addition, PSI / SI, NIT, and PMT are stored in a predetermined storage area in the third storage area AR3.

  First, as shown in FIG. 24, the host CPU 110 sets the PID corresponding to the program to be decoded in the TS separator 210 (SQ20). When a TS is input from the tuner 940 (SQ21), the TS separation unit 210 separates the video TS packet, audio TS packet, and other TS packets from the TS from the tuner 940 (SQ22). The video TS packet separated by the TS separation unit 210 is stored in the first storage area AR1 together with the error information generated by the TS separation unit 210. The audio TS packet separated by the TS separation unit 210 is stored in the second storage area AR2 together with the error information generated by the TS separation unit 210. TS packets other than the video TS packet and audio TS packet separated by the TS separation unit 210 are stored in the third storage area AR3 as PSI / SI together with error information generated by the TS separation unit 210. At this time, the TS separation unit 210 extracts NIT and PMT in the PSI / SI and stores them in the third storage area AR3.

  Next, the video decoder 230 activated by the host CPU 110 reads the video TS packet from the first storage area AR1 (SQ23). At this time, the video decoder 230 refers to the error information described above and determines whether to perform video decoding processing or discard video TS packets. When it is determined to perform the video decoding process, the video decoder 230 generates video ES data and stores the video ES data in the fourth storage area AR4 (SQ24).

  After that, the video decoder 230 reads the video ES data from the fourth storage area AR4 (SQ25). The decoding process according to the H.264 / AVC standard is performed. In FIG. 25, the video data after the decoding process is directly supplied to the display control unit 250 (SQ26). For example, the video data after the decoding process is once written back to a predetermined storage area of the memory 220, and then It is desirable to supply the display control unit 250 while synchronizing with the output timing of the audio data.

  Based on the video data thus supplied to the display control unit 250, the display driver 140 drives the display panel (SQ27).

2.3.4.2 Audio Data Reproduction Processing Next, an operation example of the audio decoder 240 that performs audio data reproduction processing will be described.

  FIG. 30 shows a flowchart of an example of memory access operation of the audio decoder 240 performed during the audio decoding process.

  First, when activated by the host CPU 110, the audio decoder 240 reads out a program stored in a predetermined storage area of the memory 220, for example, and executes the processing shown in FIG. 30 by executing processing corresponding to the program. Can be done. That is, the audio decoder 240 includes a CPU (central processing unit), and after initialization processing of the image processing IC 200 (information reproduction device), a program for realizing audio decoding processing is read into the CPU from outside the image processing IC 200. Thus, the CPU can realize the audio decoding process.

  First, the audio decoder 240 determines whether or not the second storage area AR2 provided as the audio TS buffer is in an empty state (step S150). When there is no audio TS packet to be read from the second storage area AR2, the state becomes empty.

  When it is determined in step S150 that the second storage area AR2 that is the audio TS buffer is not empty (step S150: N), the audio decoder 240 further includes a fifth storage area provided as an audio ES buffer. It is determined whether or not AR5 is full (step S151). When no more audio ES data can be stored in the fifth storage area AR5, the full state is entered.

  When it is determined in step S151 that the fifth storage area AR5, which is the audio ES buffer, is not full (step S151: N), the audio decoder 240 reads the audio TS packet from the second storage area AR2, It is detected whether or not the PID (specified PID) specified by the host CPU 110 in step S116 in FIG. 24 (step S152).

  When it is detected in step S152 that the PID of the audio TS packet is the designated PID (step S152: Y), the audio decoder 240 analyzes the TS header and the PES header (step S153), and the audio ES data Are stored in a fifth storage area AR5 provided as an audio ES buffer (step S154).

  After that, the audio decoder 240 updates the read pointer for specifying the read address of the second storage area AR2 that is the audio TS buffer (step S155), and returns to step S150 (return).

  When it is detected in step S152 that the PID of the voice TS packet is not the designated PID (step S152: N), the process proceeds to step S155. When it is determined in step S150 that the second storage area AR2 that is the audio TS buffer is in an empty state (step S150: Y), or in step S151, the fifth storage area AR5 that is the audio ES buffer. Is determined to be full (step S151: Y), the process returns to step S150 (return).

  The audio ES data stored in the fifth storage area AR5 in this manner is decoded by the audio decoder 240 in accordance with the MPEG-2 AAC standard and written as audio data in the eighth storage area AR8.

  FIG. 31 is an operation explanatory diagram of the audio decoder of the image processing IC 200 of FIGS. 21 and 22. In FIG. 31, the same parts as those of FIG.

  In FIG. 31, the seventh storage area AR7 is shared with the fourth storage area AR4, and the eighth storage area AR8 is shared with the fifth storage area AR5. In addition, PSI / SI, NIT, and PMT are stored in a predetermined storage area in the third storage area AR3.

  First, as shown in FIG. 24, the host CPU 110 sets the PID corresponding to the program to be decoded in the TS separator 210 (SQ30). When a TS is input from the tuner 940 (SQ31), the TS separation unit 210 separates the video TS packet, the audio TS packet, and the other TS packets from the TS from the tuner 940 (SQ32). The video TS packet separated by the TS separation unit 210 is stored in the first storage area AR1 together with the error information generated by the TS separation unit 210. The audio TS packet separated by the TS separation unit 210 is stored in the second storage area AR2 together with the error information generated by the TS separation unit 210. TS packets other than the video TS packet and audio TS packet separated by the TS separation unit 210 are stored in the third storage area AR3 as PSI / SI together with error information generated by the TS separation unit 210. Furthermore, the TS separation unit 210 can extract NIT and PMT in the PSI / SI and write them in a predetermined storage area of the third storage area AR3.

  Next, the audio decoder 240 activated by the host CPU 110 reads the audio TS packet from the second storage area AR2 (SQ33). At this time, the audio decoder 240 determines whether to perform the audio decoding process or discard the audio TS packet with reference to the error information described above. When it is determined to perform the audio decoding process, the audio decoder 240 generates audio ES data and stores the audio ES data in the fifth storage area AR5 (SQ34).

  Thereafter, the audio decoder 240 reads the audio ES data from the fifth storage area AR5 (SQ35), and performs a decoding process according to the MPEG-2 AAC standard. In FIG. 31, the audio data after the decoding process is directly supplied to the DAC 150 (SQ36). For example, the audio data after the decoding process is once written back to a predetermined storage area of the memory 220, and then the video data It is desirable to supply to the DAC 150 in synchronization with the output timing.

  The operation of the audio decoder 240 as described above is performed independently of the operation of the video decoder 230.

2.3.5 IDR picture search processing In this embodiment, a fatal error or a minor error is determined as described with reference to FIGS. 13 to 15 to perform a decoding process according to the determination result. it can. When a fatal error is detected, IDR picture search processing is performed. When a minor error is detected, processing for skipping the slice is performed.

  The process for determining a fatal error or a minor error is the same as the process shown in FIG. The process of switching according to a fatal error or a minor error is the same as the process shown in FIG. Hereinafter, details of the IDR picture search processing performed by the video decoder 230 will be described.

  FIG. 32 shows a flowchart of a detailed processing example of the IDR picture search processing performed by the video decoder 230. The process shown in FIG. 32 is performed in, for example, step S62 in FIG.

  The video decoder 230 interrupts the video decoding process before performing the process of searching for the IDR picture (step S160). Subsequently, when there is a normal video TS packet in the first storage area AR1 of the memory 220 (step S161: Y, step S162: Y), the video decoder 230 causes the header deletion processing unit 232 to perform the first storage. After the TS header of the video TS packet read from the area AR1 is analyzed to generate a PES packet, the PES header is deleted, and the payload portion is used as video ES data in the fourth storage area of the memory 220. Store in AR4 (step S163).

  On the other hand, when there is no data in the first storage area AR1 (step S161: N), when there is data in the first storage area AR1 but is not normal data (step S161: Y, step S162: N), video The decoder 230 returns to step S161 and waits until a normal video TS packet is stored in the first storage area AR1.

  After step S163, if the memory 220 is in an empty state and can be used (step S164: Y), the process returns to step S161. Thereby, the separation process for deleting the TS header from the TS packet is continuously performed.

  In step S164, when the memory 220 becomes full and cannot be used (step S164: N), the video decoder 230 performs IDR picture search processing (step S165). When an IDR picture is searched (step S166: Y), the video decoding processing unit 234 performs video decoding processing (step S167), and ends a series of processing (end).

  In step S166, when an IDR picture is not searched (step S166: N), the process returns to step S163 to perform a separation process for deleting a TS header from the TS packet.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. In the above embodiment or its modification, an example applicable to terrestrial digital broadcasting has been described. However, the present invention is not limited to one applicable to terrestrial digital broadcasting.

  In the present embodiment, mainly H.264 is used. Although the case where the present invention is applied to decoding processing conforming to H.264 / AVC has been described, the present invention is not limited to this, and other standards, It goes without saying that the present invention can be applied to decoding processing based on a standard developed from the H.264 / AVC standard.

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention can be made dependent on another independent claim.

The block diagram of the structural example of the information reproduction apparatus in this embodiment. Explanatory drawing of the emulation performed with respect to the start code in this embodiment. The flowchart of the operation example of the start code emulation process of FIG. FIG. 4 is an explanatory diagram of an example of an operation result of the start code emulation process of FIG. 3. Explanatory drawing of the 2nd buffer in this embodiment. The flowchart of the example of a dummy data write-in process in this embodiment. The flowchart of the process example which determines the write data size of dummy data. Explanatory drawing of the error information added to TS packet in this embodiment. FIG. 9 is a detailed explanatory diagram of the error information in FIG. 8. FIG. 10 is an explanatory diagram of an example of contents of the error status in FIG. 9. Explanatory drawing of the storage condition of the error information in this embodiment, and the buffer of TS packet. The figure which shows an example of the addition timing of the error information in this embodiment. The flowchart of the process example of an error analysis part. FIGS. 14A to 14C are explanatory diagrams of error occurrence information based on RS code errors. The flowchart of the process example of a decoder. Explanatory drawing of the concept of the segment of digital terrestrial broadcasting. Explanatory drawing of TS. Explanatory drawing of a PES packet and a section. The block diagram of the structural example of the mobile telephone containing the multimedia processing CPU in the comparative example of this embodiment. The block of the structural example of the mobile telephone containing the information reproduction apparatus in this embodiment. FIG. 21 is a block diagram of a configuration example of the image processing IC in FIG. 20. FIG. 22 is an operation explanatory diagram of the image processing IC in FIG. 21. The flowchart of the operation example of the reproduction | regeneration processing by host CPU. The flowchart of the operation example of the broadcast reception start process of FIG. FIG. 23 is an operation explanatory diagram of broadcast reception start processing of the image processing IC of FIGS. 21 and 22. The flowchart of the process example of the broadcast reception end process of FIG. FIG. 23 is an operation explanatory diagram of broadcast reception end processing of the image processing IC of FIGS. 21 and 22. The flowchart of the example of memory access operation | movement of a video decoder. FIG. 23 is an operation explanatory diagram of a video decoder of the image processing IC in FIGS. 21 and 22. The flowchart of the example of memory access operation | movement of an audio | voice decoder. FIG. 23 is an operation explanatory diagram of the audio decoder of the image processing IC in FIGS. 21 and 22. The flowchart of the detailed process example of the search process of an IDR picture.

Explanation of symbols

10 information reproducing device, 20 first buffer, 22 second buffer,
30 error detection unit, 40 error analysis unit, 50 reproduction data generation unit,
60 decoder, 70 dummy data control unit, 80 memory,
100 mobile phone, 110 host CPU, 120 RAM, 130 ROM,
140 display driver, 150 DAC, 200 image processing IC,
210 TS separator, 230 video decoder, 240 audio decoder,
250 display control unit, 260 tuner I / F, 270 host I / F,
280 Driver I / F, 290 Audio I / F, 910, 930 Antenna, 940 Tuner, 960 Display panel, 970 Speaker

Claims (11)

A first buffer in which input packets are stored;
An error detection unit for adding error information obtained as a result of detecting an error in the input packet to the input packet and storing the error information together with the input packet in the first buffer;
Based on the error information, an error analysis unit that analyzes the error of the packet;
A reproduction data generation unit for generating reproduction data based on the packet stored in the first buffer;
A second buffer in which the reproduction data is stored;
A decoder for decoding the reproduction data stored in the second buffer,
When an error is detected by the error analysis unit, dummy data is stored in the second buffer instead of the reproduction data. In claim 1,
A dummy data control unit for storing the dummy data in the second buffer;
The dummy data control unit
An information reproducing apparatus, wherein dummy data having a size corresponding to a free capacity of the second buffer is stored in the second buffer. In claim 1 or 2,
When a dummy code is inserted or added to the normal code string to be distinguished from a given prohibited code and stored in the second buffer,
The dummy data is
The information reproducing apparatus according to claim 1, wherein the data is the same data as the code string immediately before the dummy code is inserted in the normal code string. In any one of Claims 1 thru | or 3,
The dummy data control unit
When an error is detected by the error analysis unit, dummy data having a data size greater than or equal to the maximum read data size of the second buffer is written to the second buffer one or more times. apparatus. In any one of Claims 1 thru | or 4,
The error analysis unit
Determining whether a first or second error has occurred based on error information added to the packet stored in the first buffer;
An information reproducing apparatus characterized in that dummy data is stored in the second buffer instead of the reproducing data on condition that the first error is determined to occur. In any one of Claims 1 thru | or 5,
A first TS (Transport Stream) packet for generating video reproduction data, a second TS packet for generating audio reproduction data, and a third TS other than the first and second TS packets Including a separation processing unit for extracting TS packets from the transport stream;
The first buffer comprises:
A first storage area for storing the first TS packet; a second storage area for storing the second TS packet; and a third storage area for storing the third TS packet; Have
The second buffer comprises:
A fourth storage area in which the video reproduction data is stored; and a fifth storage area in which the audio reproduction data is stored;
The decoder
A video decoder that performs video decoding processing for generating video playback data based on the first TS packet read from the first storage area, and stores the playback data in the fourth storage area When,
An audio decoder that performs audio decoding processing for generating audio reproduction data based on the second TS packet read from the second storage area, and stores the reproduction data in the fifth storage area Including
An information reproducing apparatus for outputting reproduction data from at least one of the fourth and fifth storage areas. In claim 6,
The video decoder reads the first TS packet from the first storage area independently of the audio decoder, performs the video decoding process based on the first TS packet,
The audio decoder reads the second TS packet from the second storage area independently of the video decoder, and performs the audio decoding process based on the second TS packet. Information playback device. In claim 6 or 7,
When reproducing only the video data of the video data and audio data, stop the operation of the audio decoder,
An information reproducing apparatus characterized by stopping the operation of the decoding apparatus when reproducing only the audio data of the video data and audio data.   An electronic apparatus comprising the information reproducing apparatus according to claim 1. An information reproducing apparatus according to any one of claims 6 to 8,
An electronic apparatus comprising: a host that instructs the information reproduction apparatus to start at least one of the video decoding process and the audio decoding process. Tuner,
The information reproducing apparatus according to any one of claims 6 to 8, wherein a transport stream from the tuner is supplied;
An electronic apparatus comprising: a host that instructs the information reproduction apparatus to start at least one of the video decoding process and the audio decoding process.

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