JP2008022229A - Imaging device drive circuit, imaging device driving method, and imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an imperfect transfer due to the amplitude reduction at start-up. <P>SOLUTION: A high and low driving voltages VH, VL are applied to a drive circuit 11 to generate two-phase clock signals H1/H2 of amplitudes depending on the HV and VL. A timing generator circuit 12 generates a timing pulse for indicating the starting period including one cycle of the two-phase clock signal H1/H2 starting from its re-activating time to its termination. Based on the timing pulse, a voltage control circuit 13 controls the VH and VL in the starting period to apply the drive voltage to the drive circuit 11 which does not invert the potential relation of the clock signals H1/H2 in this period. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an imaging element driving circuit, an imaging element driving method, and an imaging apparatus, and in particular, a register that sequentially transfers signals obtained by an imaging element of an imaging unit is driven using a two-phase clock signal supplied in opposite phases. The present invention relates to an imaging element driving circuit and an imaging element driving method, and an imaging apparatus having such an imaging element driving circuit.

  2. Description of the Related Art Conventionally, a CCD (Charge Coupled Device) has been widely used as one of imaging elements of an imaging apparatus such as a video camera. In the CCD, the signal charge of each pixel in the imaging area is read and transferred to the vertical register, and then transferred from the vertical register to the horizontal register provided at the end of the vertical register during the horizontal blanking period. In the horizontal scanning period, the signal charge transferred to the horizontal register is horizontally transferred to the charge detection unit, and converted into a signal voltage pixel by pixel by the charge detection unit. Such a horizontal register is driven using, for example, a two-phase clock signal.

A drive circuit that generates a two-phase clock signal for driving the horizontal register will be described.
FIG. 8 is a diagram showing a schematic configuration of a conventional drive circuit and its output waveform. (A) is a schematic block diagram of the conventional drive circuit, (B) has shown the output waveform.

  As shown in (A), the H1 / H2 driver 901 is applied with a high drive voltage VH and a low drive voltage VL as drive voltages defining the amplitude of the two-phase clock signal, and based on the clock signal XH1 / XH2. A two-phase clock signal H1 / H2 is generated.

  The two-phase clock signals H1 / H2 are fixed and stopped at the high potential and the low potential in the horizontal blanking period, respectively, and inversion is started at the start point of the horizontal scanning period. As a result, as shown in (B), a two-phase clock signal is generated that stops in the horizontal blanking period and changes the potential relationship to the opposite phase in the horizontal scanning period.

  Incidentally, the drive circuit is formed of a resonance circuit having a CCD horizontal drive frequency as a resonance frequency in order to reduce power consumption. In such a drive circuit, resonance does not occur at the beginning of the clock movement, so that the first-stage two-phase clock signal H1 / H2 has a problem that the effective amplitude 911 at the time of start-up decreases as shown in FIG. It was. In the drive circuit using the two-phase clock signal H1 / H2, the potential difference between H1 and H2 contributes to the transfer. Therefore, when the effective amplitude 911 at the start is small, the transfer electric field is not applied and the transfer is incomplete. . This incomplete transfer causes deterioration of image quality such as vertical stripes.

In view of this, a drive circuit has been proposed that performs a preparatory movement for filling the resonance circuit with energy without charge transfer (see, for example, Patent Document 1).
JP-A 63-265467 (FIG. 1)

  Conventionally, a two-phase clock signal is generated in the vicinity of the first transfer stage in order to suppress a decrease in effective amplitude of the first two-phase clock signal activated by switching from the horizontal blanking period (stop period) to the horizontal scanning period. Control has been performed to increase the drive voltage.

  FIG. 9 is a diagram showing a schematic configuration of a conventional drive circuit that takes measures against a decrease in effective amplitude and its output waveform. (A) is a schematic block diagram of a conventional drive circuit that takes measures against a decrease in effective amplitude, and (B) shows its output waveform. The same elements as those in FIG.

  The H1 / H2 driver 901 shown in (A) is the same as that shown in FIG. Here, as a countermeasure against a decrease in effective amplitude, at the start of the horizontal scanning period, the high level drive voltage VH supplied to the H1 / H2 driver 901 is boosted by an external power source (not shown) and the low level drive voltage VL is lowered. Thereby, as shown to (B), the amplitude fall of the effective amplitude 921 at the time of starting is suppressed. Note that only the high drive voltage VH may be boosted.

  However, in such a configuration, in order to suppress a decrease in the effective amplitude 921 at the time of starting, a separate high drive voltage must be prepared, which is unreasonable. In particular, the H1 / H2 driver 901 is designed with a minimum withstand voltage for high-speed driving. Therefore, in order to apply a high drive voltage separately, there is a problem that a withstand voltage higher than necessary is required for the original transfer.

  In addition, for example, as described in Patent Document 1, in a circuit configuration in which a coupling resistor is inserted between a resonance circuit and a drive circuit, not only one period at the start of the problem but also the output of the clock driver is It is always supplied to the horizontal register via a coupling resistor. For this reason, the amplitude of the supplied signal generally decreases, which is not preferable.

  The present invention has been made in view of the above points, an image sensor driving circuit and an image sensor driving method capable of preventing incomplete transfer due to a decrease in the amplitude of the two-phase clock signal at the start, and this An object of the present invention is to provide an imaging apparatus equipped with an imaging element driving circuit.

  In the present invention, in order to solve the above-described problem, in an image sensor driving circuit for driving a register for sequentially transferring signals obtained by the image sensor of the imaging unit using two-phase clock signals supplied in opposite phases, An image sensor driving circuit is provided that includes a timing generation circuit that notifies a predetermined period and a voltage control circuit that controls a voltage applied to a driving signal generation circuit that generates a two-phase clock signal.

  The two-phase clock signal has a stop period in which the respective potentials are fixed in accordance with the operation of the register and a drive period in which the potentials are inverted in opposite phases. In the driving period, the potential relationship is switched every time inversion occurs. When the two-phase clock signal is started from the stop period, the timing generation circuit generates a timing pulse for notifying the start period including the first stage of the two-phase clock signal. Based on the timing pulse generated by the timing generation circuit, the voltage control circuit controls the drive voltage that defines the amplitude of the two-phase clock signal to a value that does not invert the potential relationship of the two-phase clock signal during the start period.

  According to such an image sensor driving circuit, when the two-phase clock signal that repeats the stop period and the drive period is started from the stop period, the timing generation circuit includes a start period including the first stage of the two-phase clock signal. A timing pulse for notifying is generated. The voltage control circuit controls the drive voltage that defines the amplitude of the two-phase clock signal to a value that does not invert the potential relationship of the two-phase clock signal based on the timing pulse generated by the timing generation circuit, This is applied to a drive signal generation circuit that generates a two-phase clock signal. As a result, a transfer electric field necessary for transferring the signal charge is not generated during the start-up period.

  In the present invention, when the two-phase clock signal for driving the image sensor is started from the stop period, the signal charge is not transferred during the start period in which the movement starts and the resonance does not occur and the transfer electric field becomes insufficient. The drive voltage is controlled as follows. Therefore, the drive voltage is controlled so that a drive voltage that does not invert the potential relationship between the two-phase clock signals is applied to the drive signal circuit during the start-up period including at least the first stage of the two-phase clock signal. Thereby, during the start-up period, a transfer electric field necessary for signal charge transfer does not occur, and charge transfer does not occur. As a result, it is possible to suppress incomplete transfer in which only a part of the signal charge is transferred due to the decrease in the amplitude of the two-phase clock signal, and as a result, it is possible to prevent deterioration in image quality.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, the concept of the invention applied to the embodiment will be described, and then the specific contents of the embodiment will be described.
FIG. 1 is a conceptual diagram of the invention applied to the embodiment.

  An image sensor driving circuit according to the present invention includes a driving signal generation circuit (hereinafter referred to as a drive circuit) 11 that generates a two-phase clock signal, a timing generation circuit 12 that notifies a start period, and a driving voltage applied to the drive circuit 11. And a two-phase clock signal H1 / H2 that is generated is output as a drive signal for a register that sequentially transfers signals obtained by the image sensor.

  The drive circuit 11 receives a clock signal XH1 / XH2 corresponding to a desired clock frequency, and generates a high-level driving voltage VH to be applied and a two-phase clock signal H1 / H2 having a voltage amplitude corresponding to the low-level driving voltage VL. . This two-phase clock signal H1 / H2 is used as, for example, a driving signal for a CCD horizontal register, and in accordance with the operation of the register, as a horizontal blanking period, a stop period for fixing the potentials H1 and H2, and a horizontal scanning period. A driving period in which the potential relationship between H1 and H2 is inverted in reverse phase is repeated. The drive circuit 11 is composed of an inductance connected in parallel with a CCD represented by a predetermined load capacity and a capacitor having a predetermined load capacity, and constitutes a parallel resonance circuit having a drive frequency of the CCD horizontal register as a resonance frequency. To do. This parallel resonant circuit configuration is well known, and is disclosed in, for example, Japanese Patent Application Laid-Open No. 5-122625 “Drive Circuit for Solid-State Imaging Device” by the same applicant as the present application.

  The timing generation circuit 12 includes a start period including a first-stage drive waveform that is generated first after the two-phase clock signal H1 / H2 is shifted from the stop period to the drive period and the two-phase clock signal H1 / H2 is started from the stop state. A timing pulse for notifying is generated. The timing generation circuit 12 is realized by, for example, a timing generator that generates timing signals such as start and end of a stop period and a drive period, and XH1 / XH2 as one of its functions. Alternatively, a circuit separate from the timing generator may be used to generate a timing pulse by detecting a change in a timing signal generated by the timing generator.

The voltage control circuit 13 receives a drive power supply (a higher drive power supply V ₀ H on the higher side, a lower drive power supply V ₀ L on the lower side) and is applied to the drive circuit 11 (a higher drive on the higher side with a higher potential). The voltage VH and the low potential driving voltage VL having a low potential are controlled. As described above, the two-phase clock signal H1 / H2 generated by the drive circuit 11 does not resonate at the beginning of the movement at which the signal starts inversion, and the driving of the first stage is performed when the driving voltage is the same as in the steady state. The effective amplitude of the waveform decreases. Therefore, the voltage control circuit 13 performs voltage control so that the potential difference between the high drive voltage VH and the low drive voltage VL applied to the drive circuit 11 is small during the start period in which the first drive waveform is generated. The potential relationship of the phase clock signal is not reversed. When the start-up period ends, the voltage control circuit 13 applies the high level drive power supply V ₀ H and the low level drive power supply V ₀ L to the drive circuit 11. As a result, as shown in the waveform 13a of the high-level drive voltage VH, the high-level drive voltage VH decreases only during the start period 23. Similarly, as shown in the waveform 13 b of the low drive voltage VL, the low drive voltage VL rises only during the start period 23.

  As described above, the high-level driving voltage VH and the low-level driving voltage VL change, so that the potential relationship between H1 and H2 forming the two-phase clock signal is not reversed in the starting period. At this time, the drive waveforms of H1 and H2 do not intersect. Although the signal charge transfer and the relationship between H1 and H2 will be described later, if the drive waveforms of H1 and H2 do not intersect, the transfer electric field necessary for the signal charge transfer is not applied and the transfer does not occur.

  Since energy for starting resonance is charged during the start-up period, sufficient amplitude can be obtained when the high-level drive voltage VH and the low-level drive voltage VL are returned to the steady state after the start-up period ends. It has become.

The operation of the image sensor driving circuit having such a configuration will be described.
When the two-phase clock signal is started from the stop period, the timing generation circuit 12 generates a timing pulse for notifying the start period including the period from the start to the generation of the first stage signal, and notifies the voltage control circuit 13 of the timing pulse. To do. Based on the timing pulse, the voltage control circuit 13 lowers the high drive voltage VH applied to the drive circuit 11 at the start of the starting period, and raises the low drive voltage VL to form H1 that forms a two-phase clock signal. The potential relationship of H2 is not reversed. Then, based on the timing pulse, at the end of the starting period, the high-level driving voltage VH and the low-level driving voltage VL applied to the drive circuit 11 are based on the high-level driving power supply V ₀ H and the low-level driving power supply V ₀ L. Return to.

The two-phase clock signal H1 / H2 generated by the above operation will be described. FIG. 2 is a diagram illustrating an example of a driving waveform of a two-phase clock signal.
The two-phase clock signals H1 / H2 are fixed at a high potential or a low potential in the stop period 21, respectively. In the illustrated example, H1 is fixed on the high-order side and H2 is fixed on the low-order side.

  Here, when the stop period 21 ends and the drive period 22 starts, the two-phase clock signals H1 / H2 each start to invert. At this time, in the start-up period 23 including the period in which the first two-phase clock signal is generated, the voltage control circuit 13 steps down the high-side (H2) drive voltage VH and the low-side (H1) drive voltage VL is Boosted. Since resonance does not occur at the beginning of movement, the amplitudes of H1 and H2 decrease. At this time, the high drive voltage VH is lowered by the voltage control circuit 13 and the low drive voltage VL is raised, whereby the amplitudes of H1 and H2 are lowered, and the drive waveform of H1 and the drive waveform of H2 intersect. Disappear. That is, the signal level relationship between H1 and H2 is not reversed.

  At the end of the start period 23, the high level drive voltage VH and the low level drive voltage VL are returned to the steady state. At this time, since sufficient resonance is applied, a two-phase clock signal H1 / H2 having an amplitude capable of securing a sufficient transfer electric field is generated.

  As described above, according to the present invention, the two-phase clock signal that drives the register is activated at a high level that determines the amplitude of the two-phase clock signal during the start-up period from the start of the stop period until the first stage signal is generated. The potential difference between the driving voltage and the lower driving voltage is controlled so that the inversion of the potential relationship of the two-phase clock signal (that is, the intersection of the driving waveforms) does not occur. In the register driven by this drive signal, the transfer electric field generated by the inversion of the signal level relationship of the two-phase clock signal is not secured in the initial two-phase clock signal, so that no signal charge is transferred. As a result, incomplete transfer can be suppressed, and as a result, deterioration in image quality can be prevented.

  In addition, since a higher driving voltage is not required than in a steady state, it is not necessary to prepare a higher driving voltage separately. Furthermore, in the driver, it is not possible to apply a voltage higher than the amplitude voltage in the steady state, so that an excessive breakdown voltage is not necessary, and the driver over quality can be avoided.

Here, signal charge transfer in the register will be described. FIG. 3 is a diagram showing a waveform of a two-phase clock signal for driving a two-phase CCD.
As described above, when driving a two-phase register, the two-phase clock signals H1 and H2 invert the potential relationship in the opposite phase. Hereinafter, the case where H1 is Hi level and H2 is Lo level is referred to as [1], and the case where H1 is Lo level and H2 is Hi level is referred to as [2].

FIG. 4 is a diagram showing transfer of signal charges of the two-phase CCD. [1] and [2] indicate the signal level states of FIG. The hatched portion in the figure indicates the signal charge to be transferred.
In the two-phase CCD, an accumulation part and a transfer part are formed in each electrode, and signal charges are accumulated in the accumulation part. Moreover, H1 or H2 is applied to every other electrode arranged. That is, a reverse phase clock signal is applied to adjacent electrodes.

  In this state, when the two-phase clock signals having opposite phases shown in FIG. 3 are given, the signal charges are transferred in the left direction of the figure. In the state [1] where H1 is at the Hi level and H2 is at the Lo level, signal charges are accumulated in the accumulation units 50a, 50b, and 50c. When the signal level is reversed at the next [2], for example, the signal charge of the storage unit 50a moves to the storage unit 51a adjacent to the left. Similarly, the signal charge in the storage unit 50b sequentially moves to the left as in the storage unit 51b adjacent to the left.

  Here, when the potential difference between H1 and H2 is small and the potential relationship between H1 and H2 does not reverse, the potential relationship between adjacent electrodes does not change. Therefore, the signal charge does not move to the adjacent electrode.

As described above, if the potential relationship of the two-phase clock signal is not inverted (the driving waveform does not intersect on the waveform), the signal charge accumulated in the accumulation unit is not transferred.
Hereinafter, embodiments will be described in detail with reference to the drawings.

FIG. 5 is a diagram showing a circuit configuration of the image sensor driving circuit according to the embodiment of the present invention. The same parts as those in FIG.
The image sensor driving circuit according to the embodiment of the present invention includes a drive circuit 11, a pulse A (PA) generated by a timing generation circuit (not shown), and a pulse B (PB) that is an inverted signal of the pulse A (PA). Correspondingly, it has FETs (Field Effect Transistors) Q1, Q2, Q4, Q5 constituting a switching circuit for switching the drive voltage, and resistors R1, R2, R3 and bipolar transistors Q3, Q6 for generating a voltage during the starting period. .

  In the P-channel FETs Q1 and Q2 for switching the high-level drive voltage VH of the drive circuit 11, the gate of Q1 is connected to PB and the gate of Q2 is connected to PA. Similarly, Q4 and Q5 of the N-channel FET that switches the low drive voltage VL of the drive circuit 11 have the gate of Q4 connected to PB and the gate of Q5 connected to PA. Therefore, Q1 is turned on, Q2 is turned off, Q4 is turned off, and Q5 is turned on except during the start-up period in which PA is at Hi level and PB is at Lo level. In the start-up period in which PA is Lo level and PB is Hi level, Q1 is off, Q2 is on, Q4 is on, and Q5 is off.

The resistors R1, R2, and R3 are connected in series between a high level power source that supplies the driver Hi level voltage V ₀ H and a low level power source that supplies the driver Lo level voltage V ₀ L. Further, the base of the bipolar transistor Q3 is connected between the resistor R1 and the resistor R2, and an emitter follower is configured. Similarly, the base of the bipolar transistor Q6 is connected between the resistor R2 and the resistor R3 to constitute an emitter follower. The driver Hi level voltage V ₀ H and the driver Lo level voltage V ₀ L are divided by resistors R1, R2, and R3, and the voltage between the resistors R1 and R2 is between V1 and between the resistors R2 and R3. When the voltage is _{V2, V 0 H>V1>}V2> V 0 L relation holds. V1 is taken out by the emitter follower formed by Q3 when Q1 is off and Q2 is on, and is applied to the drive circuit 11 as a high-level drive voltage. Similarly, when Q4 is on and Q5 is off, V2 is taken out by the emitter follower formed by Q6 and applied to the drive circuit 11 as a low-level drive voltage.

Here, the pulse PA / PB for notifying the start period will be described. FIG. 6 is a diagram showing the generation timing of a pulse for notifying the start period according to the embodiment of the present invention.
When the two-phase clock signal H1 / H2 is started from the stop period 21 by the timing generator that generates various timing signals such as the stop period 21 and the drive period 22, the signal level of the pulse PA / PB is inverted, and the start period 23 It is restored with the end of. The pulse PA is normally at the Lo level and is at the Hi level only during the start period 23. The pulse PB is normally at the Hi level and is at the Lo level only during the start period 23.

The start period 23 is set to an arbitrary period including at least the start of the two-phase clock signal and the end of the first-stage two-phase clock signal.
Returning to FIG. 5, the operation of the image sensor driving circuit according to the embodiment of the present invention will be described.

In the stop period 21, as shown in FIG. 6, PA is at the Hi level and PB is at the Lo level. At this time, Q1 is turned on, Q2 is turned off, Q4 is turned off, Q5 is turned on, and the driver Hi level voltage V ₀ H and the driver Lo level voltage V ₀ L are applied to the drive circuit 11.

When the two-phase clock signal H1 / H2 starts to move from the stop period 21 to the driving period 22, during the start-up period 23 including the first stage of the two-phase clock signal H1 / H2, PA is at the Lo level and PB is at the Hi level. Invert. At this time, Q1 is turned off, Q2 is turned on, and the high-level driving voltage VH applied to the drive circuit 11 is switched from V ₀ H to the starting voltage V1. Also, Q4 is turned on and Q5 is turned off. At this time, similarly, the lower driving voltage VL is switched from V ₀ L to the starting voltage V2. Since the relationship of V ₀ H> V 1> V 2> V ₀ L is established by the resistors R 1, R 2 and R 3, the high level drive voltage VH applied to the drive circuit 11 is lower than the original VH. On the other hand, the lower driving voltage VL becomes higher than the original VL. The first-stage two-phase clock signal has a smaller amplitude than the two-phase clock signal H1 / H2 after the resonance is applied, and further reduces the potential difference between the drive voltages VH and VL, thereby reducing the two-phase clock signal H1 / H2. The driving waveforms of H2 do not cross each other, and signal charge transfer does not occur.

Resonance is also sufficient during the start-up period 23. When the start period 23 ends, the pulse PA returns to the Hi level and the PB returns to the Lo level. At this time, Q1 is turned on, Q2 is turned off, Q4 is turned off, Q5 is turned on, and the driver Hi level voltage V ₀ H and the driver Lo level voltage V ₀ L are applied to the drive circuit 11. Therefore, after the start period 23 ends, the two-phase clock signal H1 / H2 having an amplitude sufficient for a complete transfer electric field is generated.

In this way, the drive voltage VH / VL applied to the drive circuit 11 is in a relationship of the original drive voltage V ₀ H / V ₀ L and V ₀ H>V1>V2> V ₀ L during the start-up period. Switch to a certain starting voltage V1 / V2. This makes it possible to reduce the amplitude of the two-phase clock signal to the extent that signal charge transfer does not occur, so that incomplete signal transfer does not occur in the starting period 23. As a result, it is possible to prevent image quality deterioration due to a decrease in the amplitude of the two-phase clock signal.

Further, since the starting voltage V1 / V2 is generated from the drive voltage V ₀ H / V ₀ L, it is not necessary to separately provide a new power source. Further, since the drive circuit 11 is not applied with a voltage higher than the original drive voltage V ₀ H / V ₀ L, the drive circuit 11 only needs to have a withstand voltage necessary for the original transfer. There is also an advantage that the over quality of can be avoided.

  Further, the path passing through Q3 and Q6 for generating the starting voltage V1 / V2 is effective only in the starting period 23, and after the starting period 23 is finished, this path is not used, and thus adversely affects the circuit during normal operation. There is also an effect that there is nothing.

Next, an image pickup apparatus including such an image pickup element driving circuit will be described.
FIG. 7 is a block diagram illustrating a configuration of the imaging apparatus according to the embodiment of the present invention.
An imaging apparatus according to an embodiment of the present invention includes an imaging element 102, a driver 101 that drives the imaging element 102, a timing generator (TG in the figure) 103 that generates driving timing of the driver 101, and an optical signal incident on the imaging element 102. A pre-amplifier 105 that extracts the signal charge of the imaging element 102, and a signal processing unit 106 that generates a video output signal by processing the output signal of the pre-amplifier 105.

  The image sensor 102 is a CCD image sensor, and includes a photodiode that performs photoelectric conversion and charge accumulation, and a vertical register and a horizontal register that perform charge transfer. The driver 101 is a circuit that generates a two-phase clock signal for driving the image sensor 102, and the image sensor drive circuit according to the embodiment of the present invention is applied thereto. The timing generator 103 provides a driving signal and various timing signals to the driver 101. The timing generator 103 also generates a timing pulse that notifies the start period of the present embodiment. The lens 104 forms an optical image of the subject on the imaging surface of the image sensor 102. The preamplifier 105 takes out the signal charge transferred by the image sensor 102 in accordance with the drive signal of the driver 101 and outputs it to the signal processing unit 106. The signal processing unit 106 processes the signal charge detected by the image sensor 102 input via the preamplifier 105, and generates an image signal (video output).

  According to such an imaging apparatus, signal charges corresponding to the subject image formed on the imaging surface of the imaging element 102 by the lens 104 are generated in the imaging element 102. The signal charge accumulated in the image sensor 102 is transferred according to the two-phase clock signal generated by the driver 101 that generates the drive signal according to the timing signal generated by the timing generator 103, taken out by the preamplifier 105, and subjected to signal processing. Sent to the unit 106.

  The driver 101 controls the potential difference between the high and low drive voltages that determine the amplitude of the two-phase clock signal during the start-up period until the two-phase clock signal is started from the stop state and becomes a stable amplitude signal. In addition, inversion of the potential relationship of the two-phase clock signal is prevented from occurring. Thereby, it is possible to prevent incomplete signal charge transfer in which only part of the signal charge is transferred. As a result, in the imaging apparatus, it is possible to prevent deterioration in the image quality of the video output generated via the signal processing unit 106.

It is a conceptual diagram of the invention applied to embodiment. It is the figure which showed an example of the drive waveform of a two-phase clock signal. It is the figure which showed the waveform of the 2 phase clock signal which drives 2 phase CCD. It is the figure which showed transfer of the signal charge of 2 phase CCD. It is a figure showing circuit composition of an image sensor drive circuit of an embodiment of the invention. It is the figure which showed the generation | occurrence | production timing of the pulse which notifies the starting period of embodiment of this invention. It is the block diagram which showed the structure of the imaging device of embodiment of this invention. It is the figure which showed schematic structure and the output waveform of the conventional drive circuit. It is the figure which showed schematic structure and the output waveform of the drive circuit which performed the countermeasure of the conventional effective amplitude fall.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Drive circuit (drive signal generation circuit), 12 ... Timing generation circuit, 13 ... Voltage control circuit, H1 / H2 ... Two-phase clock signal, VH ... High drive voltage, VL ..Low drive voltage

Claims (5)

In an image sensor driving circuit for driving a register for sequentially transferring signals obtained by an image sensor of an image pickup unit using a two-phase clock signal supplied in mutually opposite phases,
A timing generation circuit for generating a timing pulse for notifying a starting period including a first stage of the two-phase clock signal when starting the two-phase clock signal from a stop period;
Based on the timing pulse generated by the timing generation circuit, the driving voltage defining the amplitude of the two-phase clock signal is controlled to a value that does not invert the potential relationship of the two-phase clock signal in the start period. A voltage control circuit applied to a drive signal generation circuit for generating the two-phase clock signal;
An image sensor driving circuit comprising: The voltage control circuit includes:
A starting voltage generating circuit for generating a first starting voltage lower than a constant high drive voltage and a second starting voltage higher than a steady low driving voltage;
A switching circuit that switches a supply voltage between the first start-up voltage and the second start-up voltage during the start-up period, and otherwise supplies a supply voltage as the high-level drive voltage and the low-level drive voltage;
The image pickup device driving circuit according to claim 1, wherein: The starting voltage generating circuit is:
A plurality of resistors arranged in series between a high-level power source that generates the high-level driving voltage and a low-level power source that generates the low-level driving voltage;
A base is connected between the plurality of resistors, and a first transistor for extracting the first start-up voltage having a lower potential than the high-level drive voltage divided by the plurality of resistors and the first start-up voltage A second transistor that extracts the second starting voltage lower and higher than the lower drive voltage;
The imaging element driving circuit according to claim 2, wherein: In an imaging element driving method for driving a register for sequentially transferring signals obtained by an imaging element of an imaging unit using a two-phase clock signal supplied in opposite phases to each other,
When the timing generator circuit starts the two-phase clock signal from a stop period, it generates a timing pulse for notifying the start period including the first stage of the two-phase clock signal,
Based on the timing pulse generated by the timing generation circuit, the voltage control circuit does not reverse the potential relationship of the two-phase clock signal with the drive voltage that defines the amplitude of the two-phase clock signal during the start period. Controlled to a value and applied to a drive signal generation circuit for generating the two-phase clock signal,
An image pickup element driving method comprising a procedure. In an imaging apparatus in which a register for sequentially transferring signals obtained by an imaging element of an imaging unit is driven using a two-phase clock signal supplied in opposite phases to each other,
An image sensor that converts and holds an optical image of a subject incident on the imaging surface into a signal charge and sequentially transfers the signal charge according to the two-phase clock signal;
A timing generation circuit for generating a timing pulse for notifying a start-up period including a first stage of the two-phase clock signal when the two-phase clock signal is started from a stop period;
Based on the timing pulse generated by the timing generation circuit, the driving voltage defining the amplitude of the two-phase clock signal is controlled to a value that does not invert the potential relationship of the two-phase clock signal in the start period. A voltage control circuit applied to a drive signal generation circuit for generating the two-phase clock signal;
An imaging device comprising:

Images