JP2008021825A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor device and a manufacturing method thereof which has a highly accurate multilayer Cu wiring structure. <P>SOLUTION: In the manufacturing method of a semiconductor device, a buried material 13 is formed in a via pattern 41, and after applying successively a BARC film 9 and a resist 10 onto a TEOS film 6 and the buried material 13, the resist 10 is patterned. Hereupon, when a rework is generated in the patterning process of the BARC film 9 and the resist 10; the resist 10, the BARC film 9, and the buried material 13 are subjected to ashing. Further, the buried material 13 hardened when performing the ashing or the polymer, etc. generated when performing the ashing is removed by a wet processing. Thereafter, the buried material 13, the BARC film 9, and resist 10 are formed in the foregoing way. Even though performing the wet processing when the rework is generated, a wet liquid used in the wet processing does not penetrate into a Cu wiring 3 since a SiCO film 22 is formed between the buried material 13 and the Cu wiring 3. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a multilayer Cu (copper) wiring structure and a manufacturing method thereof.

  Conventionally, in a semiconductor device having a multilayer Cu wiring structure, a Cu wiring structure is obtained by a (dual) damascene method. As a Cu wiring structure using the damascene method, there is a structure disclosed in Patent Document 1, for example.

JP 2004-319616 A

  However, in the conventional multilayer Cu wiring structure, when a pin hole or the like occurs in the liner layer (underlying insulating film) formed on the lower layer Cu wiring during the etching for forming the via pattern for forming the via hole, There is a problem in that the exposed lower layer copper wiring is melted by wet processing (water washing) at the time of reworking of the upper layer Cu wiring wiring process to be executed, so that an accurate multilayer Cu wiring structure cannot be realized.

  The present invention has been made to solve the above problems, and an object thereof is to obtain a semiconductor device having a multilayer Cu wiring structure with high accuracy and a method for manufacturing the same.

  According to a first aspect of the present invention, there is provided a semiconductor device having a multilayer copper wiring structure including a lower layer copper wiring and an upper layer copper wiring portion formed on the lower layer copper wiring and having a wiring portion and a plug portion. A base insulating film formed on the lower copper wiring, an interlayer insulating film formed on the base insulating film, the base insulating film and the interlayer insulating film, and on the surface of the lower copper wiring The upper copper wiring part formed in contact with the auxiliary insulating film formed at least between the plug part of the upper copper wiring part and the interlayer insulating film.

  According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a multilayer copper wiring structure including a lower copper wiring and an upper copper wiring portion formed on the lower copper wiring and having a wiring portion and a plug portion. A method of manufacturing a semiconductor device, comprising: (a) forming the lower copper wiring; (b) forming a base insulating film on a region including the lower copper wiring; and (c) the base Forming an interlayer insulating film on the insulating film; (d) selectively forming a via pattern penetrating at least the interlayer insulating film; and (e) forming an auxiliary insulating film on the bottom and side surfaces of the via pattern. Forming (f) filling the via pattern with the filling material via the auxiliary insulating film; and (g) selectively removing the interlayer insulating film, the filling material and the auxiliary insulating film. The via pattern including the via pattern A step of selectively forming a wiring trench in an upper layer portion of the interlayer insulating film with a wider formation width than a pattern; (h) removing the filling material remaining in the via pattern; and (i) the via pattern Removing at least the auxiliary insulating film present on the bottom surface to expose the surface of the lower copper wiring to obtain a via hole; and (j) contacting the surface of the lower copper wiring inside the via hole and the wiring groove. And selectively forming the upper layer copper wiring part, wherein the upper layer copper wiring part formed in the via hole is defined as the plug part and is formed in the wiring groove Is defined as the wiring portion, and after the step (j) is performed, the auxiliary insulating film remains at least between the interlayer insulating film and the plug portion of the upper copper wiring.

  In the semiconductor device according to the first aspect of the present invention, the auxiliary insulating film formed at least between the plug portion of the upper copper wiring portion and the interlayer insulating film is formed after forming the via pattern for forming the plug portion of the upper copper wiring portion. It can also be formed on the bottom surface of the via pattern for forming the plug portion.

  Therefore, in the stage from the formation of the via pattern to the wiring groove forming process for forming the wiring portion of the upper layer copper wiring portion, the lower insulating layer lower copper wiring is protected by the presence of the protective insulating film on the bottom surface of the via pattern. Therefore, there is an effect that an accurate multilayer copper wiring structure can be obtained.

  In the semiconductor device manufacturing method according to the sixth aspect of the present invention, the step (e) is also formed on the bottom surface of the via pattern for forming the plug portion of the upper copper wiring portion.

  As a result, since the protective insulating film is present on the bottom surface of the via pattern in the stage from step (e) to step (i), the underlying lower layer copper wiring can be protected. The copper wiring structure can be obtained.

<Principle of the invention>
(Construction)
FIG. 18 is a cross-sectional view showing a multilayer Cu wiring structure (two layers in FIG. 18) as a prerequisite technology. As shown in the figure, an oxide film 2 is formed on a Si substrate 1, and a Cu wiring 3 that selectively becomes a lower Cu wiring is formed in an upper layer portion of the oxide film 2. Electrical connection is made with an active region (not shown) of the Si substrate 1 through a contact plug 31 that penetrates the oxide film 2 and reaches the surface of the Si substrate 1.

  A SiCN / SiCO film 4 (SiCN film is the lower layer and SiCO film is the upper layer) is formed on the oxide film 2 including the Cu wiring 3, and the SiOC film 5 is formed on the SiCN / SiCO film 4. An upper layer Cu wiring portion 25 is formed through the SiOC film 5 and the SiCN / SiCO film 4 and reaching a part of the surface of the Cu wiring 3.

  The upper layer Cu wiring part 25 includes an upper layer wiring part 25a and a lower layer plug part 25b, and the wiring part 25a is formed with a wider width than the plug part 25b. The upper Cu wiring portion 25 includes a barrier (metal) layer 15 and a Cu wiring 20. The barrier layer 15 is formed along the bottom and side surfaces of the upper Cu wiring portion 25, and the Cu wiring 20 is formed in the barrier layer 15. . Therefore, the Cu wiring 3 and the Cu wiring 20 are electrically connected via the barrier layer 15 formed on the surface of the Cu wiring 3.

  As described above, the multilayer Cu wiring structure as the base technology is formed by the Cu wiring 3 and the upper Cu wiring portion 25.

  However, due to the formation of pinholes in the SiCN / SiCO film 4 in the manufacturing process of the multilayer Cu wiring structure shown in FIG. 18, a defect 17 occurs in the Cu wiring 3 as shown in FIG. In addition, the upper layer Cu wiring part 26 (wiring part 26a, plug part 26b) composed of the barrier layer 16 and the Cu wiring 21 is also formed in the defect part 17, and there is a problem that a wiring defect occurs.

(Production method)
20 to 25 are cross-sectional views showing a multilayer Cu wiring manufacturing method as a prerequisite technique for explaining the cause of the above-described problem (the structure shown in FIG. 19).

  As shown in FIG. 20, an oxide film 2 is formed on the Si substrate 1, a Cu wiring 3 that selectively becomes a lower Cu wiring is formed in an upper layer portion of the oxide film 2, and penetrates the oxide film 2 below the wiring 3 Thus, a structure in which the contact plug 31 reaching the surface of the Si substrate 1 is formed is obtained.

  Then, a SiCN / SiCO film 4 is deposited on the oxide film 2 including the Cu wiring 3 by a CVD method, and a SiOC film 5 is further deposited on the SiCN / SiCO film 4 by a CVD method. A TEOS film 6 is deposited thereon by CVD.

  Then, as shown in FIG. 21, a BARC (Bottom Anti-Reflection Coating) film 7 is formed on the TEOS film 6 and a via resist 8 is formed on the BARC film 7. After patterning (by exposure and development processing), using the patterned resist 8 as a mask, the BARC film 7, TEOS film 6, and SiOC film 5 are etched to obtain a via pattern 41.

  At this time, if the film thickness of the SiOC film 5 is reduced and the film thickness of the SiCN / SiCO film 4 is reduced, or the film quality is locally in a part of the SiCN / SiCO film 4, the etching selectivity is different from other regions. A small pinhole 51 is generated at the corresponding location when the current is low.

  Next, as shown in FIG. 22, the BARC film 7 and the resist 8 are removed by ashing (O 2 plasma) treatment. At this time, although the pinhole 51 exists, the Cu wiring 3 under the via pattern 41 is not dissolved because the wet process using the wet liquid is not applied.

  Next, as shown in FIG. 23, the filling material 13 made of an organic material or the like is applied and etched back to leave the filling material 13 in the via pattern 41. Next, a wiring BARC film 9 is applied on the TEOS film 6 and the filling material 13, and further, a wiring resist 10 is applied on the BARC film 9. Thereafter, the resist 10 is exposed and developed and patterned.

  Usually, since the wet process is not applied at this point, the Cu wiring 3 under the pinhole 51 is not etched. However, when rework occurs in the lithographic process (patterning process) of the BARC film 9 and the resist 10 due to a dimensional defect or the like, FIG. The process shown in FIG. 23 needs to be performed again.

  In order to return to the state shown in FIG. 22, the resist 10, the BARC film 9, and the burying material 13 are ashed, and in addition to the burying material 13 hardened at the time of ashing, a wet process is performed to remove the polymer generated at the time of ashing. After that, as described above, the structure shown in FIG. 23 can be obtained again through the steps shown in FIG. 23 (formation of the filling material 13 by etching back, formation of the BARC film 9 and the resist 10, and patterning of the resist 10). it can.

  Therefore, as shown in FIG. 23, when wet processing is performed on the filling material 13 at the time of rework, the wet liquid penetrates into the pinhole 51, and a part of the Cu wiring 3 is removed by etching, so that the defect portion 17 is formed.

  Next, as shown in FIG. 24, the BARC film 9, the TEOS film 6, the filling material 13, and a part of the SiOC film 5 are selectively removed by dry etching using the patterned resist 10 as a mask. A wiring groove 46 is formed in the upper layer portion of the film 5. The wiring groove 46 includes the via pattern 41 and is formed with a wider formation width than the via pattern 41. Thereafter, the resist 10, the BARC film 9, and the remaining filling material 13 are removed by ashing, and then the TEOS film 6 on the SiOC film 5 and the SiCN / SiCO film 4 under the via pattern 41 are removed by liner etching. As a result, the remaining portion of the via pattern 41 located under the wiring groove 46 becomes a via hole 47.

  Then, as shown in FIG. 25, the barrier layer 16 is formed by sputtering, and the Cu wiring 21 is deposited by plating.

  Finally, annealing is performed, and unnecessary barrier layer 16 and Cu wiring 21 are removed by CMP (Chemical Mechanical Polishing) processing to obtain the structure shown in FIG.

  As described above, in the multi-layer Cu wiring process as the base technology, when a pinhole 51 is generated in the SiCN / SiCO film 4, a part of the Cu wiring 3 under the SiCN / SiCO film 4 is removed during the rework of the lithographic process, resulting in a defect. There is a problem that the portion 17 is generated and the electrical characteristics of the wiring deteriorate. The present invention is intended to solve this problem.

<Embodiment 1>
(Construction)
1 is a cross-sectional view showing a multilayer Cu wiring structure (two layers in FIG. 1) in a semiconductor device according to a first embodiment of the present invention. As shown in the figure, an oxide film 2 is formed on a Si substrate 1, and a Cu wiring 3 that selectively becomes a lower Cu wiring is formed in an upper layer portion of the oxide film 2. The Cu wiring 3 is located below the Cu wiring 3. An active region (such as a source / drain region of a MOS transistor; not shown in FIG. 1) formed on the surface of the Si substrate 1 through a contact plug 31 that reaches the surface of the Si substrate 1 through the oxide film 2 And electrical connection.

  A SiCN / SiCO film 4 as a base insulating film (liner film) is formed on the oxide film 2 including the Cu wiring 3, and a SiOC film 5 as an interlayer insulating film is formed on the SiCN / SiCO film 4. An upper layer Cu wiring portion 18 is formed by penetrating through the SiOC film 5 and the SiCN / SiCO film 4 and reaching a part of the surface of the Cu wiring 3.

  The upper layer Cu wiring part 18 includes an upper layer wiring part 18a and a lower layer plug part 18b, and the wiring part 18a is formed with a wider width than the plug part 18b. The upper Cu wiring portion 18 includes a barrier (metal) layer 11 and a Cu wiring 12. The barrier layer 11 is formed along the bottom and side surfaces of the upper Cu wiring portion 18, and the Cu wiring 12 is formed in the barrier layer 11. . Therefore, the Cu wiring 3 and the Cu wiring 12 are electrically connected by the barrier layer 11 formed on the surface of the Cu wiring 3.

  Further, an SiCO film 22 as an auxiliary insulating film is interposed between the side surface of the plug portion 18 b and the SiCN / SiCO film 4 and the SiOC film 5. As described above, the multilayer Cu wiring structure of the first embodiment is formed by the Cu wiring 3 and the upper Cu wiring portion 18, and the side surface of the plug portion 18 b of the upper Cu wiring portion 18 and the SiOC film 5 and the SiCN / SiCO film 4. A structure having a SiCO film 22 in between is exhibited.

(Production method)
2 to 8 are cross-sectional views showing a method for manufacturing a multilayer Cu wiring structure in the semiconductor device of the first embodiment. Hereinafter, the method for forming the multilayer Cu wiring structure of the first embodiment will be described with reference to these drawings.

  As shown in FIG. 2, an oxide film 2 is formed on the Si substrate 1, a Cu wiring 3 that selectively becomes a lower Cu wiring is formed in an upper layer portion of the oxide film 2, and penetrates the oxide film 2 below the wiring 3. Thus, a structure in which the contact plug 31 reaching the surface of the Si substrate 1 is formed is obtained.

  Then, a SiCN / SiCO film 4 is deposited on the oxide film 2 including the Cu wiring 3 by a CVD method, and a SiOC film 5 is further deposited on the SiCN / SiCO film 4 by a CVD method. A TEOS film 6 is deposited thereon by CVD.

  Then, as shown in FIG. 3, a via BARC film 7 is formed on the TEOS film 6, a via resist 8 is formed on the BARC film 7, and then the resist 8 is patterned (by exposure and development processing). Then, using the patterned resist 8 as a mask, the BARC film 7, the TEOS film 6, and the SiOC film 5 are etched to obtain a via pattern 41 penetrating the SiOC film 5.

  At this time, if the film thickness of the SiOC film 5 is reduced and the film thickness of the SiCN / SiCO film 4 is reduced, or the film quality is locally in a part of the SiCN / SiCO film 4, the etching selectivity is different from other regions. A small pinhole 51 is generated at the corresponding location when the current is low.

  Next, as shown in FIG. 4, the BARC film 7 and the resist 8 are removed by an ashing (O2 plasma) process. At this time, since the pinhole 51 exists but the wet process is not applied, the Cu wiring 3 under the via pattern 41 is not melted.

  Further, as shown in FIG. 4, the SiCN / SiCO film 4 under the via pattern 41 is also removed by dry etching, and the via pattern penetrating the SiOC film 5 and the SiCN / SiCO film 4 is formed deeper than the via pattern 41. 42 is obtained.

  Next, as shown in FIG. 5, a SiCO film 22 is deposited on the entire surface to prevent (resist) poisoning and protect the Cu wiring 3. Poisoning prevention means that when part of the SiCN / SiCO film 4 which is a liner film (underlying insulating film) is removed, the underlying liner film / Metal (SiCN / SiCO film 4 and Cu wiring 3) or the liner film "Nitrogen" at the time of deposition of the liner film comes into the via (embedding material 13, TEOS film 6 or BARC film 9) from the interface between the oxide film / oxide film (SiCN / SiCO film 4 and oxide film 2), and resist 10 Means a phenomenon that does not resolve.

  Next, as shown in FIG. 6, the filling material 13 is applied and etched back to leave the filling material 13 in the via pattern 41. Next, a BARC film 9 for wiring (pattern) is applied on the TEOS film 6 and the filling material 13, and further, a resist 10 for wiring is applied on the BARC film 9. Thereafter, the resist 10 is exposed and developed and patterned.

  Here, similarly to the case shown in the column of the principle of the invention, it is assumed that rework occurs in the lithographic process (patterning process) of the BARC film 9 and the resist 10 due to a dimension defect or the like. In this case, it is necessary to return to the state shown in FIG. 5 and execute the process shown in FIG. 6 again.

  In order to return to the state shown in FIG. 5, the resist 10, the BARC film 9 and the burying material 13 are ashed, and the burying material 13 hardened during ashing or the polymer generated during ashing is removed by wet processing. Thereafter, as described above, the structure shown in FIG. 6 can be obtained through the steps shown in FIG. 6 (formation of the filling material 13 by etching back, formation of the BARC film 9 and the resist 10, and patterning of the resist 10). .

  Therefore, even if the wet processing for removing the burying material 13 and the polymer at the time of reworking is performed, the SiCO film 22 is formed between the burying material 13 and the Cu wiring 3, so that the wet liquid used for the wet processing is Cu wiring. The Cu wiring 3 can be reliably protected from etching removal by the wet liquid.

  Next, as shown in FIG. 7, the BARC film 9, the SiCO film 22, the TEOS film 6, the filling material 13, and the SiOC film 5 are selectively removed by dry etching using the patterned resist 10 as a mask. A wiring trench 45 is formed in the upper layer portion of the SiOC film 5. The wiring groove 45 includes the via pattern 42 and is formed with a wider formation width than the via pattern 42.

  Thereafter, the resist 10, the BARC film 9 and the remaining filling material 13 are removed by ashing, and then the TEOS film 6 and the SiCO film 22 on the SiOC film 5 and the SiCO film 22 below the bottom of the via pattern 42 are removed by liner etching. Remove.

  As a result, the via pattern 42 located under the wiring groove 45 becomes the via hole 43, and the SiCO film 22 remains on the side surfaces of the SiOC film 5 and the SiCN / SiCO film 4 in the via hole 43. The reason why the wet process is not performed after the ashing process is that there is a low possibility that a polymer or the like remains as compared with the ashing process during rework.

  Then, as shown in FIG. 8, the barrier layer 11 is formed by sputtering, and the Cu wiring 12 is deposited by plating. Finally, annealing is performed, and unnecessary barrier layer 11 and Cu wiring 12 are removed by a CMP process to obtain the structure shown in FIG.

  As described above, in the multilayer Cu wiring structure of the first embodiment, even when a pinhole 51 is generated in the SiCN / SiCO film 4 in the manufacturing process, the Cu wiring 3 is protected by the SiCO film 22 formed on the upper part. Therefore, a part of the Cu wiring 3 is not dissolved by the wet process at the time of reworking in the lithographic process, and it is effective to improve the electrical characteristics of the wiring.

  In the first embodiment, the base insulating film is realized by the SiCN / SiCO film 4 having a two-layer structure. Of the SiCN / SiCO film 4, the SiCN film functions as an etching stopper because it has a high etching selectivity with respect to the SiOC film 5 that is an interlayer insulating film. However, as described above, the resist poisoning phenomenon caused by the nitrogen (N) -based gas in the SiCN film occurs.

  Therefore, by forming a SiCO film on the SiCN film to realize a SiCN / SiCO film 4 having a two-layer structure, the resist poisoning phenomenon can be effectively suppressed by making it difficult for nitrogen-based gas to escape. There is an effect.

  Further, since the SiCO film 22 formed on the side surface of the plug portion 18b can be formed with good film thickness and has a characteristic that the nitrogen-based gas is difficult to escape as described above, the resist poisoning resistance described above is stabilized. There is also an effect.

<Embodiment 2>
(Construction)
FIG. 9 is a cross-sectional view showing a multilayer Cu wiring structure (two layers in FIG. 9) in the semiconductor device according to the second embodiment of the present invention. As shown in the figure, a SiCN film 14 is formed on the oxide film 2 including the Cu wiring 3. Since the structure is the same as that of the first embodiment shown in FIG. 1 except that the SiCN / SiCO film 4 is replaced with the SiCN film 14, the description of other parts is omitted.

(Production method)
Since the manufacturing method is the same as the manufacturing method of the first embodiment except that the SiCN / SiCO film 4 is replaced with the SiCN film 14, the description thereof is omitted.

  In the multilayer Cu wiring structure of the second embodiment, in the manufacturing process, the Cu wiring 3 is formed in the upper SiCO even when the pinhole 51 is generated in the SiCN film 14 as in the SiCN / SiCO film 4 of the first embodiment. Since it is protected by the film 22, a part of the Cu wiring 3 is not dissolved by the wet process at the time of reworking in the lithography process, and it is effective to improve the electrical characteristics of the wiring.

  In addition, since the SiCN / SiCO film 4 of the first embodiment realizes the liner film with two layers, as a result of the large spread during etching, the via hole and the TOP dimension of the wiring are widened, and the wiring (via), wiring ( There is a concern that the space between vias becomes narrow and reliability becomes severe.

  On the other hand, in the multilayer Cu wiring structure of the second embodiment, since the liner film is realized by the single layer of the SiCN film 14, the spread during etching is reduced, so that the concern material of the first embodiment is surely avoided. Further effects are possible. In addition, the cost can be reduced by realizing the SiCN film 14 as a single layer. In the case of a single layer, it is desirable to use a SiCN film having a large etching selection ratio with respect to the SiOC film 5 which is an interlayer insulating film.

<Embodiment 3>
(Construction)
10 is a sectional view showing a multilayer Cu wiring structure (two layers in FIG. 10) in a semiconductor device according to a third embodiment of the present invention. As shown in the figure, the upper layer Cu wiring part 19 is composed of a wiring part 19a and a plug part 19b, similarly to the upper layer Cu wiring part 18 of the first embodiment shown in FIG. It is formed with a wider width than the plug portion 19b. The upper Cu wiring portion 19 includes a barrier (metal) layer 11 and a Cu wiring 12. The barrier layer 11 is formed along the bottom and side surfaces of the upper Cu wiring portion 19, and the Cu wiring 12 is formed in the barrier layer 11. . Therefore, the Cu wiring 3 and the Cu wiring 12 are electrically connected via the barrier layer 11 formed on the surface of the Cu wiring 3.

  Further, an SiCO film 23 as an auxiliary insulating film is interposed between the side surface of the plug part 19 b and the SiOC film 5. As described above, the multilayer Cu wiring structure of the third embodiment is formed by the Cu wiring 3 and the upper Cu wiring portion 19, and the SiCO film 23 is provided only between the side surface of the plug portion 19 b of the upper Cu wiring portion 19 and the SiOC film 5. It has the structure which has. Since other structures are the same as those of the first embodiment shown in FIG.

(Production method)
11 to 17 are sectional views showing a method for manufacturing a multilayer Cu wiring structure in the semiconductor device of the third embodiment. Hereinafter, a method for forming the multilayer Cu wiring structure of the third embodiment will be described with reference to these drawings.

  As shown in FIG. 11, an oxide film 2 is formed on the Si substrate 1, a Cu wiring 3 that selectively becomes a lower Cu wiring is formed in an upper layer portion of the oxide film 2, and penetrates the oxide film 2 from below the wiring 3. Thus, a structure in which the contact plug 31 reaching the surface of the Si substrate 1 is formed is obtained.

  Then, a SiCN / SiCO film 4 is deposited on the oxide film 2 including the Cu wiring 3 by a CVD method, and a SiOC film 5 is further deposited on the SiCN / SiCO film 4 by a CVD method. A TEOS film 6 is deposited thereon by CVD.

  Then, as shown in FIG. 12, a via BARC film 7 is formed on the TEOS film 6, a via resist 8 is formed on the BARC film 7, and then the resist 8 is patterned (by exposure and development processing). Then, using the patterned resist 8 as a mask, the BARC film 7, the TEOS film 6, and the SiOC film 5 are etched to obtain a via pattern 41.

  At this time, if the film thickness of the SiOC film 5 is reduced and the film thickness of the SiCN / SiCO film 4 is reduced, or the film quality is locally in a part of the SiCN / SiCO film 4, the etching selectivity is different from other regions. A small pinhole 51 is generated at the corresponding location when the current is low.

  Next, as shown in FIG. 13, the BARC film 7 and the resist 8 are removed by ashing (O 2 plasma) treatment. At this time, although the pinhole 51 exists, the Cu wiring 3 under the via pattern 41 is not dissolved because the wet process using the wet liquid is not applied.

  Next, as shown in FIG. 14, a SiCO film 23 is deposited on the entire surface to prevent poisoning and protect the Cu wiring 3.

  Next, as shown in FIG. 15, the filling material 13 is applied and etched back to leave the filling material 13 in the via pattern 41. Next, a wiring BARC film 9 is applied on the TEOS film 6 and the filling material 13, and further, a wiring resist 10 is applied on the BARC film 9. Thereafter, the resist 10 is exposed and developed and patterned.

  Here, similarly to the case shown in the column of the principle of the invention, it is assumed that rework occurs in the lithographic process (patterning process) of the BARC film 9 and the resist 10 due to a dimension defect or the like. In this case, it is necessary to return to the state shown in FIG. 14 and execute the process shown in FIG. 15 again.

  In order to return to the state shown in FIG. 14, the resist 10, the BARC film 9, and the burying material 13 are ashed, and the burying material 13 hardened during ashing and the polymer generated during ashing are removed by wet processing. Thereafter, as described above, the structure shown in FIG. 15 can be obtained through the steps shown in FIG. 15 (formation of the filling material 13 by etch back, formation of the BARC film 9 and the resist 10, and patterning of the resist 10). .

  Therefore, even if wet processing is performed on the burying material 13 at the time of reworking, the SiCO film 23 and the SiCN / SiCO film 4 are formed between the burying material 13 and the Cu wiring 3, and the SiCO film 23 is wet such as pinholes. Since there is no room for the liquid to enter, the wet liquid does not permeate the Cu wiring 3, and the Cu wiring 3 is reliably protected from etching removal.

  At this time, since the Cu wiring 3 is doubly protected by the SiCO film 23 and the SiCN / SiCO film 4, the Cu wiring 3 is etched and removed more reliably than in the first embodiment where only the SiCO film 22 is protected. Can be protected from.

  Next, as shown in FIG. 16, the BARC film 9, the SiCO film 22, the TEOS film 6, the filling material 13, and the SiOC film 5 are partially removed by dry etching using the patterned resist 10 as a mask. A wiring groove 45 is formed in the upper layer portion of the film 5. The wiring groove 45 includes the via pattern 41 and is formed with a wider formation width than the via pattern 41. The resist 10, the BARC film 9 and the remaining filling material 13 are removed by ashing, and then the TEOS film 6 and the SiCO film 23 on the SiOC film 5 and the SiCO film 23 and the SiCN below the bottom of the via pattern 41 by liner etching. / SiCO film 4 is removed. As a result, the via pattern 41 located under the wiring groove 45 becomes a via hole 44, and the SiCO film 23 remains on the side surface of the SiOC film 5 in the via hole 44.

  Then, as shown in FIG. 17, the barrier layer 11 is formed by the sputtering method, and the Cu wiring 12 is deposited by the plating method. Finally, annealing is performed, and unnecessary barrier layer 11 and Cu wiring 12 are removed by CMP processing to obtain a structure shown in FIG.

  Thus, the multilayer Cu wiring structure of the third embodiment is protected by the SiCO film 23 and the SiCN / SiCO film 4 even when the pinhole 51 is generated in the SiCN / SiCO film 4 in the manufacturing process. Therefore, a part of the Cu wiring 3 is not dissolved by the wet process at the time of rework in the lithographic process, and it is effective to improve the electrical characteristics of the wiring.

  Further, the manufacturing method of the third embodiment is a step of removing the SiCN / SiCO film 4 under the via pattern 41 after the formation of the via pattern 41 when compared with the manufacturing method of the first embodiment (step shown in FIG. 4). Since the process can be omitted, the manufacturing process can be simplified.

  On the other hand, in the manufacturing method of the third embodiment, since the SiCN / SiCO film 4 and the SiCO film 23 under the via pattern 41 after the formation of the wiring trench 45 are simultaneously removed, it is necessary to make the etching rates of SiCN and SiCO the same. However, in the manufacturing method of the first embodiment, it is only necessary to remove the SiCO film 22 under the via pattern 42 after the wiring trench 45 is formed, so that the etching process can be performed relatively easily and accurately.

<Others>
In the structure of the third embodiment, a structure in which the SiCN / SiCO film 4 is replaced with the SiCN film 14 as in the second embodiment is also conceivable. In this case, in addition to the simplification of the manufacturing process described above, the same effects as those of the second embodiment can be obtained. The above structure can be obtained by the manufacturing method similar to the manufacturing method of the third embodiment except that the SiCN / SiCO film 4 is replaced with the SiCN film 14.

  In the first to third embodiments, FIG. 1 (FIGS. 9 and 10) shows a two-layer structure including the Cu wiring 3 and the upper Cu wiring portion 18 (19). Of course, a multilayer structure of three or more layers can be realized by providing a wiring portion similar to the upper layer Cu wiring portion 18.

It is sectional drawing which shows the multilayer Cu wiring structure in the semiconductor device which is Embodiment 1 of this invention. FIG. 6 is a cross-sectional view showing the method for manufacturing the multilayer Cu wiring structure in the semiconductor device of the first embodiment. FIG. 6 is a cross-sectional view showing the method for manufacturing the multilayer Cu wiring structure according to the first embodiment. FIG. 6 is a cross-sectional view showing the method for manufacturing the multilayer Cu wiring structure according to the first embodiment. FIG. 6 is a cross-sectional view showing the method for manufacturing the multilayer Cu wiring structure according to the first embodiment. FIG. 6 is a cross-sectional view showing the method for manufacturing the multilayer Cu wiring structure according to the first embodiment. FIG. 6 is a cross-sectional view showing the method for manufacturing the multilayer Cu wiring structure according to the first embodiment. FIG. 6 is a cross-sectional view showing the method for manufacturing the multilayer Cu wiring structure according to the first embodiment. It is sectional drawing which shows the multilayer Cu wiring structure in the semiconductor device which is Embodiment 2 of this invention. It is sectional drawing which shows the multilayer Cu wiring structure in the semiconductor device which is Embodiment 3 of this invention. 12 is a cross-sectional view showing a method for manufacturing a multilayer Cu wiring structure in the semiconductor device of the third embodiment. FIG. FIG. 10 is a cross-sectional view showing a method for manufacturing the multilayer Cu wiring structure of the third embodiment. FIG. 10 is a cross-sectional view showing a method for manufacturing the multilayer Cu wiring structure of the third embodiment. FIG. 10 is a cross-sectional view showing a method for manufacturing the multilayer Cu wiring structure of the third embodiment. FIG. 10 is a cross-sectional view showing a method for manufacturing the multilayer Cu wiring structure of the third embodiment. FIG. 10 is a cross-sectional view showing a method for manufacturing the multilayer Cu wiring structure of the third embodiment. FIG. 10 is a cross-sectional view showing a method for manufacturing the multilayer Cu wiring structure of the third embodiment. It is sectional drawing which shows the multilayer Cu wiring structure used as a prerequisite technique. It is sectional drawing which shows the problem of the multilayer Cu wiring structure used as a prerequisite technique. It is sectional drawing which shows the manufacturing method of the multilayer Cu wiring used as the premise technique for demonstrating the cause which the problem shown in FIG. 19 arises. It is sectional drawing which shows the manufacturing method of the multilayer Cu wiring used as a prerequisite technique. It is sectional drawing which shows the manufacturing method of the multilayer Cu wiring used as a prerequisite technique. It is sectional drawing which shows the manufacturing method of the multilayer Cu wiring used as a prerequisite technique. It is sectional drawing which shows the manufacturing method of the multilayer Cu wiring used as a prerequisite technique. It is sectional drawing which shows the manufacturing method of the multilayer Cu wiring used as a prerequisite technique.

Explanation of symbols

1 Si substrate, 2 oxide film, 3,12 Cu wiring, 4 SiCN / SiCO film, 5 SiOC film, 6 TEOS film, 7,9 BARC film, 8,10 resist, 11 barrier layer, 13 filling material, 14 SiCN film 18, 19 Upper layer Cu wiring part, 22, 23 SiCO film, 31 contact plug.

Claims (10)

A semiconductor device having a multilayer copper wiring structure including a lower layer copper wiring and an upper layer copper wiring part formed on the lower layer copper wiring and having a wiring part and a plug part,
A base insulating film formed on the lower copper wiring;
An interlayer insulating film formed on the base insulating film;
The upper copper wiring portion formed through the underlying insulating film and the interlayer insulating film and in contact with the surface of the lower copper wiring;
An auxiliary insulating film formed at least between the plug portion of the upper copper wiring portion and the interlayer insulating film;
A semiconductor device comprising: The semiconductor device according to claim 1,
The auxiliary insulating film is further formed between the plug portion of the upper copper wiring portion and the base insulating film.
Semiconductor device. The semiconductor device according to claim 1,
The auxiliary insulating film is formed only between the plug portion of the upper copper wiring portion and the interlayer insulating film.
Semiconductor device. A semiconductor device according to any one of claims 1 to 3,
The base insulating film includes a base insulating film having a multi-layer structure including at least one layer made of a material having a sufficiently high etching selectivity with the interlayer insulating film.
Semiconductor device. A semiconductor device according to any one of claims 1 to 3,
The base insulating film includes a base insulating film having a single layer structure made of a material having a sufficiently large etching selectivity with the interlayer insulating film.
Semiconductor device. A method for manufacturing a semiconductor device having a multilayer copper wiring structure including a lower layer copper wiring and an upper layer copper wiring part formed on the lower layer copper wiring and having a wiring part and a plug part,
(a) forming the lower layer copper wiring;
(b) forming a base insulating film on a region including on the lower copper wiring;
(c) forming an interlayer insulating film on the base insulating film;
(d) selectively forming a via pattern penetrating at least the interlayer insulating film;
(e) forming an auxiliary insulating film on the bottom and side surfaces of the via pattern;
(f) burying a filling material in the via pattern via the auxiliary insulating film;
(g) selectively removing the interlayer insulating film, the filling material and the auxiliary insulating film, and selectively wiring the upper layer portion of the interlayer insulating film with the formation width including the via pattern and wider than the via pattern; Forming a groove;
(h) removing the filling material remaining in the via pattern;
(i) removing at least the auxiliary insulating film present on the bottom surface of the via pattern to expose a surface of the lower copper wiring to obtain a via hole;
(j) selectively forming the upper copper wiring portion in contact with the surface of the lower copper wiring inside the via hole and the wiring groove, and forming the upper copper wiring portion formed in the via hole Is defined as the plug portion, the upper copper wiring portion formed in the wiring groove is defined as the wiring portion,
After the execution of step (j), the auxiliary insulating film remains at least between the interlayer insulating film and the plug portion of the upper copper wiring,
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 6,
The step (d) includes a step of obtaining the via pattern by further penetrating the base insulating film in addition to the interlayer insulating film.
The step (i) includes the step of obtaining only the via hole by removing only the auxiliary insulating film present on the bottom of the via pattern,
After the execution of step (j), the auxiliary insulating film further remains between the base insulating film and the plug portion of the upper copper wiring.
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 6,
The step (d) includes the step of obtaining the via pattern only through the interlayer insulating film,
The step (i) includes a step of obtaining the via hole by removing the base insulating film in addition to the auxiliary insulating film present on the bottom of the via pattern,
After the execution of step (j), the auxiliary insulating film remains only between the interlayer insulating film and the plug portion of the upper copper wiring.
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to any one of claims 6 to 8,
The base insulating film includes a base insulating film having a multi-layer structure including at least one layer made of a material having a sufficiently high etching selectivity with the interlayer insulating film.
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to any one of claims 6 to 8,
The base insulating film includes a base insulating film having a single layer structure made of a material having a sufficiently large etching selectivity with the interlayer insulating film.
A method for manufacturing a semiconductor device.

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