JP2008021684A5 - - Google Patents

Description

Semiconductor integrated circuit and standard cell

  The present invention relates to a standard cell type semiconductor integrated circuit, and more particularly to a power supply wiring structure in a standard cell.

  In recent years, due to the increase in the scale of semiconductor integrated circuits, a cell library is created using logic cells such as AND and OR as standard cells, and standard cell layout design using the cell library is generally performed. On the other hand, with the increase in the speed and functionality of semiconductor integrated circuits, a technique for separately controlling the voltage supply of the source region and well region of the transistor (hereinafter also referred to as substrate bias control) for the purpose of improving the operation speed and suppressing the leakage current. )) Is being applied. For this reason, standard cells used in the layout design of a semiconductor integrated circuit can be classified into two types, a substrate bias control compatible type and a non-compatible type, when paying attention to the power supply wiring structure.

The standard cell corresponding to the substrate bias control has four wiring elements for supplying the source voltage and the substrate voltage of the PMOS and NMOS transistors, respectively. On the other hand, the number of wiring elements included in the standard cell that does not support the substrate bias control is two because the same voltage is supplied to the source voltage and the substrate voltage of the PMOS and NMOS transistors. Thus, since the number of wiring elements is different between the substrate bias control compatible type and the non-compatible type, the two types cannot be directly connected. Accordingly, in order to construct a semiconductor integrated circuit that does not support substrate bias control using a standard cell that supports substrate bias control, each of the PMOS and NMOS transistors that are formed by connecting the standard cells that support substrate bias control. Four wirings for supplying the source voltage and the substrate voltage and power lines (hereinafter also referred to as power straps) intersecting these wirings in the upper layer of these wirings are appropriately connected through via contacts, and PMOS and It is necessary to make the source voltage of the NMOS transistor and the substrate voltage have the same potential (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 11-233647

  There are a wide variety of development targets for semiconductor integrated circuits, and a product that supports substrate bias control and a product that does not support it can be manufactured in the same process. However, since the standard cell that supports substrate bias control cannot be directly connected to the standard cell that does not support substrate bias, the existing standard cell that does not support substrate bias control is used in a semiconductor integrated circuit design tool that supports substrate bias control. It is not possible. Accordingly, in order to design a semiconductor integrated circuit that does not support substrate bias control using a design tool for a semiconductor integrated circuit that supports substrate bias control, as described above, after arranging a standard cell that supports substrate bias control, a PMOS transistor Wiring for supplying the source voltage and the substrate voltage is electrically connected by the power supply strap and the via contact, or the substrate bias control non-corresponding cell that can be directly connected to the standard cell corresponding to the substrate bias control. It is necessary to build a new library.

  However, since the wirings for supplying the source voltage and the substrate voltage of the PMOS or NMOS transistor are usually arranged close to each other, via contacts connected to these wirings are also provided close to each other. For this reason, other signal wirings must be arranged avoiding these via contacts, and the wiring is congested. When the substrate bias control is not performed, almost no current flows through the substrate voltage supply wiring. For this reason, while the power supply voltage fluctuation (IR-Drop) in the well region is relatively small, a large current flows through the source voltage supply wiring due to the switching operation of the transistor, and the power supply voltage fluctuation increases. As a result, the substrate bias effect acts locally due to the potential difference between the well region and the source region, resulting in delay variation.

  On the other hand, the general cell lineup includes not only logic cells that constitute logic such as AND and OR, but also cells that have the same logic but different driving capabilities, flip-flops, latches, and transistors that are arranged to fill empty spaces between cells. There are hundreds of types, such as filler cells that do not have a capacitor, and capacitor cells that have a transistor for adding a capacitance between power supply lines of a power supply voltage and a ground voltage. If a standard cell that does not support substrate bias control is newly developed for all of these, the man-hours for developing a semiconductor integrated circuit will increase significantly.

  In view of the above problems, the present invention provides a standard cell that can be directly connected to a substrate bias control compatible standard cell to constitute a semiconductor integrated circuit that does not support substrate bias control, and a semiconductor integrated circuit including such a cell. The issue is to provide

In order to solve the above-mentioned problems, the present invention provides a semiconductor integrated circuit in which a plurality of standard cells are connected, and each of the plurality of standard cells has the full width of the cell at a predetermined position in the cell. to extend, has a pair of wire elements for supplying respective source voltages and a substrate voltage of a predetermined conductivity type insulated gate field effect transistor, the plurality of standard cells, connecting said pair of interconnection elements to each other The first standard cell and the second standard cell in which the pair of wiring elements are not connected to each other, and the first standard cell and the second standard cell are directly connected Shall. Further, as a standard cell connected to a standard cell for constituting a semiconductor integrated circuit capable of controlling a substrate bias, it extends to the full width of the cell at a predetermined position in the cell, and is a predetermined conductivity type insulated gate field effect transistor. a pair of wire elements of the source voltage and for supplying a substrate voltage, respectively, a pair of wiring elements is assumed to be connected to each other physician.

According to this, in the standard cell, because the pair of wiring elements for the source voltage and a substrate voltage supply respective predetermined conductivity type insulated gate field effect transistor is connected to the doctor each other, the standard cell, the substrate A semiconductor integrated circuit that does not support substrate bias control can be configured by directly connecting to a standard cell that supports bias control. Further, if at least one standard cell has the above-described configuration, a semiconductor integrated circuit that does not support substrate bias control can be configured. Therefore, the man-hours required for correction and addition of the standard cell can be reduced.

Specifically, the above scan Tandadoseru are filler cell, capacity cells or mass transistor cells.

  Preferably, the semiconductor integrated circuit is formed in a wiring layer different from a pair of wirings formed by connecting a pair of wiring elements in the plurality of standard cells and intersects with the pair of wirings. Assume that there are two power lines. One of the pair of wirings and the power supply line are connected via via contacts. According to this, since the wiring layer between the other of the pair of wirings and the power supply line can be used for other signal wirings, wiring congestion is reduced.

  More preferably, the semiconductor integrated circuit includes a plurality of power supply lines, and these power supply lines are all connected to only one of a pair of wirings. According to this, it is possible to lay out another signal wiring that is linear and long between the other of the pair of wirings and the power supply line.

  Preferably, the pair of wiring elements are arranged at a minimum pitch on the wiring layout. According to this, since a pair of wiring elements are connected in an area that is not used in the signal wiring layout, the wiring area is not wasted.

  Specifically, the pair of wiring elements are formed in the same wiring layer. Alternatively, the pair of wiring elements are formed in different wiring layers, and the upper layer wiring element of the pair of wiring elements is via-contacted to the intermediate wiring element formed in the same wiring layer as the lower layer wiring element. The intermediate wiring element and the lower wiring element are connected to each other in the wiring layer of the lower wiring element.

  As described above, according to the present invention, in order to design a semiconductor integrated circuit that does not support substrate bias control using a semiconductor integrated circuit design tool that supports substrate bias control, some types of standard cells are included in the cell library. Just add only. As a result, the number of development man-hours when a semiconductor integrated circuit that does not support substrate bias control is configured using the design tool is greatly reduced.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 shows the configuration of a standard cell according to the first embodiment. This standard cell is an example of a cell constituting logic, and operates as an inverter circuit. Specifically, this standard cell includes four wiring elements 11, 12, 13, and 14 extending to the full width of the cell. Each of these wiring elements 11 to 14 is provided at a predetermined position in the cell so that wiring is formed when a plurality of standard cells are connected.

  The wiring elements 11 and 12 are for supplying the source voltage and the substrate voltage of the PMOS transistor 210 formed on the N well 21, respectively. The wiring element 11 has a protrusion 111 that extends onto the source region diffusion layer 211 of the PMOS transistor 210. The wiring element 11 is connected to the source region diffusion layer 211 through the contact at the protrusion 111. On the other hand, the wiring element 12 is connected to the high-concentration N-type impurity diffusion region 212 on the N well 21 through a contact. The wiring element 11 and the wiring element 12 are connected to each other by a bridge 112.

  Similarly to the above, the wiring elements 13 and 14 are for supplying the source voltage and the substrate voltage of the NMOS transistor 220 formed on the P well 22, respectively. The wiring element 13 has a protrusion 131 that extends onto the source region diffusion layer 221 of the NMOS transistor 220. The wiring element 13 is connected to the source region diffusion layer 221 through a contact at the protrusion 131. On the other hand, the wiring element 14 is connected to the high-concentration P-type impurity diffusion region 222 on the P well 22 through a contact. The wiring element 13 and the wiring element 14 are connected to each other by a bridge 132.

  A broken line in FIG. 1 represents a grid line that is a reference in wiring layout. Usually, the wiring elements 11 and 12 are arranged at the minimum pitch d on the wiring layout. The same applies to the wiring elements 13 and 14. Accordingly, since no other signal wiring is originally arranged between the wiring element 11 and the wiring element 12 or between the wiring element 13 and the wiring element 14, the wiring area is not wasted by the bridges 112 and 132. .

  As described above, the standard cell according to the present embodiment includes the four wiring elements for supplying the source voltage and the substrate voltage of the PMOS transistor and the NMOS transistor, respectively, like the standard cell for substrate bias control. It can be directly connected to a bias control compatible standard cell. Further, in the semiconductor integrated circuit configured by appropriately connecting the standard cell according to the present embodiment and the standard cell for substrate bias control, the source voltage of the PMOS transistor and the substrate voltage become the same potential, and the NMOS transistor The source voltage and the substrate voltage are the same potential. Therefore, a semiconductor integrated circuit that does not support substrate bias control can be designed with a design tool for a semiconductor integrated circuit that supports substrate bias control by simply adding the standard cell according to the present embodiment to the cell library.

(Second Embodiment)
FIG. 2 shows the configuration of a standard cell according to the second embodiment. This standard cell operates as a MOS capacitor. As in the first embodiment, in this standard cell, the wiring element 11 and the wiring element 12 are connected to each other by the bridge 112, and the wiring element 13 and the wiring element 14 are connected to each other by the bridge 132.

  As in the first embodiment, the standard cell according to this embodiment can be directly connected to a standard cell that supports substrate bias control. Furthermore, in the semiconductor integrated circuit configured by connecting the standard cell according to the present embodiment and the standard cell for substrate bias control, both wirings for supplying the source voltage and the substrate voltage of the PMOS transistor are implemented. Since it is connected to the gate capacitance in the standard cell according to the embodiment, noise on the substrate power supply side of the PMOS transistor can be absorbed.

(Third embodiment)
FIG. 3 shows the configuration of a standard cell according to the third embodiment. This standard cell is one in which three standard cells (inverter circuits) shown in FIG. 1 are connected in parallel to increase power consumption. In this standard cell, the wiring element 11 and the wiring element 12 are connected to each other by three bridges 112, and the wiring element 13 and the wiring element 14 are connected to each other by three bridges 132. As described above, for an element through which a large current flows, it is preferable to reduce the connection resistance by connecting the wiring element 11 and the wiring element 12 and the wiring element 13 and the wiring element 14 at a plurality of locations.

  As in the first embodiment, the standard cell according to this embodiment can be directly connected to a standard cell that supports substrate bias control. Further, when a large current flows through the PMOS transistor 210, the potential of the source region diffusion layer 211 decreases. However, since the wiring element 11 and the wiring element 12 are connected, the source region diffusion layer 211 and the N well 21 are connected. Hardly causes a potential difference, and a decrease in operation speed due to the substrate bias effect is suppressed. The same can be said for the NMOS transistor 220.

(Fourth embodiment)
FIG. 4 shows the configuration of a standard cell according to the fourth embodiment. This standard cell is an example of a filler cell. As in the first embodiment, in this standard cell, the wiring element 11 and the wiring element 12 are connected to each other by the bridge 112, and the wiring element 13 and the wiring element 14 are connected to each other by the bridge 132.

  As in the first embodiment, the standard cell according to this embodiment can be directly connected to a standard cell that supports substrate bias control. Furthermore, since filler cells are used to fill the space between logic cells, they are frequently used and may occupy about 20 to 30 percent of the total number of cells. Therefore, in the semiconductor integrated circuit including the standard cell according to the present embodiment, it is possible to secure a large number of wiring connection points for supplying the source voltage and the substrate voltage of the PMOS transistor or NMOS transistor, and the power supply voltage of the well region. The fluctuation can be made sufficiently small.

(Fifth embodiment)
FIG. 5 shows a configuration of a standard cell according to the fifth embodiment. This standard cell is a filler cell obtained by modifying the standard cell shown in FIG. In this standard cell, the wiring element 11 and the wiring element 12 are connected to each other by a bridge 112 extending to the full width of the cell. That is, in this standard cell, the wiring elements 11 and 12 and the bridge 112 are formed as one wide wiring element extending to the full width of the cell.

  As in the first embodiment, the standard cell according to this embodiment can be directly connected to a standard cell that supports substrate bias control. Furthermore, since the bridge connecting the two wiring elements has the maximum width in the cell, the connection resistance between these wiring elements can be minimized.

  In the present embodiment, the wiring element 13 and the wiring element 14 are not connected, but this is to enable the substrate bias control of the NMOS transistor. Also in the first to fourth embodiments, the bridge connecting the wiring elements may have the maximum width. Further, in either one of the PMOS transistor and the NMOS transistor, a bridge between the wiring elements may not be provided in order to enable substrate bias control.

(Sixth embodiment)
FIG. 6 shows a configuration of a semiconductor integrated circuit according to the sixth embodiment. In the present semiconductor integrated circuit, two standard cells 100A according to any one of the first to fifth embodiments and six standard cells 200A corresponding to substrate bias control are connected. This semiconductor integrated circuit uses the wirings 110 and 120 formed by connecting wiring elements for supplying the source voltage and the substrate voltage of the PMOS transistor in each standard cell, and the source voltage and the substrate voltage of the NMOS transistor. Wiring elements 130 and 140 are formed by connecting wiring elements for supplying each of them. The semiconductor integrated circuit is formed in a wiring layer different from the wirings 110 to 140 and crosses the wirings 110 to 140 to supply the source voltages of the PMOS transistor and the NMOS transistor, respectively. 3 each. In FIG. 6, illustration of each diffusion layer and gate wiring on the N well 21 and the P well 22 is omitted, and only various wirings are shown.

  In the present semiconductor integrated circuit, the wiring 110 and the wiring 120 are connected to each other in the standard cell 100A. For this reason, the power supply strap 150 only needs to be connected to either one of the wirings 110 and 120 via a via contact. Specifically, the power supply strap 150 is connected to the wiring 110 via a via contact. That is, another signal wiring can be arranged in the wiring layer between the power supply strap 150 and the wiring 120. Normally, the wiring 110 and the wiring 120 are arranged at the minimum pitch in the wiring layout. Therefore, when the via contacts are passed through the wirings 110 and 120 from the power supply strap 150, other signal wirings should avoid these via contacts. It must be placed, causing wiring congestion. On the other hand, in the present embodiment, the wiring layer between the power supply strap 150 and the wiring 120 can be used for other signal wiring, so that wiring congestion is alleviated.

  Furthermore, in this semiconductor integrated circuit, all three power supply straps 150 are connected to the wiring 110 via via contacts. Accordingly, another signal wiring having a linear length can be arranged between the power supply strap 150 and the wiring 120 in parallel with the wiring 120. The same applies to the wirings 130 and 140 and the power supply strap 160.

(Seventh embodiment)
FIG. 7 shows the configuration of a standard cell according to the seventh embodiment. FIG. 8 shows a cross section of the semiconductor integrated circuit shown in FIG. This standard cell operates as an inverter circuit. In this standard cell, the wiring elements 11 and 13 are formed in a wiring layer different from the wiring elements 12 and 14. Specifically, the wiring element 11 is connected to an intermediate wiring element 113 formed in the same wiring layer as the wiring element 12 via a via contact. Similarly, the wiring element 13 is connected to an intermediate wiring element 133 formed in the same wiring layer as the wiring element 14 via a via contact. The intermediate wiring element 113 and the wiring element 12 are connected to each other by a bridge 112, and the intermediate wiring element 133 and the wiring element 14 are connected to each other by a bridge 132.

  The standard cell according to the present embodiment is directly connected to a substrate bias control compatible standard cell in which wiring elements for supplying the source voltage and substrate voltage of the PMOS transistor or NMOS transistor are formed in different wiring layers. Can do. Further, in the semiconductor integrated circuit configured by connecting the standard cell according to the present embodiment and the standard cell for substrate bias control, the source voltage of the PMOS transistor and the substrate voltage become the same potential, and the NMOS transistor 220 The source voltage and the substrate voltage are the same potential. Therefore, a semiconductor integrated circuit that does not support substrate bias control can be designed with a design tool for a semiconductor integrated circuit that supports substrate bias control by simply adding the standard cell according to the present embodiment to the cell library.

(Eighth embodiment)
FIG. 9 shows the configuration of a standard cell according to the eighth embodiment. FIG. 10 shows a cross section of the semiconductor integrated circuit shown in FIG. This standard cell is an example of a filler cell. As in the seventh embodiment, in this standard cell, the intermediate wiring element 113 and the wiring element 12 are connected to each other by the bridge 112, and the intermediate wiring element 133 and the wiring element 14 are connected to each other by the bridge 132. Yes.

  Similar to the seventh embodiment, the standard cell according to the present embodiment can be directly connected to a substrate bias control compatible standard cell in which each wiring element is formed in a different wiring layer. Furthermore, as described above, filler cells are frequently used in standard cell type semiconductor integrated circuits. Therefore, in the semiconductor integrated circuit including the standard cell according to the present embodiment, it is possible to secure a large number of wiring connection points for supplying the source voltage and the substrate voltage of the PMOS transistor or NMOS transistor, and the power supply voltage of the well region. The fluctuation can be made sufficiently small.

  Note that a standard cell that operates as a MOS capacitor and a standard cell that operates as a large-current inverter circuit can be configured in the same manner as described above.

(Ninth embodiment)
FIG. 11 shows a configuration of a semiconductor integrated circuit according to the ninth embodiment. In the present semiconductor integrated circuit, two standard cells 100B according to any of the seventh and eighth embodiments are connected to five standard cells 200B corresponding to substrate bias control. This semiconductor integrated circuit uses the wirings 110 and 120 formed by connecting wiring elements for supplying the source voltage and the substrate voltage of the PMOS transistor in each standard cell, and the source voltage and the substrate voltage of the NMOS transistor. Wiring elements 130 and 140 are formed by connecting wiring elements for supplying each of them. In FIG. 6, illustration of each diffusion layer and gate wiring on the N well 21 and the P well 22 is omitted, and only various wirings are shown.

  In the present semiconductor integrated circuit, the wiring 110 and the wiring 120 are connected to each other in the standard cell 100B. Thus, by connecting the standard cell according to the present invention and a standard cell that supports substrate bias control, a semiconductor integrated circuit that does not support substrate bias control can be easily configured.

  The standard cell according to the present invention can be connected directly to a substrate bias control compatible standard cell to form a semiconductor integrated circuit that does not support substrate bias control. It is useful as a cell for designing a semiconductor integrated circuit that does not support substrate bias control.

It is a block diagram of the standard cell (inverter circuit) which concerns on 1st Embodiment. FIG. 6 is a configuration diagram of a standard cell (MOS capacitor) according to a second embodiment. It is a block diagram of the standard cell (high current inverter circuit) which concerns on 3rd Embodiment. It is a block diagram of the standard cell (filler cell) which concerns on 4th Embodiment. It is a block diagram of the standard cell (filler cell) which concerns on 5th Embodiment. It is a block diagram of the semiconductor integrated circuit which concerns on 6th Embodiment. It is a block diagram of the standard cell (inverter circuit) which concerns on 7th Embodiment. FIG. 8 is a cross-sectional view of the semiconductor integrated circuit shown in FIG. 7. It is a block diagram of the standard cell (filler cell) which concerns on 8th Embodiment. FIG. 10 is a cross-sectional view of the semiconductor integrated circuit shown in FIG. 9. It is a block diagram of the semiconductor integrated circuit which concerns on 9th Embodiment.

100A, 100B Standard cells 11-14 Wiring elements 150, 160 Power line

Claims (13)

A semiconductor integrated circuit in which a plurality of standard cells are connected,
Each of the plurality of standard cells extends to the full width of the cell at a predetermined position in the cell, and a pair of wirings for supplying a source voltage and a substrate voltage of a predetermined conductivity type insulated gate field effect transistor, respectively. Has elements,
The plurality of standard cells are:
A first standard cell, wherein the pair of interconnecting element are connected to each other,
A second standard cell in which the pair of wiring elements are not connected to each other;
The semiconductor integrated circuit, wherein the first standard cell and the second standard cell are directly connected . The semiconductor integrated circuit according to claim 1,
The semiconductor integrated circuit according to claim 1, wherein the first standard cell is a filler cell. The semiconductor integrated circuit according to claim 1,
The semiconductor integrated circuit according to claim 1, wherein the first standard cell is a capacitor cell. The semiconductor integrated circuit according to claim 1,
The semiconductor integrated circuit according to claim 1, wherein the first standard cell is a large capacity transistor cell. The semiconductor integrated circuit according to claim 1,
The pair of wiring elements in the plurality of standard cells is formed in a wiring layer different from the pair of wirings formed in a connected manner, and includes at least one power supply line crossing the pair of wirings;
One of the pair of wirings and the power supply line are connected via a via contact. The semiconductor integrated circuit according to claim 5,
A plurality of the power lines are provided,
The plurality of power supply lines are all connected to only one of the pair of wirings. A standard cell connected to a standard cell for constituting a semiconductor integrated circuit capable of controlling substrate bias,
A pair of wiring elements for respectively supplying a source voltage and a substrate voltage of an insulated gate field effect transistor of a predetermined conductivity type, extending to the full width of the cell at a predetermined position in the cell;
It said pair of wire elements, standard cells, characterized in that connected to each other physician. In the standard cell according to claim 7,
The standard cell, wherein the pair of wiring elements are arranged at a minimum pitch on a wiring layout. In the standard cell according to claim 7,
The standard cell, wherein the pair of wiring elements are formed in the same wiring layer. In the standard cell according to claim 7,
The pair of wiring elements are formed in different wiring layers,
Of the pair of wiring elements, the upper layer side wiring element is connected to an intermediate wiring element formed in the same wiring layer as the lower layer side wiring element via a via contact,
The standard cell according to claim 1, wherein the intermediate wiring element and the lower wiring element are connected to each other in a wiring layer of the lower wiring element. The semiconductor integrated circuit according to any one of claims 1 to 6,
The pair of wiring elements are formed in different wiring layers.
A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 11, wherein
In the pair of wiring elements, a wiring element for supplying a source voltage is formed in an upper layer than a wiring element for supplying a substrate voltage.
A semiconductor integrated circuit. The semiconductor integrated circuit according to any one of claims 1 to 6, 11, and 12,
The second standard cell is a standard cell for substrate bias control.
A semiconductor integrated circuit.