CN116938220A - Semiconductor device and level shift circuit - Google Patents

Abstract

Embodiments of the present application provide a semiconductor device and a level shift circuit, the semiconductor device including a plurality of transistors formed in a substrate, a front side power rail disposed on a front side of the substrate, and a back side power rail disposed on a back side of the substrate. The transistor forms a first cell that operates at least at a first supply voltage and a second cell that operates at a second supply voltage that is different from the first supply voltage. The front side power rail provides a first power supply voltage to the first cell and the back side power rail provides a second power supply voltage to the second cell.

Description

Semiconductor device and level shift circuit

Technical Field

Embodiments of the present application relate to a semiconductor device and a level shift circuit.

Background

The semiconductor Integrated Circuit (IC) industry has experienced an exponential growth. Technological advances in integrated circuit materials and design have resulted in a generation of yet another generation of integrated circuits, each of which is smaller and more complex than the previous generation. During the development of ICs, the functional density (i.e., the number of interconnected devices per chip area) generally increases, while the geometry (i.e., the smallest component (or line) that can be created using a manufacturing process) decreases. Such a scaling down process generally provides benefits by improving production efficiency and reducing associated costs. This scaling down also increases the complexity of processing and manufacturing ICs.

Integrated circuits may be built in a stacked fashion with transistors at the lowest level and interconnects (vias and wires) on top of the transistors to provide connections to the transistors. The power rails (e.g., metal lines for the voltage source and ground plane) may also be over the transistors and may be part of the interconnect. As integrated circuits continue to scale, so does the power rails. This results in an increase in voltage drop across the power supply rail and an increase in power consumption of the integrated circuit. Thus, while existing methods in semiconductor fabrication are generally adequate for their intended purposes, they are not entirely satisfactory in all respects. One area of interest is how to form power rails on the front and back sides of an integrated circuit. Accordingly, there is a need for a power rail structure for integrated circuits that addresses these issues with enhanced circuit performance and reliability, as well as increased packaging density.

Disclosure of Invention

According to an aspect of an embodiment of the present application, there is provided a semiconductor device including: a plurality of transistors formed in the substrate, the plurality of transistors forming at least a first cell operating at a first power supply voltage and a second cell operating at a second power supply voltage different from the first power supply voltage; a front side power rail disposed on a front side of the substrate, the front side power rail providing a first power voltage to the first unit; and a backside power rail disposed on a backside of the substrate, the backside power rail providing a second power voltage to the second unit.

According to another aspect of an embodiment of the present application, there is provided a semiconductor device including: a plurality of active regions formed on the substrate, each active region extending longitudinally in a first direction; a plurality of gate structures disposed over the active region, each gate structure extending longitudinally in a second direction perpendicular to the first direction; a first front side metal line disposed above the gate structure and extending longitudinally in a first direction, the first front side metal line carrying a first power supply voltage; a second front side metal line disposed over the gate structure and extending longitudinally in the first direction, the second back side metal line carrying a ground reference voltage; a first backside metal line disposed below the substrate and extending longitudinally in a first direction, the first backside metal line carrying a second power supply voltage different from the first power supply voltage; and a second backside metal line disposed under the substrate and extending longitudinally in the first direction, the second backside metal line carrying a ground reference voltage.

According to still another aspect of an embodiment of the present application, there is provided a level shift circuit including: a plurality of transistors configured to convert a signal of a first voltage level to a second voltage level higher than the first voltage level; a front side power line disposed over the transistor, the front side power line transmitting a first voltage level to a first source/drain region of the transistor; and a backside power line disposed below the transistor, the backside power line transmitting a second voltage level to a second source/drain region of the transistor.

Drawings

The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a schematic diagram of a circuit having multiple voltage domains according to some embodiments of the present disclosure.

Fig. 2 is a schematic diagram of a memory circuit according to some embodiments of the present disclosure.

Fig. 3 is a schematic diagram illustrating different voltage domains of the memory circuit in fig. 2 according to some embodiments of the present disclosure.

Fig. 4A and 4B are front and back side views, respectively, of a layout of a plurality of cells operating at a plurality of voltage domains, according to some embodiments of the present disclosure.

Fig. 5 is a schematic diagram of a plurality of cells operating under a plurality of voltage domains in fig. 4A and 4B, according to some embodiments of the present disclosure.

Fig. 6 is an alternative schematic diagram of a plurality of cells operating under a plurality of voltage domains in fig. 4A and 4B, according to some embodiments of the present disclosure.

Fig. 7, 8, 9, and 10 are cross-sectional views of regions of a semiconductor device according to some embodiments of the present disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact.

Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Furthermore, in the present disclosure below, features formed on, connected to, and/or coupled to another feature may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed as intervening features such that the features may not be in direct contact. Further, for example, "below," "above," "horizontal," "vertical," "above …," "below," "upper," "lower," "top," "bottom," etc., and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) are used to simplify the relationship of one feature of the disclosure to another feature. Spatially relative terms are intended to cover different orientations of the device comprising the features. Furthermore, when a number or range of numbers is described with "about," "approximately," etc., the term is intended to cover numbers within +/-10% of the number described unless otherwise specified. For example, the term "about 5nm" includes the size range from 4.5nm to 5.5 nm.

The present disclosure provides various embodiments of a semiconductor device having front and back side power rails. In particular, the present disclosure provides various embodiments for distributing different supply voltages from multiple voltage domains to a cell stage or transistor stage through front side and back side supply rails.

Semiconductor devices may be fabricated on a substrate, typically but not necessarily made of silicon or other suitable semiconductor material. The semiconductor device may have circuit blocks that provide certain functions. These circuit blocks may be referred to as "cells". The semiconductor device may include a plurality of cells. The cells may be custom designed or provided by standard cell libraries. The layout of a cell of a typical design may be drawn by a circuit designer. The provider of the standard cell library may provide the layout of its cells as well as other characteristics such as timing performance and electrical parameters.

The unit requires a power supply to function properly. On the substrate, the power supply may be distributed through a network made of conductive material (e.g., metal lines and vias). The power distribution network is also referred to as a power rail. The power rail provides one or more conductive paths disposed between the cells and the voltage domain. The voltage domain may provide a reference voltage by being connected to a power supply. One example is Vdd, which provides a positive voltage of a certain magnitude. In general, an integrated circuit may have a single positive voltage domain (the other voltage domain is Vss, which provides a ground reference). For a single positive voltage domain, all cells in the integrated circuit are powered by Vdd.

Not all cells need to operate in the same voltage domain. Taking a memory device such as a Static Random Access Memory (SRAM) circuit as an example, the memory device is affected by a phenomenon called leakage power (leakage power). Leakage power is typically dissipated by logic in the peripheral and core memory arrays whenever the memory is powered up. As technology continues to shrink device components below sub-nanometer geometries, leakage power dissipation in memory devices increases. Such leakage power is becoming an important factor in the total power dissipation in memory devices. One way to reduce leakage power is to reduce the supply voltage of the memory device. However, the voltage level of the bit cells in the memory needs to be maintained at a minimum voltage specification for retention, while the peripheral portion of the memory device may operate below a specified voltage.

Implementing multiple voltage domains is an effective way to suppress leakage power and reduce power consumption. A high voltage (denoted VddH) is applied to critical functional blocks or paths and a low voltage (denoted VddL) is applied to non-critical functional blocks or paths. This approach not only reduces power, but also maintains circuit performance.

Fig. 1 shows an example circuit 10 having multiple voltage domains implemented at the cell level or even lower-transistor level. The circuit 10 includes logic gates of clusters (clusters) 12A, 12B, 12C, 12D of voltage domains allocated with higher voltages VddH, which are logic gates on the critical path. The circuit 10 also includes logic gates of clusters 14A, 14B, 14C assigned another voltage domain of lower voltage VddL, which are logic gates on non-critical paths. The Level Shifter (LS) requires a logic gate that is sandwiched between logic gates in the VddL domain and that fans into the VddH domain, such as LS 16 sandwiched between cluster 14A in the VddL domain and cluster 12D in the VddH domain. Flip-flop (FF) 12 and level shifter flip-flop (LCFF) 14 provide input/output (I/O) of circuit 10. FF 12 provides direct input and output connections to clusters in the VddH domain. To couple the clusters in the VddL domain to FF 12, LS is required for voltage domain switching, such as LS 16 sandwiched between clusters 14C and FF 12 in the VddL domain. At the same time, the LCFF may provide a direct output connection to a cluster in the VddL domain, such as LCFF 14 coupled directly to cluster 14C in the VddL domain, without requiring an additional LS.

Returning to the above example of a memory device, the multiple voltage domains allow the periphery and core of the memory device to operate with different power supplies at different voltages to reduce leakage power. A memory device having multiple voltage domains uses a level shifter to isolate a high voltage domain (e.g., vddH) of one set of cells (or transistors) from a low voltage domain (e.g., vddL) of another set of cells and converts the signal voltage to the appropriate domain through the level shifter. Multiple voltage domains inevitably require multiple power rails. Furthermore, to implement multiple voltage domains at the cell level or transistor level, the power supply rails of different voltage domains may need to be interleaved.

FIG. 2 depicts a block diagram of a memory circuit 20 in accordance with one or more embodiments. In an embodiment, the memory circuit includes control circuitry 22, word line drivers 24, memory cell array 26, and I/O circuitry 38. The memory cell array 26 stores data in the respective memory cells; each cell is capable of storing one bit. The memory cells in the memory cell array 26 are addressable by respective intersections of the memory cells with individually selectable word lines, which correspond to rows of data bits that may have any suitable length, and individual columns or bit lines. The word lines are selected and driven by a word line driver 24. Word line driver 24 receives control signals from control circuitry 22 and in response selects and causes the individually addressed word lines to be asserted. In response to the asserted word line, data stored within memory cells associated with the asserted word line within memory cell array 26 is gated onto their respective bit lines. The control circuit 22 may also include a column selector for selecting individual bit lines or bit line ranges to be transferred to the IO connection 28. The bit lines are associated with sense amplifiers 36. When the word line is activated, the control circuit 22 includes a timing circuit for enabling the sense amplifier 36 at the appropriate time in accordance with, for example, a read operation. The sense amplifier 36 is driven by the sense amplifier driver 34. The sense amplifier 36, sense amplifier driver 34, and I/O connection 28 may be collectively referred to as an I/O circuit 38. Each sense amplifier driver 34 is enabled by a respective local sense amplifier enable signal. Each local sense amplifier enable signal is generated in response to a Global Sense Amplifier Enable (GSAE) signal generated by GSAE circuit 30. This GSAE signal may be generated in response to a bit line read enable signal generated by a control circuit of the memory application.

Fig. 3 depicts a graph 50 showing the power domains from which the components of fig. 2 receive respective voltage supplies. GSAE circuitry 30, I/O circuitry 38, and word line driver 24 may be powered by VddL from a low voltage domain (VddL domain). On the other hand, the memory cell array 26, the word line 40, and the GSAE signals 42 may be provided by VddH from a high voltage domain (VddH domain). As shown, word line driver 24 may include control components that are powered by VddL, while word line 40 itself may be powered by VddH because word line 40 needs to be transferred into memory cell array 26 in the VddH domain. Similarly, GSAE circuit 30 may include control components powered by VddL, while GSAE signals 42 themselves may be powered by VddH. One consideration is that the GSAE signal may be buffered to avoid clock skew due to long-term propagation to sense amplifiers farther in the circuit, and that providing VddH to GASE may reduce any fanout problem due to propagating GSAE to many drivers. In the illustrated memory circuit 20, at least three circuit blocks, namely the word line driver 24, the GSAE circuit 30 and the I/O circuit 38, operate in a dual voltage domain. A level shifter may be interposed in these circuit blocks for internal switching from a low voltage domain to a high voltage domain at the cell level or transistor level.

Semiconductor devices including memory circuits are typically built in a stacked fashion with transistors at the lowest level and interconnects (vias and wires) at the top of the transistors to provide connections to the transistors. The power rail is also over the transistor and may be part of the interconnect. In order to provide multiple voltage domains to a cell or transistor stage, it may be necessary to interleave the power rails of the different voltage domains. As integrated circuits continue to scale, so does the power rails. Interleaving power rails of different voltage domains becomes quite challenging. In order to install multiple power rails into a limited chip area, the voltage drop across the power rails is typically increased, which in turn increases the power consumption of the integrated circuit and negates the benefits of introducing a low voltage domain.

In addition to the power supply rails on the front side of the substrate, additional power supply rails may be provided on the back side of the substrate. The front side power rail may be dedicated to one voltage domain while the back side power rail may be dedicated to another voltage domain. Alternatively, one of the power rails may be dedicated to a single voltage domain and the other may be dedicated to a dual voltage domain. One benefit of implementing the backside power rail is the ability to separate dual voltage domains on the front side and the backside, respectively, without (or with reduced) competition for routing areas, and/or the ability to reserve more area on the front side for circuit elements such as logic and memory.

The substrate on which the semiconductor device is fabricated may be single-sided or double-sided. For a single sided substrate, the terms "front side", "front side" and "front side" generally refer to the side where circuit elements or devices (e.g., passive and active devices) are present, while the terms "back side", "backside" or "backside" generally do not contain circuit elements, generally refer to the side opposite the front side. For a double sided substrate, "front side" and similar terms generally still refer to the side on which the circuit elements or devices are fabricated, but there may also be circuit elements on the "back side". In this disclosure, for a double-sided substrate, "front side" and similar terms generally refer to the side on which most active circuit elements (such as transistors and other circuits formed from transistors, such as logic gates and memory) are located, while "back side" generally has fewer active circuit elements (if any).

Fig. 4A and 4B are layout diagrams of a semiconductor device 100 according to some embodiments of the present disclosure. The semiconductor device 100 may be fabricated on both sides of a substrate. In the illustrated embodiment, fig. 4A shows the front side and fig. 4B shows the back side.

The semiconductor device 100 includes a plurality of cells. The boundaries of some of the cells in fig. 4A and 4B are represented by dashed rectangles. In some embodiments, these units may form one or more combined units. In the embodiment shown, six units are shown, namely C1, C2, C3, C1', C2' and C3'. The units C1, C2, and C3 are sequentially arranged along the X direction. The units C1', C2', and C3' are sequentially arranged along the X direction. Further, the cells C1', C2', and C3' are image reflections of the cells C1, C2, and C3 along the X-axis.

Taking cells C1-C3 as an example, the boundaries of the cells represent: cell C2 is located in the middle of semiconductor device 100, with cells C1 and C3 immediately adjacent to the opposite boundaries of cell C2. All three cells are shown extending at different widths in the X direction, referred to as the "cell width". Cell C1 has a cell width W1, cell C2 has a cell width W2, and cell C3 has a cell width W3. The cell width W2 may be smaller than the other two cell widths. The height of a cell in the Y direction may be referred to as the "cell height". In the illustrated embodiment, all three cells have a cell height CH. Cells C1-C3 having a cell height CH may form a combined standard cell having a cell height CH that may be repeated (e.g., cells C1', C2', and C3 ') to form a larger layout. In some other embodiments, the cell heights may be different. For example, the cell heights of cells C1 and C3 may be twice the cell height of cell C2.

Referring to fig. 4A, the semiconductor device 100 may have a plurality of elements in different regions. The plurality of elements may include diffusion regions RX, gates GT, metal M0 (metal layer 0), metal MD, and vias (Via). Some elements may form a unit. Conversely, one unit may include a plurality of elements. These elements may form circuits such as transistors, logic, memory, and other circuits that may be fabricated. In various embodiments, the depicted cells C1-C3 are part of a memory device as shown in FIGS. 2 and 3, such as part of the word line driver 24, GSAE circuit 30, or I/O circuit 38 as described above. Note that the semiconductor device 100 may have other elements not shown in fig. 4A and 4B.

The substrate on which the semiconductor device 100 is fabricated may be made of a semiconductor material, such as silicon or germanium or a suitable alloy. The diffusion regions RX may be doped with impurities to change the electrical characteristics of the substrate material. In the illustrated embodiment, the diffusion regions RX extend in the X direction. The diffusion region RX may also be referred to as an active region. The diffusion regions RX may form, for example, source/drain (S/D) regions of a Field Effect Transistor (FET). The type of FET is not limited. For example, planar FETs and finfets, as well as other types of FETs (e.g., full-gate-all (GAA) FETs) may be used for semiconductor device 100. Depending on the context, the source/drain regions may be referred to as sources or drains individually or collectively.

The region indicated by the gate GT may be made of a conductive material such as polysilicon, although this is not a limitation. In some embodiments, the gate GT may include a high-k gate dielectric layer and a metal gate electrode (HKMG). As the name suggests, the gate GT may be used as a gate terminal for various types of transistors (e.g., FETs). In the illustrated embodiment, the gates GT extend in the Y-direction and are uniformly spaced apart from each other along the X-direction. The distance between the centerlines of two adjacent gates GT is denoted as gate pitch P. A FET is formed at the intersection of the gate GT and the diffusion region RX.

The metal MD and the metal M0 are conductive, and although named "metal", may be made of other types of conductive materials. The metal MD may be used as a local interconnect, such as a source/drain contact. In some embodiments, metal MD is located on a layer that is vertically different from the substrate surface and may be used to connect the doped region to other elements of semiconductor device 100, such as metal M0. In some embodiments, the metal MD may extend in the Z-direction; i.e. perpendicular to the X-Y plane.

The metal layer M0 is present on a layer vertically separated from the substrate surface, for example, above the substrate surface. The metal layer M0 may comprise several electrically separate metal lines for distributing the voltages Vdd1 and Vss, respectively, although these metal lines are substantially on the same layer. Depending on the circuit design, vdd1 may be one of a high voltage VddH and a low voltage VddL. Vss provides a ground reference voltage (ground voltage). Not shown in fig. 4A, there may be other metal layers (e.g., M1, M2, … Mx) suspended above the metal layer M0, for example, four to ten total metal layers. These metal layers form the front side power rails to provide voltage from the voltage domain Vdd1 to the semiconductor device 100. In the embodiment shown in fig. 4A, the metal layer M0 includes two metal lines that distribute the voltage Vdd1 extending in the X direction and one metal line that distributes the voltage Vss therebetween. The metal lines are electrically connected to the metal MD through vias. In the illustrated embodiment, the top metal line provides a voltage Vdd1 through Via-v1 to the source/drain regions of the FETs in cell C1 and the source/drain regions of some FETs in cell C2; the bottom metal line provides a voltage Vdd1 through the Via-v1 to the source/drain regions of the FETs in cell C1 'and the source/drain regions of some FETs in cell C2'; and the intermediate metal lines are shared by the cells in the top and bottom rows to provide a voltage Vss through the vias Via-g to the source/drain regions of FETs in cells C1-C3 and C1 '-C3'.

Fig. 4B shows the backside of the substrate on which the semiconductor device 100 is fabricated. The semiconductor device 100 may include a plurality of cells whose positions correspond to the cells already indicated in fig. 4A and boundaries are indicated by dotted rectangles. On the back side, different elements may be present.

Depending on the thickness of the substrate, the diffusion regions RX, which are typically visible from the front side, can also be visible from the back side; the diffusion region RX is thus shown in fig. 4B. In some embodiments, the diffusion region RX cannot be seen from the backside because the doping level near the backside surface is different from near the front side surface and may be closer to the doping level of the undoped portion of the substrate; in this case, the diffusion regions RX are marked in the schematic view of the back side only to indicate mirror positions on the back side of the diffusion regions RX formed on the front side.

In the embodiment shown in fig. 4B, the gate material is typically not fabricated on the backside. Thus, the gate GT in fig. 4B indicates that the gate GT is present in a mirrored position on the front side (see fig. 4A), but does not necessarily mean that the actual gate material (e.g. polysilicon or HKMG) is present on the back side.

A backside metal layer BM0 may be present on the backside of the semiconductor device 100. The backside metal layer BM0 exists on a layer vertically separated from the backside of the substrate. For example, below the backside surface. The back side metal layer BM0 may distribute voltages of different levels. The backside metal layer BM0 may comprise a plurality of electrically separated metal lines for distributing the voltages Vdd2 and Vss, respectively, although these metal lines are substantially on the same layer. Depending on the circuit design, vdd2 may be one of a high voltage VddH and a low voltage VddL in addition to Vdd 1. Vss provides a ground reference voltage (ground voltage). Not shown in fig. 4B, there may be other backside metal layers (e.g., BM1, BM2, … BMy) suspended below the backside metal layer BM0, for example, a total of two to four backside metal layers. These metal layers form the backside supply rail to provide voltage from the voltage domain Vdd2 to the semiconductor device 100. In the embodiment shown in fig. 4B, the back side metal layer BM0 includes two metal lines that distribute the voltage Vdd2 extending in the X direction and two metal lines that distribute the voltage Vss therebetween. The metal lines are electrically connected to the metal MD through backside vias. In the illustrated embodiment, the topmost metal line provides a voltage Vdd2 through via VB-v2 to the source/drain regions of the FETs in cell C3 and the source/drain regions of some FETs in cell C2; the bottom metal line provides a voltage Vdd2 through via VB-v2 to the source/drain regions of the FETs in cell C3 'and the source/drain regions of some FETs in cell C2'; the middle two metal lines supply voltage Vss to the source/drain regions of FETs of the cells C1-C3 of the top row and the cells C1'-C3' of the bottom row, respectively, through vias VB-g.

It is worth noting that even in the described embodiments, the middle two metal lines providing Vss in the back side metal layer BM0 do not overlap in top view with the middle metal lines providing Vss in the front side metal layer M0 (nor do the vias Via-g and VB-g overlap in top view), some of the vias Via-g and VB-g (e.g. Via-g, VB-g in cells C1 and C3) are located on the front and back side of the same source/drain region by metal MD. Thus, the front side and back side metal lines providing Vss are actually electrically connected. That is, the front-side and back-side vias help distribute the voltage Vss to the front and back sides of the semiconductor device 100. Further, since the front side metal line and the back side metal line providing Vss are electrically connected, some cells may provide Vss from the front side metal line alone or from the back side metal line alone. For example, in the depicted embodiment, cell C2 (or C2 ') receives Vdd1 from front side metal layer M0, vdd2 from back side metal layer BM0, but receives Vss only from front side metal layer M0 (e.g., there are no back side vias VB-g in cell C2 (or C2'). Such a configuration provides additional flexibility in power routing.

Fig. 5 is a schematic diagram of a semiconductor device 100 according to some embodiments of the present disclosure. In fig. 5, the metal lines in the front side metal layer M0 and the metal lines in the back side metal layer BM0 are depicted together only for indicating the positions of the various metal lines in the top view of the semiconductor device 100. In the regions of the cells C1-C3 and C1'-C3' as shown in fig. 5, each of the front and back side metal lines extends in the X direction and is spaced apart from each other in a top view without overlapping.

Referring to fig. 5, the semiconductor device 100 includes various types-1, type-2, and type-3 of cells. The type-1 cell operates in a first voltage domain. The type-2 cell operates in a second voltage domain that is different from the first voltage domain. The type-3 cell operates in first and second voltage domains. In some embodiments, the first voltage domain is VddH, the second voltage domain is VddL (VddH > VddL > Vss), and the type-3 cell is a level shifter to transfer signals from the low voltage domain to the high voltage domain (e.g., from the type-3 cell to the type-1 cell). In some embodiments, the first voltage domain is VddL, the second voltage domain is VddH, and the type-3 cell is a level shifter to transfer signals from the low voltage domain to the high voltage domain (e.g., from the type-1 cell to the type-3 cell). In some embodiments, the combination of type-1, type-2, and type-3 cells is part of a memory device as shown in fig. 2 and 3, such as part of the word line driver 24, GSAE circuit 30, or I/O circuit 38, as described above.

A first supply voltage (e.g., vdd 1) and a ground reference voltage (e.g., vss) may be provided to a type-1 cell (e.g., cells C1, C1'). The metal lines in the front side metal layer M0 (and the higher metal lines in M2 … Mx, if present) provide the first power supply voltage Vdd1 and the ground reference voltage Vss through the front side vias. A second supply voltage (e.g., vdd 2) and a ground reference voltage (e.g., vss) may be provided to the type-3 cells (e.g., cells C3, C3'). The metal lines in the backside metal layer BM0 (and the lower metal lines in BM2 … BMy, if present) provide the second power supply voltage Vdd2 and the ground reference voltage Vss through the backside via. The first power supply voltage Vdd1 and the second power supply voltage Vdd2 may be provided to the type-2 cells (e.g., cells C2, C2'). The metal lines in the front side metal layer M0 (and the higher metal lines in M2 … Mx, if present) provide the corresponding first supply voltage Vdd1 through the front side vias, and the metal lines in the back side metal layer BM0 (and the lower metal lines in bm2.. BMy, if present) provide the corresponding second supply voltage Vdd2 through the back side vias. In some embodiments, vdd1 is a high voltage VddH and Vdd2 is a low voltage VddL; however, in some alternative embodiments, vdd1 is a low voltage VddL and Vdd2 is a high voltage VddH, depending on design requirements. In the depicted embodiment, the backside metal lines are wider than the front side metal lines, which reduces the metal wiring resistance on the backside of the semiconductor device 100.

Either the front side metal line or the back side metal line or both may provide the ground reference voltage Vss to the type-2 cell. Further, since the front side metal line and the back side metal line carrying the ground reference voltage Vss are electrically connected, any of the type-1, type-2, and type-3 cells may be directly supplied with the ground reference potential Vss from either the front side metal line or the back side metal line alone or both. For example, the cell C3 (or C3') may be supplied with the second power supply voltage Vdd2 by the back side metal line in the BM0 layer, but with the ground reference voltage Vss by the front side metal line in the M0 layer. Similarly, the cell C1 (or C1') may be supplied with the first power supply voltage Vdd1 by the front side metal line in the M0 layer, but with the ground reference voltage Vss by the back side metal line in the BM0 layer. Such a configuration provides additional flexibility in power routing.

In the embodiment shown in fig. 5, semiconductor device 100 receives Vdd1 alone from the front side metal line and Vdd2 alone from the back side metal line. In an alternative embodiment, the semiconductor device 100 may receive Vdd2 from the backside metal line alone, but Vdd1 from both the front side and backside metal lines. Such an alternative embodiment is shown in fig. 6. Referring to fig. 6, the originally continuous backside metal line in the BM0 layer carrying Vdd2 in fig. 5 is divided into two sections, one section still carrying Vdd2 and the other section carrying Vdd1. In other words, the backside metal lines in the BM0 layer do not extend all the way through the areas of the type-2 and type-1 cells, but remain in the area of the type-3 cell and in the partial area of the type-2 cell adjoining the type-3 cell. The back side metal lines in the BM0 layer in the area of the type-1 cell and the area of the type-2 cell adjoining the type-1 cell replace the bearer Vdd1. Thus, the FETs in the portions of the type-1 and type-2 cells receive Vdd1 from the front and back side metal lines through front and back side vias (vias not shown in fig. 6). By comparison, FETs in the other portions of the type-3 and type-2 cells receive only Vdd2 from the backside metal line. This configuration effectively reduces the resistance of the power supply wiring when the Vdd1 domain is a high voltage domain, and reduces the power dissipated by the power supply rails by powering the FETs from the front and back side power supply rails. The front side metal lines in the M0 layer may still extend through the regions of the type-1, type-2 and type-3 cells as shown in fig. 6.

Fig. 7 illustrates a cross-sectional view of a semiconductor device 100 corresponding to the layout in fig. 5, in accordance with some embodiments. The semiconductor device 100 includes a front side interconnect structure formed on a front side of a substrate. The FET is formed on the front side of the substrate. The front side interconnect structure includes a front side metal layer M0.. In some embodiments, the front side interconnect structure includes four to ten metal layers. Metal lines and vias in the front side interconnect structure provide the front side power rails. The semiconductor device 100 also includes a backside interconnect structure on the backside of the substrate. The backside interconnect structure includes a backside metal layer bm0.. BMy. In some embodiments, the backside interconnect structure includes two to four metal layers. In some embodiments, the number of metal layers in the backside interconnect structure is less than the front side. Metal lines and vias in the backside interconnect structure provide backside power rails.

The semiconductor device 100 further includes package bumps 120. The package bumps 120 provide electrical connection between the semiconductor device 100 and an external power source. In other words, voltages of different voltage domains (e.g., vddH, vddL, and Vss) are introduced into the semiconductor device 100 from the package bumps 120. In the illustrated embodiment, the package bumps 120 are deposited on the backside of the semiconductor device 100. Thus, voltages from different voltage domains are first transferred from the package bumps 120 to the backside power rail, and some voltages are further transferred from the backside power rail to the front side power rail through power taps extending through the substrate. Alternatively, the package bump 120 may be deposited on the front side of the semiconductor device 100. Thus, voltages from different voltage domains are transferred from the package bumps 120 to the front side power rail, and some of the voltages are further transferred from the front side power rail to the back side power rail through power taps extending through the substrate. Whether the package bumps 120 are disposed on the front side or the back side of the semiconductor device 100 may depend on design requirements.

Still referring to fig. 7, diffusion regions RX are formed in the substrate. The stacked gate material GT, indicated as small rectangles within the diffusion region RX, indicates a gate implemented in a full-gate-all-around (GAA) FET. However, it is also possible to implement FETs in other types of FETs, such as planar FETs and finfets. Source/drain (S/D) regions are formed in the diffusion regions RX and interposed between adjacent gates GT. In some embodiments, the source/drain regions are formed of doped epitaxial features.

In the illustrated embodiment, to pass the voltage Vdd1 from the back side power rail to the front side power rail, a conductive path is provided between the back side metal line in BM0 and the front side metal line in M0. The conductive path includes a backside Via VB-v1, a source/drain region in contact with the backside Via VB-v1, a source/drain contact MD in contact with the source/drain region, and a front side Via Via-v1 in contact with the source/drain contact MD. The conductive path is also referred to as a power tap. The power tap pitch D (distance between two adjacent power taps) may be in the range of about 20 to 40 times the gate pitch P (fig. 4A). The range is not arbitrary. If the power tap pitch D is less than 20 times the gate pitch P, the space between the two power taps may be insufficient to layout functional units (e.g., type-1, type-2, and type-3 units). If the power tap pitch D is greater than 40 times the gate pitch P, the number of power taps may be insufficient and the resistance of the Vdd1 voltage domain may be too large. In the illustrated embodiment, the power taps are located outside the area housing the type-1, type-2, and type-3 cells. Alternatively, the power tap may be part of the area housing the type-1, type-2, and type-3 cells. In the embodiment shown in fig. 7, the backside metal lines carrying Vdd1 and the backside vias therebetween in bm0. BMy form islands of voltage domain Vdd1, separated from the other portions of the backside power rail carrying Vdd2, without powering any functional units from the backside of semiconductor device 100.

In the illustrated embodiment, between the power taps, the cells of type-1, type-2, and type-3 are placed side by side. The type-2 cell acts as a level shifter between the type-1 cell and the type-3 cell. The front side metal line in the M0 layer passes Vdd1 to a portion of the type-1 and type-2 cells. The backside metal lines in the BM0 layer (which are not part of the power taps) receive Vdd2 from the package bumps 120 and pass Vdd2 to the other parts of the type-3 and type-2 cells. As described above, the front side metal lines and the back side metal lines do not overlap in a top view of the area accommodating the type-1, type-2, and type-3 cells. For illustration purposes, fig. 7 covers the front side metal lines and the back side metal lines in one cross-sectional view.

Fig. 8 shows a different configuration of the power tap for the embodiment in fig. 7. Unlike the power tap of fig. 7, the source/drain regions are not present in the power tap of fig. 8. The depicted power tap includes a backside Via VB-v1, a metal MD contacting the backside Via VB-v1, and a front side Via Via-v1 contacting the metal MD. The metal MD extends through the substrate. In some embodiments, the metal MD is a through-substrate via (TSV).

Fig. 9 illustrates a cross-sectional view of a semiconductor device 100 corresponding to the layout in fig. 6, in accordance with some embodiments. For clarity and consistency reasons, similar elements appearing in fig. 9 are labeled the same as in fig. 7, and the details of these elements need not be repeated again below. One difference between the embodiments in fig. 7 and 9 is that in fig. 9 the originally continuous backside metal line in the BM0 layer carrying Vdd2 is divided into two sections, one section still carrying Vdd2 and the other section carrying Vdd1. In other words, the backside metal lines in the BM0 layer do not extend all the way through the areas of the type-2 and type-1 cells, but remain in the area of the type-3 cell and in a part of the area of the type-2 cell adjoining the type-3 cell. The back side metal lines in the BM0 layer in the area of the type-1 cell and in a part of the area of the type-2 cell adjoining the type-1 cell replace the bearer Vdd1. The power tap may fall directly on the backside metal line in the BM0 layer carrying Vdd1. Thus, FETs in a portion of the type-1 and type-2 cells receive Vdd1 from the front and back metal lines through the front-side Via Via-v1 and the back-side Via VB-v 1. By comparison, FETs in the other portions of the type-3 and type-2 cells receive Vdd2 from the backside metal line only through the backside via VB-v 2. This configuration effectively reduces the resistance of the power supply wiring when the Vdd1 domain is a high voltage domain, and reduces the power dissipated by the power supply rails by powering the FETs from the front and back side power supply rails. The front side metal lines in the M0 layer may still extend through the regions of the type-1, type-2 and type-3 cells as shown in fig. 9.

Fig. 10 shows a different configuration of the power tap for the embodiment in fig. 9. Unlike the power tap of fig. 9, the source/drain regions are not present in the power tap of fig. 10. The depicted power tap includes a backside Via VB-v1, a metal MD contacting the backside Via VB-v1, and a front side Via Via-v1 contacting the metal MD. The metal MD extends through the substrate. In some embodiments, the metal MD is a through-substrate via (TSV).

By forming the backside power rails, it becomes more feasible to distribute voltages from multiple voltage domains to different regions of the semiconductor device at the cell level (e.g., between cells C1-C3) or at the transistor level (e.g., within cell C2). The power supply wiring is simplified and the resistance in the power supply rail is also reduced, which results in reduced power dissipated in the power supply rail and reduced leakage power in the semiconductor device. Further, embodiments of the present disclosure may be easily integrated into existing semiconductor manufacturing processes.

In one exemplary aspect, the present disclosure relates to a semiconductor device. The semiconductor device includes: a plurality of transistors formed in the substrate, the plurality of transistors forming at least a first cell operating at a first power supply voltage and a second cell operating at a second power supply voltage different from the first power supply voltage; a front side power rail disposed on a front side of the substrate, the front side power rail providing a first power voltage to the first unit; and a backside power rail disposed on a backside of the substrate, the backside power rail providing a second power voltage to the second unit. In some embodiments, the semiconductor device further comprises: a package bump that supplies a first power supply voltage and a second power supply voltage to the semiconductor device; and a power tap contacting the front side power rail and electrically coupling the front side power rail to a portion of the package bump that provides the first power voltage. In some embodiments, the pitch of the power supply taps is about 20 times to about 40 times the pitch of the gate structures in the plurality of transistors. In some embodiments, one of the power taps includes a source/drain feature, a source/source contact disposed on the source/drain feature, and a backside via disposed below the source/drain feature. In some embodiments, one of the power taps includes a through-substrate via and a backside via in contact with the through-substrate via. In some embodiments, the plurality of transistors further forms a third cell that operates at the first power supply voltage and the second power supply voltage, wherein the front side power supply rail provides the first power supply voltage to the third cell and the back side power supply rail provides the second power supply voltage to the third cell. In some embodiments, the third cell is located between the first cell and the second cell and functions as a level shifter. In some embodiments, the backside power rail is further configured to provide a first power supply voltage to the first cell. In some embodiments, the front side power rail includes a first front side metal line providing a first power supply voltage and a second front side metal line parallel to the first front side metal line and providing a ground reference voltage, the back side power rail includes a first back side metal line providing a second power supply voltage and a second back side metal line parallel to the first back side metal line and providing the ground reference voltage, and the first back side metal line and the second back side metal line are sandwiched between the first front side metal line and the second front side metal line. In some embodiments, the first backside metal line and the second backside metal line are wider than the first front side metal line and the second front side metal line.

In another exemplary aspect, the present disclosure is directed to a semiconductor device. The semiconductor device includes: a plurality of active regions formed on the substrate, each active region extending longitudinally in a first direction; a plurality of gate structures disposed over the active region, each gate structure extending longitudinally in a second direction perpendicular to the first direction; a first front side metal line disposed above the gate structure and extending longitudinally in a first direction, the first front side metal line carrying a first power supply voltage; a second front side metal line disposed over the gate structure and extending longitudinally in the first direction, the second back side metal line carrying a ground reference voltage; a first backside metal line disposed below the substrate and extending longitudinally in a first direction, the first backside metal line carrying a second power supply voltage different from the first power supply voltage; and a second backside metal line disposed under the substrate and extending longitudinally in the first direction, the second backside metal line carrying a ground reference voltage. In some embodiments, the first backside metal line and the second backside metal line are disposed between the first front side metal line and the second front side metal line in a top view. In some embodiments, the first backside metal line, the second backside metal line, the first front side metal line, and the second front side metal line do not overlap in a top view. In some embodiments, the active region includes a first source/drain region and a second source/drain region, and wherein the first front side metal line is electrically coupled to the first source/drain region and the first back side metal line is electrically coupled to the second source/drain region. In some embodiments, the active region further comprises a third source/drain region, and wherein the second front side metal line and the second back side metal line are both electrically coupled to the third source/drain region. In some embodiments, the semiconductor device further includes a third backside metal line disposed below the substrate and extending longitudinally in the first direction, the third backside metal line carrying the first supply voltage. In some embodiments, the active region includes a source/drain region, and wherein the first front side metal line and the third back side metal line are both electrically coupled to the source/drain region.

In another exemplary aspect, the present disclosure is directed to a level shifting circuit. The level shift circuit includes: a plurality of transistors configured to convert a signal of a first voltage level to a second voltage level higher than the first voltage level; a front side power line disposed over the transistor, the front side power line transmitting a first voltage level to a first source/drain region of the transistor; and a backside power line disposed below the transistor, the backside power line transmitting a second voltage level to a second source/drain region of the transistor. In some embodiments, the width of the backside power line is greater than the width of the front side power line. In some embodiments, the level shifting circuit further includes another backside power line disposed below the transistor and configured to transmit the first voltage level to a first source/drain region of the transistor.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A semiconductor device, comprising:

a plurality of transistors formed in a substrate, the plurality of transistors forming at least a first cell operating at a first power supply voltage and a second cell operating at a second power supply voltage different from the first power supply voltage;

a front side power rail disposed on a front side of the substrate, the front side power rail providing the first power voltage to the first unit; and

a backside power rail disposed on a backside of the substrate, the backside power rail providing the second power voltage to the second cell.

2. The semiconductor device of claim 1, further comprising:

a package bump that supplies the first power supply voltage and the second power supply voltage to the semiconductor device; and

a power tap contacts the front side power rail and electrically couples the front side power rail to a portion of the package bump that provides the first power supply voltage.

3. The semiconductor device of claim 2, wherein a pitch of the power supply tap is about 20 times to about 40 times a pitch of gate structures in the plurality of transistors.

4. The semiconductor device of claim 2, wherein one of the power taps comprises a source/drain feature, a source/source contact disposed on the source/drain feature, and a backside via disposed below the source/drain feature.

5. The semiconductor device of claim 2, wherein one of the power taps comprises a through-substrate via and a backside via in contact with the through-substrate via.

6. The semiconductor device of claim 1, wherein the plurality of transistors further form a third cell that operates at the first and second supply voltages, wherein the front side supply rail provides the first supply voltage to the third cell and the back side supply rail provides the second supply voltage to the third cell.

7. The semiconductor device according to claim 6, wherein the third cell is located between the first cell and the second cell and functions as a level shifter.

8. The semiconductor device of claim 1, wherein the backside power rail is further configured to provide the first power supply voltage to the first cell.

9. A semiconductor device, comprising:

a plurality of active regions formed on the substrate, each of the active regions extending longitudinally in a first direction;

a plurality of gate structures disposed over the active region, each gate structure extending longitudinally in a second direction perpendicular to the first direction;

A first front side metal line disposed above the gate structure and extending longitudinally in the first direction, the first front side metal line carrying a first supply voltage;

a second front side metal line disposed over the gate structure and extending longitudinally in the first direction, the second back side metal line carrying a ground reference voltage;

a first backside metal line disposed below the substrate and extending longitudinally in the first direction, the first backside metal line carrying a second power supply voltage different from the first power supply voltage; and

a second backside metal line disposed below the substrate and extending longitudinally in the first direction, the second backside metal line carrying the ground reference voltage.

10. A level shifting circuit, comprising:

a plurality of transistors configured to convert a signal of a first voltage level to a second voltage level higher than the first voltage level;

a front side power supply line disposed over the transistor, the front side power supply line delivering the first voltage level to a first source/drain region of the transistor; and

a backside power line disposed below the transistor, the backside power line delivering the second voltage level to a second source/drain region of the transistor.