JP2008021589A - Capacity adjustment device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacity adjustment device capable of shortening capacity adjustment time. <P>SOLUTION: In the capacity adjustment device in which capacity adjustment of a plurality of cells C1 to C3 constituting a battery pack is carried out by a prescribed capacity adjustment electric current value and in which fluctuations of charging capacity between the cells is adjusted, CPU103 sets capacity adjustment ability improvement request according to a state of the battery pack (for example, cell voltage distribution state, and using time proportion and capacity deterioration coefficient of battery pack). Then, a prescribed capacity adjustment current value is changed based on the capacity adjustment ability improvement request, and capacity adjustment circuits 12, 22, 33 carry out capacity adjustment by the changed capacity adjustment current value. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a battery capacity adjustment device used in an electric vehicle such as an electric vehicle or a hybrid vehicle.

  Conventionally, a capacity adjustment method for an assembled battery in which a plurality of cells are connected in series is known (see, for example, Patent Document 1). In the conventional capacity adjustment method, a capacity adjustment target and a capacity adjustment time are determined for each cell in accordance with the cell voltage distribution state at the time of no load, and discharging is performed at a specified current value.

JP 2003-215495 A

  However, since the conventional technology discharges at a specified current value, the capacity is adjusted quickly, for example, when the cell capacity varies greatly or when the vehicle usage time is extremely short. In some cases, the capacity adjustment time is long and the system may be turned off before the capacity adjustment is completed. Therefore, there has been a problem that capacity adjustment cannot be performed sufficiently.

  The present invention is applied to a capacity adjustment device that adjusts the capacity of a plurality of cells constituting an assembled battery with a predetermined capacity adjustment current value, and adjusts the variation in charging capacity between cells, and is determined according to the state of the assembled battery. Setting means for setting the adjustment capacity improvement degree for capacity adjustment with the capacity adjustment current value, and the capacity for changing the predetermined capacity adjustment current value based on the adjustment capacity improvement degree and performing capacity adjustment with the changed capacity adjustment current value And adjusting means.

  According to the present invention, according to the state of the assembled battery, the adjustment capacity improvement degree for the capacity adjustment at the predetermined capacity adjustment current value is set, and the capacity adjustment is performed with the capacity adjustment current value changed based on the adjustment capacity improvement degree. As a result, the capacity adjustment capability is improved and the capacity adjustment time can be shortened.

Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings.
-First embodiment-
FIG. 1 is a diagram showing a first embodiment of a capacity adjusting apparatus according to the present invention, and shows a case where the capacity adjusting apparatus is applied to an EV (electric vehicle) capacity adjusting apparatus. In FIG. 1, a thick solid line indicates a high-power line, a thin solid line indicates a low-power line, and a dotted line indicates a signal line. The capacity adjustment device according to the present invention is not limited to the EV, but can be applied to HEV (hybrid vehicle), FCV (fuel cell vehicle), etc., and the battery-related configuration is the same as that shown in FIG.

  The control system shown in FIG. 1 includes a battery control unit 1 and a vehicle system 3 provided with an assembled battery 2. The battery control unit 1 includes a cell voltage detection unit 101, a capacity adjustment unit 102, a CPU 103, a memory 104, and the like, and performs charge / discharge control and capacity adjustment control of the assembled battery 2 provided in the vehicle system 3. The assembled battery 2 has a plurality of cells connected in series, and the voltage of each cell is detected by the cell voltage detector 101. The voltage information of each cell detected by the cell voltage detection unit 101 is transmitted to the CPU 103.

  The CPU 103 issues an appropriate capacity adjustment instruction to the capacity adjustment unit 102 based on the voltage status (voltage distribution status) of each cell after no load (when the vehicle system is activated) and after charging the specified capacity. When the capacity adjustment is interrupted due to the vehicle system being turned off, the CPU 103 stores the remaining adjustment conditions in the memory 104 for each cell. The capacity adjustment unit 102 corrects capacity variation between cells by performing capacity adjustment in units of cells. Details of the capacity adjustment unit 102 will be described later. The memory 104 stores information necessary for charge / discharge control and capacity adjustment control, information from the CPU 103, and the like.

  The assembled battery 2 is connected to the inverter 301 and the auxiliary machine system 302 via the main relays 303a and 303b, and supplies DC power to the inverter 301 and the auxiliary machine system 302. By turning on and off the main relays 303a and 303b based on a command from the CPU 103, the power on / off of the high voltage circuit is controlled. The inverter 301 converts the DC power of the assembled battery 2 into AC power and applies it to the driving motor M, and drives the motor M to run the vehicle. The drive motor M functions as a generator during regenerative control, supplies regenerative power to the assembled battery 2 via the inverter 301, and charges the assembled battery 2.

  The vehicle system CPU 304 controls the vehicle system 3, and the inverter 301 and the auxiliary system 302 are controlled by the vehicle system CPU 304. The auxiliary machine system 302 includes an air conditioning system installed in the vehicle and is driven by the electric power of the assembled battery 2. The current sensor 201 monitors the current flowing through the high power circuit of the vehicle system 3 and transmits the information to the CPU 103 of the battery control unit 1.

  The voltage sensor 202 monitors the potential difference between both ends of the assembled battery 2 and transmits the information to the CPU 103. The temperature sensor 203 monitors the temperature of the assembled battery 2 and transmits the temperature information to the CPU 103. The SOC (State Of Charge) of the assembled battery 2 is obtained by referring to a correlation table between the total voltage of the assembled battery 2 and the SOC. In this case, the detected value of the voltage sensor 203 may be used as the total voltage. The sum of the cell voltages detected by the cell voltage detection unit 101 may be used. The correlation table is stored in the memory 104.

  The auxiliary battery 401 is a power source for the CPU 103 and the vehicle system CPU 304, and a switch 403 for turning on / off the power source is turned on / off by an ignition signal 402. The ignition signal 402 is input in conjunction with the on / off of the ignition switch of the vehicle. The history of the ignition signal 402, that is, the on / off history of the switch 403 is stored in the memory 104, and is used to calculate the usage time described later. When an abnormality occurs in the vehicle system 3, the vehicle system CPU 304 turns on the warning lamp 305 to notify the driver of the occurrence of the abnormality.

  FIG. 2 is a diagram showing details of the capacity adjustment unit 102, and shows three cells among a plurality of cells provided in the assembled battery 2. The capacity adjustment unit 102 performs capacity adjustment independently for each of the cells C1 to C3, and each cell C1 to C3 includes a capacity adjustment circuit 12 including a capacity adjustment resistor R10 and an FET 11 as a control switch. , 22, 32 are provided in parallel. By controlling the on / off of the FET 11, the duty ratio, which is the ratio of the energization time of the capacity adjustment resistor R10, is controlled to variably control the capacity adjustment current.

  Each FET 11 is ON / OFF controlled independently by a signal from the CPU 103. The capacity adjustment circuits 12, 22, and 32 turn on the FET 11 to cause the current to flow through the capacity adjustment resistor R10, thereby discharging the cells C1 to C3, and adjust the capacity of the cells C1 to C3. Here, an FET is used as the switching element, but a transistor or the like may be used. As will be described later, the CPU 103 performs duty control on the FET 11 in accordance with the required level of capacitance adjustment.

  FIG. 3 is a flowchart showing an example of capacity adjustment control in the present embodiment. In step S11, after the ignition signal is detected and before the main relays 303a and 303b are turned on, the cell voltage detector 101 detects the open voltage of each cell. In step S12, the CPU 103 calculates an average cell voltage and a cell voltage standard deviation based on the cell voltage detected in step S11, and calculates a difference between the average cell voltage and the lowest cell voltage.

  In step S <b> 13, the CPU 103 obtains the system activation time and the non-energization time when the switch 403 is off based on the on / off history of the switch 403 stored in the memory 104, and calculates the system usage time ratio. . The system usage time ratio is a ratio between the system startup time and the total usage time (= system startup time + non-energization time), and is an index corresponding to the usage time of the assembled battery. In step S14, a capacity deterioration coefficient (= current capacity / new capacity) indicating the capacity deterioration state of the assembled battery 2 is checked. For example, the capacity deterioration coefficient is obtained from the difference between the voltage value estimated from the change in capacity obtained from the charge / discharge integration (the voltage value calculated assuming that the battery is new) and the actually detected voltage value. be able to.

  In step S15, the capacity adjustment capability improvement request level is calculated based on the data collected in steps S12 to S14. Here, the capacity adjustment capability improvement request levels k1 to k3 are calculated for each data, and the final capacity adjustment capability improvement request level k is calculated based on the calculated request levels k1 to k3. FIG. 4 is a diagram illustrating an example of the capacity adjustment capability improvement request level k1 based on the data obtained in step S12. The horizontal axis represents the difference between the average cell voltage and the minimum cell voltage, and the vertical axis represents the cell voltage standard deviation. The map of the required degree k1 at the time is shown. That is, the required degree k1 (≧ 1) is set by a combination of the difference and the cell voltage standard deviation.

  Each of the lines L1 to L5 indicates a line having the same required degree. For example, all points (difference, cell voltage standard deviation) on the line L1 have the same required degree k1 (L1). Since the variation in the self-discharge amount of each cell is large, a state occurs in which the charge capacity of some cells is considerably lower than other cells, but the map shown in FIG. 4 quickly eliminates such a state. This is a map with particular emphasis. The required levels k1 (L1) to k1 (L5) of the lines L1 to L5 are set such that k1 (L1) <k1 (L2) <k1 (L3) <k1 (L4) <k1 (L5).

  FIG. 8 qualitatively shows the states of the points P1 and P2 in FIG. FIG. 8 (a) shows the cell voltage distribution at the point P1 on the line L2 with the required level k2 (L2). Many cells are distributed around the average cell voltage, and the cell with the lowest cell voltage is below that. There is one. Black circles represent the number of cells. On the other hand, FIG. 8B shows the cell voltage distribution at the point P1 on the line L2 of the required degree k2 (L2). In this case, the difference between the average cell voltage and the minimum cell voltage is the same as that shown in FIG. 8A. However, since the cell standard deviation at the point P2 is smaller than the point P1, it is more near the average cell voltage. Cells are distributed in a narrow voltage range. Therefore, k1 (L2) <k1 (L3) is set.

  FIG. 5 is a diagram illustrating an example of the capacity adjustment capability improvement request level k2 based on the data obtained in step S13, where the vertical axis indicates the capacity adjustment capability increase request level k2 and the horizontal axis indicates the system usage time ratio. . When the system usage time ratio is small, the capacity adjustment opportunities are reduced, so the capacity adjustment capability improvement request level k2 is set larger so that the capacity adjustment is completed in a short time. When the system usage time ratio is greater than or equal to a predetermined value, capacity adjustment is performed with a specified adjustment capability (specified capacity adjustment current value).

  FIG. 6 is a diagram illustrating an example of the capacity adjustment capability improvement request level k3 based on the data obtained in step S14. The vertical axis represents the capacity adjustment capability improvement request level k3, and the horizontal axis represents the capacity deterioration coefficient (%). ing. Since the capacity adjustment time is calculated on the assumption that the assembled battery 2 is new, if the capacity is reduced due to deterioration, it is necessary to reduce the capacity adjustment current accordingly. Otherwise, excessive adjustments will be made.

  For example, when the capacity deterioration coefficient is 80%, the capacity adjustment capability improvement requirement k3 is set to 0.8. The capacity adjustment capability improvement request level k3 is 1 or less, and the capacity adjustment capability is requested to decrease as the capacity deterioration coefficient (%) increases. Therefore, the capacity adjustment capability improvement request level k1, k1, k2 ≧ 1. It can be considered as a correction coefficient that suppresses the degree of improvement due to k2.

Thus, if each capacity adjustment capability improvement request | requirement k1-k3 is obtained, the final capacity adjustment capability improvement request | requirement k will be calculated | required by following Formula.
k = k1 × k2 × k3

  Returning to FIG. 3, in step S16, the capacity adjustment current to be passed through the capacity adjustment resistor R10 of the capacity adjustment circuits 12, 22, and 32 is determined based on the capacity adjustment capability improvement requirement k calculated in step S15. Set to “adjusted current value × k”. Here, the ratio (duty) in which the FET 11 is turned on is changed so that the capacity adjustment current value = the specified capacity adjustment current value × k. FIG. 7 is a diagram showing the relationship between the capacity adjustment capability improvement request level k and the duty of the FET 11, and the duty ratio increases as the request level k increases. In the present embodiment, the specified capacity adjustment current is individually set according to the charge capacity of each cell. Therefore, the capacity adjustment current value that is an integrated value of the specified capacity adjustment current and the capacity adjustment capability improvement requirement k is also set for each cell. Will be set.

  In step S17, capacity adjustment is started with the capacity adjustment current value set for each cell in step S16. In step S18, it is determined for each cell whether or not capacity adjustment has been completed, that is, whether or not the set adjustment time has been reached. If capacity adjustment has been completed for all the cells, a series of capacity adjustment is performed. The process ends. If the capacity adjustment current value of each cell is set so that the capacity adjustment time is the same between cells, the determination in step S18 may not be performed for each cell.

-Second Embodiment-
FIG. 9 is a diagram showing a second embodiment of the capacity adjustment device according to the present invention, and shows the details of the capacity adjustment unit 102 similar to FIG. In the capacitance adjustment unit 102 shown in FIG. 2, the current flowing through the capacitance adjustment resistor R10 is adjusted by controlling the duty of the FET 11. However, in the second embodiment, a plurality of capacitance adjustment capability improvement requests k are set according to a plurality of requirements. The capacitance adjustment current value was changed discretely by selecting and using some of the resistors.

In the example shown in FIG. 9, each of the capacitance adjusting circuits 12, 22, and 32 is provided with three resistors R1A, R1B, and R1C in parallel, and the resistance value is changed by switching with the switch SW1. did. For example, if the resistance values of the resistors R1A, R1B, and R1C are set to 5 kΩ, 10 kΩ, and 10 kΩ in order, the following four types of resistance selection patterns are set by changing the method of selecting the resistor to be used using the switch SW1. can do.
(1) Resistance selection pattern a: 2.5kΩ (R1A, R1B, R1C),
(2) Resistance selection pattern b: 3.3kΩ (R1A, R1B or R1A, R1C),
(3) Resistance selection pattern c: 5kΩ (R1B, R1C or R1A),
(4) Resistance selection pattern d: 10kΩ (R1B or R1C)

  Then, as shown in FIG. 10, control is performed so that a resistance selection pattern having a smaller resistance value is used as the capacity adjustment capability improvement requirement k increases. That is, in the first embodiment, the current value is changed by changing the duty of the FET 11 in step S16 of FIG. 3, but in the second embodiment, the plurality of resistors are used to meet the required degree k. The difference is that the current value is changed by selecting a resistor. In this case, the resistance value changes stepwise according to the capacity adjustment capability improvement request level k. Other processes are the same as those shown in FIG.

  FIG. 11 is a flowchart illustrating another control method according to the second embodiment. In the control method shown in FIG. 11, the resistance selection pattern is switched so that the calorific values of the capacitance adjusting resistors R1A to R1C are uniform on the control circuit. Steps having the same reference numerals as those in the flowchart shown in FIG. 3, that is, steps S11 to S17 and step S18, perform exactly the same processing as described in FIG. Here, different processing will be mainly described.

  In step S17, capacity adjustment is started. In a succeeding step S100, it is determined whether or not a predetermined switching time has elapsed since the start of the capacity adjustment based on a timer included in the CPU 103. If it is determined in step S100 that the time has elapsed, the process proceeds to step S101 to switch the resistance selection pattern. In this case, it is preferable to switch so that the resistance values before and after switching are the same.

  For example, in the above-described example, the resistance selection pattern b has two combinations of the resistance selection pattern b1 = R1A + R1B and the resistance selection pattern b2 = R1A + R1C. Therefore, the selection may be performed as b1 → b2 or b2 → b1. Since there are two combinations for the resistance selection pattern d, the same can be considered. The switching of the resistance selection pattern in step S101 is performed for all of the capacitance adjustment circuits. If the switching process of step S101 is completed, the process proceeds to step S18 to determine whether or not the capacity adjustment is completed, and if not completed, the process returns to step S100.

  In the above description, the time from the start of capacitance adjustment is adopted as the time to be compared with the specified switching time. However, the time from the previous resistance selection pattern switching time may be used.

  FIG. 12 is a diagram illustrating another control example in the case of using a plurality of resistors. The control flow shown in FIG. 12 shows processing when an abnormality occurs in the capacity adjustment circuits 12, 22, and 32, and is executed in parallel with the control flow shown in FIG.

  In step S200, it is determined whether or not a resistance abnormality has occurred in the capacity adjustment circuits 12 to 32. If it is determined that there is an abnormality, the process proceeds to step S201, and if it is determined that no abnormality has occurred, the process proceeds to step S204. . In step S201, in the capacity adjustment circuit in which an abnormality has occurred, it is determined whether or not it can be replaced with another resistor instead of the disabled resistor. If it is determined in step S201 that substitution is not possible, the process proceeds to step S206 to stop the capacity adjustment. Further, in step S207, the warning lamp 305 (see FIG. 1) is turned on, and the series of processing ends. On the other hand, if it is determined in step S201 that substitution is possible, the process proceeds to step S202, and a difference in capacity adjustment capability associated with resistance substitution is checked.

For example, consider the case where capacity adjustment is started with the following settings.
・ Capacitance adjustment circuit 12: Resistance selection pattern a (R1A, R1B, R1C), resistance value = 2.5 kΩ
・ Capacitance adjustment circuit 22: Resistance selection pattern c (R1B, R1C), resistance value = 5 kΩ
・ Capacitance adjustment circuit 32: Resistance selection pattern c (R1B, R1C), resistance value = 5 kΩ
When the resistor R1A of the capacitance adjustment circuit 12 becomes unusable during the capacitance adjustment, the resistance selection pattern c is switched to not using the resistor R1A. As a result, the resistance value changes twice, so that the current flowing through the capacitance adjustment circuit 12 is halved.
・ Capacitance adjustment circuit 12: Resistance selection pattern c (R1B, R1C), resistance value = 5 kΩ

  As described above, when the current flowing through the capacitance adjustment circuit 12 is changed by changing the resistance selection pattern, the balance of the capacitance adjustment capability between the capacitance adjustment circuits 12 to 32 is changed, and the capacitance adjustment is interrupted midway. In this case, capacity variation occurs between the cells C1 to C3. Therefore, in step S203, the resistance selection pattern of the capacitance adjustment circuits 22 and 32 is changed in accordance with the change in the current flowing through the capacitance adjustment circuit 12 due to the change in resistance, and the current flowing through the capacitance adjustment circuits 22 and 32 is changed. Adjust the balance.

For example, when the current flowing through the capacitance adjustment circuit 12 is halved, the resistance selection pattern is changed so that the current flowing through the capacitance adjustment circuits 22 and 32 is also halved. In the case of the above-described example, if the resistance selection pattern is changed to the following, the current flowing through each capacitance adjusting circuit 22 and 32 is also halved.
・ Capacitance adjustment circuit 12: Resistance selection pattern c (R1B, R1C), resistance value = 5 kΩ
・ Capacitance adjustment circuit 22: Resistance selection pattern d (R1B), resistance value = 10 kΩ
・ Capacitance adjustment circuit 32: resistance selection pattern d (R1B), resistance value = 10 kΩ

  In the above-described example, a combination of resistors in which the resistance values of the capacitance adjustment circuits 22 and 32 are doubled is found, but there is not always a combination in which the value is exactly doubled. In such a case, it is only necessary to select a combination of resistors so that the balance between the cells is not lost as much as possible. If the process of step S203 is completed, the process proceeds to step S204 to continue the capacity adjustment. In step S205, it is determined whether or not capacity adjustment has been completed. If capacity adjustment has been completed for all cells, a series of capacity adjustment processing ends.

  FIG. 13 shows a comparison between the control shown in FIG. 12 and the conventional control, and is a diagram showing temporal changes in capacity adjustment status, capacity adjustment time, and the like. In FIG. 13, (a) relates to the conventional capacity adjustment, and (b) shows a case where the control flow shown in FIG. 12 is adopted. In the case of conventional control, since a plurality of capacitance adjustment resistors are not provided, if the capacitance adjustment resistor becomes unusable due to a failure, the capacitance adjustment operation has to be interrupted at that time.

  On the other hand, in the present embodiment, since a plurality of capacitance adjustment resistors are provided and selected from among them, the capacitance adjustment operation can be continued as shown in FIG. 13 even if a failure occurs. it can. If the capacitance adjustment current changes when the resistance selection pattern is changed, the target capacitance variation adjustment can be achieved by changing the capacitance adjustment time accordingly.

The effects of the embodiment described above are summarized as follows.
(1) The capacity adjustment capability improvement request level k for capacity adjustment at the specified capacity adjustment current value is set according to the state of the assembled battery 2, and the capacity adjustment capability improvement request level k is set to the preset specified capacity adjustment current value. Since the capacity adjustment is performed with the capacity adjustment current value multiplied by (adjustment ability improvement degree), the capacity adjustment current can be set to an optimum value according to the state of the assembled battery 2, and the capacity adjustment ability is improved. Thus, the capacity adjustment time can be shortened and the capacity adjustment accuracy can be improved.
(2) The state of the assembled battery 2 includes the cell voltage distribution status of the assembled battery 2, the usage time of the assembled battery 2, the capacity deterioration status, and the like. The capacity adjustment capability can be appropriately increased while reliably avoiding the discharge.

(3) Capacitance adjustment includes a method in which a capacitance adjustment resistor R10 is connected in parallel to each of the cells C1 to C3, and the capacitance adjustment current flowing through the capacitance adjustment resistor R10 is duty controlled by the FET 11, or each cell C1 to C3 There is a method of connecting resistance circuits having variable resistance values in parallel. As shown in FIG. 9, the resistor circuit has a configuration in which a plurality of capacitance adjusting resistors R1A to R1C are provided, and at least one of them is selected by a switch SW1 and connected in parallel to a cell. As shown in FIG. 14, the switch SW10 may be switched to switch between the case of only the resistor R1A and the case of connecting the resistor R1B to the resistor R1A in series.

(4) When a plurality of capacitance adjustment resistors R1A to R1C are provided and used as shown in FIG. 9, a plurality of capacitance adjustment resistor selection patterns having the same resistance value can be set. As a result, by switching the capacitance adjustment resistor selection pattern when a predetermined time elapses during the capacitance adjustment, it is possible to adjust the bias of the temperature distribution in the resistance circuit to be uniform, and the circuit board temperature rises locally. In addition, the device life can be improved.
(5) If at least one of the selected capacitance adjustment resistors is not usable, another capacitance adjustment resistor may be substituted by changing the resistance selection pattern. By doing so, the capacity adjustment operation can be continued even when the capacity adjustment resistor becomes unusable during capacity adjustment. In that case, by making the resistance value the same before and after the selection pattern change, it is possible to prevent the capacity adjustment capability from being lowered. Furthermore, the balance of the capacity adjustment current can be maintained by selecting and changing the capacity adjustment resistor for each cell so that the ratio of the capacity adjustment current between the cells C1 to C3 is substantially the same. As a result, even when the capacity adjustment is interrupted in the middle, the capacity variation can be suppressed low.
(6) Also, by setting the capacity adjustment amount for each cell based on the charge capacity of each cell, the cell voltage variation can be eliminated with high accuracy and efficiency.

  In the correspondence between the embodiment described above and the elements of the claims, the CPU 103 is a setting means, the switches SW1 and SW10 are selection means, the CPU 103 and the capacity adjustment circuits 12, 22, and 32 are capacity adjustment means, and the FET 11 Constitutes a current control element, and the capacity adjustment capability improvement request level constitutes an adjustment capability improvement level. The above description is merely an example, and when interpreting the invention, there is no limitation or restriction on the correspondence between the items described in the above embodiment and the items described in the claims.

It is a figure which shows 1st Embodiment of the capacity | capacitance adjustment apparatus by this invention. 3 is a diagram illustrating details of a capacity adjustment unit 102. FIG. It is a flowchart which shows an example of the capacity | capacitance adjustment control in 1st Embodiment. It is a figure which shows an example of capacity adjustment capability improvement request | requirement degree k1. It is a figure which shows an example of the capacity | capacitance adjustment capability improvement requirement k2. It is a figure which shows an example of the capacity | capacitance adjustment capability improvement requirement k3. It is a figure which shows the relationship between the capacity adjustment capability improvement required degree k and the duty of FET11. FIG. 5 is a diagram qualitatively showing the states of points P1 and P2 in FIG. 4, in which (a) shows the cell voltage distribution at point P1 on the line L2 of the required level k2 (L2), and (b) is the required level The cell voltage distribution at the point P1 on the line L2 of k2 (L2) is shown. It is a figure which shows 2nd Embodiment of the capacity | capacitance adjustment apparatus by this invention, and shows the detail of the capacity | capacitance adjustment part 102 similar to FIG. It is a figure which shows the relationship between a resistance selection pattern and the capacity | capacitance adjustment capability improvement requirement k. It is a flowchart which shows the other control method in 2nd Embodiment. It is a figure which shows the other example of control in the case of using a some resistance. FIG. 13 is a comparison diagram between the control shown in FIG. 12 and conventional control, in which (a) relates to conventional capacity adjustment, and (b) shows a case where the control flow shown in FIG. 12 is adopted. It is a figure which shows the other example of a resistance circuit.

Explanation of symbols

  1: battery control unit, 2: assembled battery, 3: vehicle system, 11: FET, 12, 22, 32: capacity adjustment circuit, 101: cell voltage detection unit, 102: capacity adjustment unit, 103: CPU, 104: memory , 201: current sensor, 202: voltage sensor, 203: temperature sensor, 301: inverter, 302: auxiliary system, 304 vehicle system CPU, 305: warning light, 403, SW1, SW10: switch, C1 to C3: cell, M: Motor, R10, R1A to R1C: Capacity adjustment resistor

Claims (11)

In a capacity adjustment device that adjusts the capacity of a plurality of cells constituting an assembled battery with a predetermined capacity adjustment current value, and adjusts variation in charge capacity between the cells,
Setting means for setting an adjustment capability improvement degree for capacity adjustment with the predetermined capacity adjustment current value according to the state of the assembled battery;
A capacity adjustment device comprising: capacity adjustment means for changing the predetermined capacity adjustment current value based on the degree of adjustment capability improvement, and performing capacity adjustment with the changed capacity adjustment current value. The capacity adjustment apparatus according to claim 1,
The capacity adjustment device, wherein the setting means sets the degree of improvement in adjustment capability based on at least one of a cell voltage distribution status of the assembled battery, a usage time of the assembled battery, and a capacity deterioration status. The capacity adjustment apparatus according to claim 1 or 2,
The capacity adjusting device includes a capacity adjusting resistor connected in parallel to the cell, and a current control element for duty-controlling a capacity adjusting current flowing through the capacity adjusting resistor. The capacity adjustment apparatus according to claim 3, wherein
The capacity adjustment device is characterized in that the capacity adjustment means increases the ratio of the energization state of the capacity adjustment resistor as the degree of adjustment capability improvement increases. The capacity adjustment apparatus according to claim 1 or 2,
The capacity adjusting device includes a resistance circuit connected in parallel to the cell and having a variable resistance value. The capacity adjustment apparatus according to claim 1 or 2,
The capacity adjustment device includes a plurality of capacitance adjustment resistors and a selection device that selects at least one of the plurality of capacitance adjustment resistors and connects them in parallel to the cell. The capacity adjustment apparatus according to claim 5 or 6,
The capacity adjustment device is characterized in that the resistance value is set lower as the degree of improvement in the adjustment capacity is higher. The capacity adjusting device according to claim 6, wherein
The plurality of capacitance adjustment resistors are configured such that a plurality of capacitance adjustment resistor selection patterns having the same resistance value can be set,
The selection unit selects one of the plurality of capacitance adjustment resistor selection patterns at the start of capacitance adjustment, and selects another capacitance adjustment resistor selection pattern when a predetermined time has elapsed. . In the capacity adjustment device according to any one of claims 6 to 8,
If at least one of the selected capacitance adjusting resistors is unusable or becomes unusable during the capacity adjustment, the selecting means uses other capacitance adjusting resistors other than the unusable capacitance adjusting resistor. A capacitance adjusting device that changes the selection of the capacitance adjusting resistor so as to do so. The capacity adjustment apparatus according to claim 9, wherein
The capacity adjusting means is provided for each cell,
The selecting means of the capacity adjusting means provided for each cell performs the change of the capacity adjusting resistor so that the ratio of the capacity adjusting current between the cells before and after the selection change is substantially the same. Capacitance adjusting device characterized. In the capacity adjusting device according to any one of claims 1 to 10,
A capacity adjustment device for setting a capacity adjustment amount by the capacity adjustment means for each cell based on a charge capacity of each cell.

Images