JP2008016597A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP2008016597A
JP2008016597A JP2006185433A JP2006185433A JP2008016597A JP 2008016597 A JP2008016597 A JP 2008016597A JP 2006185433 A JP2006185433 A JP 2006185433A JP 2006185433 A JP2006185433 A JP 2006185433A JP 2008016597 A JP2008016597 A JP 2008016597A
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JP
Japan
Prior art keywords
semiconductor element
semiconductor device
bed
external terminal
conductor strap
Prior art date
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Pending
Application number
JP2006185433A
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Japanese (ja)
Inventor
Eitaro Miyake
英太郎 三宅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
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Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2006185433A priority Critical patent/JP2008016597A/en
Publication of JP2008016597A publication Critical patent/JP2008016597A/en
Pending legal-status Critical Current

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    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide the manufacturing method of semiconductor device capable of forming uniform joint and improved in the degree of freedom for selecting the thickness of solder, which becomes a factor for increasing the inclination of a semiconductor element while permitting the thickening of the solder, thereby improving the long period reliability of the semiconductor device. <P>SOLUTION: The semiconductor device is provided with the semiconductor element 5, a bed 7 for mounting the semiconductor element, external terminals connected electrically to the electrode of the semiconductor element, conductor straps for connecting electrically the electrode of semiconductor element to the external terminals and a resin sealing body for the resin sealing of these components. The manufacturing method comprises a process for the ultrasonic connection of the conductor strap 6 onto the semiconductor element 5, and a process for mounting the semiconductor element on the bed 7 after connecting the conductor strap 6 to the semiconductor element 5. The uniform joint can be formed and the degree of freedom of selecting the thickness of solder which becomes the factor for increasing the inclination of the semiconductor element is improved whereby the thickness of solder can be increased, thereby permitting the improvement of long period reliability of the semiconductor device. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体素子がベッドに搭載され、前記半導体素子を導電体ストラップを経由して外部リードと電気的に接続させた樹脂封止タイプの半導体装置の製造方法に関するものである。   The present invention relates to a method for manufacturing a resin-encapsulated semiconductor device in which a semiconductor element is mounted on a bed and the semiconductor element is electrically connected to an external lead via a conductor strap.

従来技術における導電体ストラップを具備した半導体装置の製造工程は、半導体素子を搭載するベッドに予めはんだでマウントした半導体素子上に導電体ストラップを超音波接続する。この時、マウントはんだの厚さ不均一に起因する半導体素子の傾きが生じた場合、導電体ストラップの接続時にボンディングツールの片当りが起って、接合の不均一が生じる。また、ボンディングツール片当りによる半導体素子へのダメージの原因となる。
従来では、半導体素子の傾きを抑えるために、はんだを薄くすることで対応しているが、そのため半導体素子面積が大きい製品では、温度サイクルによる熱応力を十分にはんだが吸収できずに長期信頼性が確保出来なくなってしまうという問題があった。 In the manufacturing process of a semiconductor device provided with a conductor strap in the prior art, the conductor strap is ultrasonically connected to a semiconductor element previously mounted on a bed on which the semiconductor element is mounted with solder. At this time, when the inclination of the semiconductor element due to the non-uniform thickness of the mount solder occurs, the bonding tool comes into contact with each other at the time of connecting the conductor strap, resulting in non-uniform bonding. Moreover, it causes damage to the semiconductor element due to the bonding tool piece.
Conventionally, in order to suppress the inclination of the semiconductor element, it is possible to reduce the thickness of the solder, but for products with a large semiconductor element area, the solder cannot absorb the thermal stress due to the temperature cycle and the long-term reliability There was a problem that could not be secured.

従来技術としては、特許文献１に省電力で作動可能であると共に電気的性能が安定しており、且つ耐久性が高い半導体装置が開示されている。リードフレームのドレイン側端子のドレイン側ポスト部の上に、半導体素子をそのソース電極及びゲート電極が上向きとなる姿勢で接合する。素子のゲート電極とフレームのゲート側端子のゲート側ポスト部とをボンディングワイヤで電気的に接続する。略板形状に形成されており、且つソース電極に接続される部分とソース側ポスト部に接続される部分との間の中間部が、素子から離間する形状に形成されている１個のアルミニウム製の接続ストラップをその両端部が、電極及びポスト部に直接接触するように、超音波接合により同時に電気的に接合する。
特開２００２−３１４０１８号公報 As a conventional technique, Patent Document 1 discloses a semiconductor device that can operate with power saving, has stable electrical performance, and has high durability. A semiconductor element is bonded onto the drain-side post portion of the drain-side terminal of the lead frame so that the source electrode and the gate electrode face upward. The gate electrode of the element and the gate side post portion of the gate side terminal of the frame are electrically connected by a bonding wire. One aluminum product that is formed in a substantially plate shape, and in which the intermediate part between the part connected to the source electrode and the part connected to the source side post part is separated from the element These connection straps are electrically bonded simultaneously by ultrasonic bonding so that both ends thereof are in direct contact with the electrodes and the post portions.
Japanese Patent Laid-Open No. 2002-314018

本発明は、均一な接合が形成可能であり、半導体素子傾き増大の要因となるはんだ厚の選択自由度が向上し、はんだをより厚くすることが可能となって半導体装置の長期信頼性を向上させる半導体装置の製造方法を提供する。   The present invention can form a uniform bond, improves the degree of freedom in selecting the solder thickness, which causes an increase in the tilt of the semiconductor element, and enables the solder to be thicker, thereby improving the long-term reliability of the semiconductor device. A method for manufacturing a semiconductor device is provided.

本発明の半導体装置の一態様は、複数の電極を有する半導体素子と、前記半導体素子を搭載するベッドと、前記複数の電極と電気的に接続された外部端子と、前記複数の電極のうちの１個の電極と前記外部端子のうちの少なくとも１個の外部端子とを電気的に接続する導電体ストラップと、前記半導体素子、前記導電体ストラップ及び前記外部端子をパッケージングする樹脂封止体とを具備した半導体装置を製造する方法において、前記導電体ストラップを前記半導体素子上に超音波接続する工程と、前記導電体ストラップを前記半導体素子に接続した後、前記ベッド上に前記半導体素子をマウントする工程とを備えたことを特徴としている。   One embodiment of a semiconductor device of the present invention includes a semiconductor element having a plurality of electrodes, a bed on which the semiconductor element is mounted, an external terminal electrically connected to the plurality of electrodes, and the plurality of electrodes. A conductor strap that electrically connects one electrode and at least one of the external terminals; a resin sealing body that packages the semiconductor element, the conductor strap, and the external terminal; A step of ultrasonically connecting the conductor strap to the semiconductor element, and mounting the semiconductor element on the bed after connecting the conductor strap to the semiconductor element. It is characterized by comprising a process for performing.

本発明は、均一な接合が形成可能であり、半導体素子傾き増大の要因となるはんだ厚の選択自由度が向上するため、はんだをより厚くすることが出来るので半導体装置の長期信頼性を向上させることが可能となる。   According to the present invention, uniform bonding can be formed, and the degree of freedom in selecting a solder thickness that causes an increase in the inclination of a semiconductor element is improved. Therefore, the solder can be made thicker, so that the long-term reliability of a semiconductor device is improved. It becomes possible.

以下、実施例を参照して発明の実施の形態を説明する。   Hereinafter, embodiments of the invention will be described with reference to examples.

図１乃至図５を参照して実施例１を説明する。
図１は、この実施例に係る半導体装置の製造方法を説明する工程図、図２は、この実施例に係る半導体装置の斜視図、図３は、図２のＡ−Ａ線に沿う部分の断面図、図４は、図２のＢ−Ｂ線に沿う部分の断面図、図５は、この実施例に係る半導体装置の製造方法における導電体ストラップを半導体素子に接続する工程から半導体素子をベッドに接合する工程までを説明する工程図である。
図２に示すように、この実施例の半導体装置としてＭＯＳＦＥＴ（パワーＭＯＳＦＥＴ）を用いて説明する。この半導体装置１は、その全体の殆どを、例えば、エポキシ系樹脂などからなる封止樹脂体（モールド樹脂）２によって固めて形成されたハウジングに覆われている。また、この半導体装置１は、例えば、ＳＯＰ−８パッケージといわれているように、８本の外部端子３を有するリードフレームを備えている。各外部端子３は、樹脂封止体２の両側部において４本ずつに分かれて対向するように、その外側に露出されている。 A first embodiment will be described with reference to FIGS.
FIG. 1 is a process diagram for explaining a method of manufacturing a semiconductor device according to this embodiment, FIG. 2 is a perspective view of the semiconductor device according to this embodiment, and FIG. 3 is a sectional view taken along line AA in FIG. 4 is a cross-sectional view of a portion along line BB in FIG. 2, and FIG. 5 is a cross-sectional view of the semiconductor element from the step of connecting the conductor strap to the semiconductor element in the method of manufacturing a semiconductor device according to this embodiment. It is process drawing explaining to the process joined to a bed.
As shown in FIG. 2, description will be made using a MOSFET (power MOSFET) as a semiconductor device of this embodiment. The semiconductor device 1 is almost entirely covered with a housing formed by sealing with a sealing resin body (mold resin) 2 made of, for example, an epoxy resin. In addition, the semiconductor device 1 includes a lead frame having eight external terminals 3 as is called, for example, an SOP-8 package. Each external terminal 3 is exposed to the outside so as to be divided into four on both sides of the resin sealing body 2 and face each other.

図では、８本の外部端子３のうち、５本のみを示し、残りの３本はそれらの図示を省略する。樹脂封止体２の右側の側面には、ソース電極に電気的に接続された３本の外部端子（ソース側外部端子）３１の先端及びゲート電極に電気的に接続された１本の外部端子（ゲート側外部端子）３２の先端が露出している。樹脂封止体２の左側の側面には、ドレイン電極に電気的に接続された４本の外部端子（ドレイン側外部端子）３３の先端が露出している。
この実施例で用いられるリードフレームは、銅やＦｅ−４２Ｎｉなどからなる材料を用い、フレームに支持された外部端子及び半導体素子搭載用ベッドが一体化して形成されている。そして、外部端子のうち、ドレイン側外部端子は、ベッドに一体的につながっている。 In the figure, only five of the eight external terminals 3 are shown, and the remaining three are not shown. On the side surface on the right side of the resin sealing body 2, one external terminal electrically connected to the tip of three external terminals (source side external terminals) 31 electrically connected to the source electrode and the gate electrode The tip of (gate side external terminal) 32 is exposed. On the left side surface of the resin sealing body 2, tips of four external terminals (drain side external terminals) 33 electrically connected to the drain electrode are exposed.
The lead frame used in this embodiment is made of a material made of copper, Fe-42Ni, or the like, and the external terminals supported by the frame and the semiconductor element mounting bed are integrally formed. Of the external terminals, the drain side external terminal is integrally connected to the bed.

図３及び図４には、半導体装置１の内部構造の主要部分が示されている。
図３及び図４に示すように、外部端子３３は、樹脂封止体２の内部において４本１組に一体化されて形成されており、更に、半導体素子５を搭載するベッド７とは一体化されて形成されている。ベッド７には半導体素子５が搭載され、外部端子３３は、ベット７を介して、半導体素子５のドレイン電極（図示しない）に電気的に接続されている（ドレイン側外部端子）。
外部端子３１は、半導体素子５の電極４のうちのソース電極４１に電気的に接続されている（ソース側外部端子）。両者を電気的に接続するのは、アルミニウムや銅などの金属材料からなる略板形状の導電体ストラップ６である。導電体ストラップ６は、一端が半導体素子５のソース電極４１に、例えば、超音波溶接により面接触で接続され、他端が３本の外部端子３１に超音波溶接などにより面接触で接続される。３本の外部端子３１は、共通部分３１１を有し、導電体ストラップ６の他端は、この共通部分３１１に接合される。 3 and 4 show the main part of the internal structure of the semiconductor device 1.
As shown in FIGS. 3 and 4, the external terminal 33 is formed integrally with a set of four inside the resin sealing body 2, and further integrated with the bed 7 on which the semiconductor element 5 is mounted. It is formed. The semiconductor element 5 is mounted on the bed 7, and the external terminal 33 is electrically connected to the drain electrode (not shown) of the semiconductor element 5 via the bed 7 (drain-side external terminal).
The external terminal 31 is electrically connected to the source electrode 41 of the electrodes 4 of the semiconductor element 5 (source side external terminal). The two are electrically connected by a substantially plate-shaped conductor strap 6 made of a metal material such as aluminum or copper. One end of the conductor strap 6 is connected to the source electrode 41 of the semiconductor element 5 by surface contact, for example, by ultrasonic welding, and the other end is connected to the three external terminals 31 by surface contact, for example, by ultrasonic welding. . The three external terminals 31 have a common portion 311, and the other end of the conductor strap 6 is joined to the common portion 311.

外部端子３２は、半導体素子５の電極４のうちのゲート電極４２に電気的に接続されている（ゲート側外部端子）。ゲート電極４２は、半導体素子５のソース電極４１が形成されている面と同一面に形成されている。両者を電気的に接続するのは、アルミニウムや金などのボンディングワイヤ８である。ボンディングワイヤ８は、一端が半導体素子５のゲート電極４２にボンディングされ、他端が外部端子３２にボンディングされる。ボンディングワイヤ８は、樹脂封止体２内部に含まれる。４本の外部端子３１、３２は、樹脂封止体２の内側において、ソース電極４１及びゲート電極４２を含めた半導体素子５に直接接触しないように設けられている。   The external terminal 32 is electrically connected to the gate electrode 42 of the electrodes 4 of the semiconductor element 5 (gate side external terminal). The gate electrode 42 is formed on the same surface as the surface on which the source electrode 41 of the semiconductor element 5 is formed. Both are electrically connected by a bonding wire 8 such as aluminum or gold. The bonding wire 8 has one end bonded to the gate electrode 42 of the semiconductor element 5 and the other end bonded to the external terminal 32. The bonding wire 8 is included in the resin sealing body 2. The four external terminals 31 and 32 are provided inside the resin sealing body 2 so as not to directly contact the semiconductor element 5 including the source electrode 41 and the gate electrode 42.

この実施例の半導体装置１は、その半導体素子（半導体チップ）５のチップサイズが、３．７９ｍｍ×２．６５ｍｍに形成されている。また、導電体ストラップ６は、その幅が２．０ｍｍの大きさに、その厚さが０．１ｍｍの大きさにそれぞれ形成されている。導電体ストラップ６は、例えば、アルミニウム（Ａｌ）によって形成されており、Ａｌストラップ６とも称する。
この実施例は、半導体素子をベッドに導電体ストラップを用いて接合する工程に特徴がある。その特徴は、導電体ストラップを半導体素子上に予め超音波接続しておき、その後に、半導体素子をベッド上にマウントすることにある。 In the semiconductor device 1 of this embodiment, the semiconductor element (semiconductor chip) 5 has a chip size of 3.79 mm × 2.65 mm. The conductor strap 6 is formed to have a width of 2.0 mm and a thickness of 0.1 mm. The conductor strap 6 is made of, for example, aluminum (Al) and is also referred to as an Al strap 6.
This embodiment is characterized in that a semiconductor element is bonded to a bed using a conductor strap. The feature is that the conductor strap is ultrasonically connected to the semiconductor element in advance, and then the semiconductor element is mounted on the bed.

図１及び図５は、この実施例における半導体装置の製造工程の一部を示すものである。この実施例では、半導体素子５を保持するために受け台８を用いる。この受け台８は、超音波接続中の半導体素子５の横滑り及び破損を防ぐために、半導体素子５との接触面の摩擦係数が高く、弾性率の高い、例えば、ラバー等の材料が望ましい。また、半導体素子５の受け台８への沈み込みによる半導体素子５の四隅の破損を防ぐために、例えば、半導体素子５より小さいものを用いる。つまり、受け台８に搭載された半導体素子５は、半導体素子５の各辺より内側において受け台８と接している。また、この弾性を有する受け台を用いて超音波接続を行う方法では、半導体素子は上面と下面間の平行度が高精度で加工されているため、超音波接続用の超音波振動子が内蔵されたボンディングツールの片当りが生じないと言う利点がある。   1 and 5 show a part of the manufacturing process of the semiconductor device in this embodiment. In this embodiment, a cradle 8 is used to hold the semiconductor element 5. The cradle 8 is preferably made of a material having a high coefficient of friction and a high modulus of elasticity, for example, a rubber, in order to prevent a side slip and breakage of the semiconductor element 5 during ultrasonic connection. Further, in order to prevent breakage of the four corners of the semiconductor element 5 due to sinking of the semiconductor element 5 into the cradle 8, for example, one smaller than the semiconductor element 5 is used. That is, the semiconductor element 5 mounted on the cradle 8 is in contact with the cradle 8 inside each side of the semiconductor element 5. Moreover, in the method of performing ultrasonic connection using this elastic cradle, the parallelism between the upper surface and the lower surface of the semiconductor element is processed with high accuracy, so an ultrasonic transducer for ultrasonic connection is built-in. There is an advantage that no contact between the bonded bonding tools occurs.

まず、半導体素子５及び導電体ストラップ６を用意し、半導体素子５をラバーなど弾性のある材料を用いて形成し、半導体素子５より小さい受け台８の上に載せる。受け台８は、その外周が半導体素子５の各辺より内側に配置されるように、半導体素子５を搭載する（図１（ａ）及び図５（１）参照）。次に、受け台８に搭載された半導体素子５のソース電極（図示しない）が露出している面に導電体ストラップ６を当接し、超音波振動子を内蔵するボンディングツール１０先端を導電体ストラップ６に押し当て、導電体ストラップ６と半導体素子５のソース電極とを超音波接続させる（図１（ｂ）、図５（２）参照）。次工程では、導電体ストラップ６を接続した半導体素子５をＰｂ系、Ｓｎ系あるいはＰｂ−Ｓｎ系などのはんだを使用してベッド７上面にマウントする（図１（ｃ）、図５（３）参照）。
図２及び図３に示す通り、ベッド７は、ソース側外部端子３３と一体的に形成されている。したがって、次工程で、ゲート側外部端子３２をゲート電極に電気的に接続し、その後、外部端子の一端部、半導体素子、導電体ストラップ及びボンディングワイヤ等を封止するエポキシ樹脂などの樹脂封止体を形成し、その後、外部端子等を構成するリードフレームの不要部分を樹脂封止体から切り離し整形して半導体装置を完成する。 First, the semiconductor element 5 and the conductor strap 6 are prepared, the semiconductor element 5 is formed using an elastic material such as rubber, and is placed on a cradle 8 smaller than the semiconductor element 5. The cradle 8 is mounted with the semiconductor element 5 so that the outer periphery thereof is disposed inside each side of the semiconductor element 5 (see FIGS. 1A and 5A). Next, the conductor strap 6 is brought into contact with the surface of the semiconductor element 5 mounted on the cradle 8 where the source electrode (not shown) is exposed, and the tip of the bonding tool 10 containing the ultrasonic vibrator is connected to the conductor strap. 6 is ultrasonically connected to the conductor strap 6 and the source electrode of the semiconductor element 5 (see FIGS. 1B and 5B). In the next step, the semiconductor element 5 to which the conductor strap 6 is connected is mounted on the upper surface of the bed 7 using Pb, Sn, or Pb-Sn solder (FIGS. 1 (c) and 5 (3)). reference).
As shown in FIGS. 2 and 3, the bed 7 is formed integrally with the source-side external terminal 33. Therefore, in the next step, the gate-side external terminal 32 is electrically connected to the gate electrode, and thereafter, resin sealing such as epoxy resin that seals one end of the external terminal, the semiconductor element, the conductor strap, the bonding wire, etc. After that, an unnecessary portion of the lead frame constituting the external terminal or the like is cut off from the resin sealing body and shaped to complete the semiconductor device.

この実施例では、予め導電体ストラップを半導体素子に接続してから、半導体素子をベッドに搭載しているので、はんだ厚の不均一に起因する半導体素子の傾きを考慮することなくマウントが可能となり、はんだをより厚くすることが出来る。そのために温度サイクルによるはんだへの応力が緩和でき、半導体装置の長期信頼性を向上させることが可能となる。   In this embodiment, since the conductor strap is connected to the semiconductor element in advance and the semiconductor element is mounted on the bed, mounting is possible without considering the inclination of the semiconductor element due to non-uniform solder thickness. , Solder can be made thicker. Therefore, the stress on the solder due to the temperature cycle can be relaxed, and the long-term reliability of the semiconductor device can be improved.

次に、図６を参照して実施例２を説明する。
図６は、この実施例の半導体装置に用いるリードフレームの斜視図である。
この実施例はリードフレームに特徴がある。このリードフレームは、銅やＦｅ−４２Ｎｉなどからなる材料を用い、フレームに支持された外部端子が一体化して形成されているが半導体素子搭載用ベッドは、リードフレームに一体化されて形成されておらず、リードフレームにはめ込まれている。
この半導体装置は、図示はしないがその全体の殆どを、例えば、エポキシ系樹脂などからなる封止樹脂体（モールド樹脂）によって固めて形成されたハウジングに覆われている。また、この半導体装置は、例えば、７本の外部端子２３を有するリードフレーム２１を備えている。リードフレーム２１は、外周に形成されたフレーム２１１と、フレーム２１１の対向する２辺から内側に突出した釣りピン２１２と、釣りピン２１２が突出している辺とは隣接した２辺から内側に突出した夫々７本の外部端子２３と、２辺から突出した外部端子２３の間に配置されたベッド２７から構成されている。 Next, Embodiment 2 will be described with reference to FIG.
FIG. 6 is a perspective view of a lead frame used in the semiconductor device of this embodiment.
This embodiment is characterized by a lead frame. This lead frame is made of a material made of copper, Fe-42Ni, or the like, and the external terminals supported by the frame are integrally formed. The semiconductor element mounting bed is formed integrally with the lead frame. It is not inserted into the lead frame.
Although not shown, this semiconductor device is almost entirely covered with a housing formed by sealing with a sealing resin body (mold resin) made of, for example, an epoxy resin. The semiconductor device also includes a lead frame 21 having, for example, seven external terminals 23. The lead frame 21 protrudes inward from two sides adjacent to the frame 211 formed on the outer periphery, the fishing pin 212 protruding inward from two opposite sides of the frame 211, and the side from which the fishing pin 212 protrudes. Each is composed of seven external terminals 23 and a bed 27 arranged between the external terminals 23 protruding from the two sides.

２辺のうち一方の辺から突出した外部端子２３のうち６本は半導体素子２５のソース電極と電気的に接続されるソース側外部端子２３１であり、１本は半導体素子２５のゲート電極と電気的に接続されるゲート側外部端子２３３である。ソース側外部端子２３１は、導電体ストラップ２６との接合部分に板状の共通部分２３２を備えている。この実施例では、リード形状のドレイン側外部端子を用いない。したがって、ベッド２７裏面がドレイン側外部端子となる。ベット２７は、対向する２辺から突出する釣りピン２１２によってその弾性力により嵌め込まれて固定される。   Six of the external terminals 23 protruding from one of the two sides are source-side external terminals 231 that are electrically connected to the source electrode of the semiconductor element 25, and one is electrically connected to the gate electrode of the semiconductor element 25. This is a gate-side external terminal 233 that is electrically connected. The source-side external terminal 231 includes a plate-like common portion 232 at the joint portion with the conductor strap 26. In this embodiment, the lead-shaped drain-side external terminal is not used. Therefore, the back surface of the bed 27 becomes the drain side external terminal. The bed 27 is fitted and fixed by the elastic force of the fishing pin 212 protruding from two opposing sides.

実施例１と同様に、この実施例では、半導体素子２５を保持するために受け台を用いる。まず、半導体素子２５及び導電体ストラップ２６を用意し、半導体素子２５を受け台の上に載せる。次に、受け台に搭載された半導体素子２５のソース電極（図示しない）が露出している面に導電体ストラップ２６を当接し、超音波振動子を内蔵するボンディングツール先端を導電体ストラップ２６に押し当て、導電体ストラップ２６と半導体素子２５のソース電極とを超音波接続させる。次工程では、導電体ストラップ２６を接続した半導体素子２５をＰｂ系、Ｓｎ系あるいはＰｂ−Ｓｎ系などのはんだ２９を使用してベッド２７上面マウントする。
次工程で、ゲート側外部端子２３３をゲート電極にボンディングワイヤ（図示しない）を用いて電気的に接続し、その後、外部端子の一端部、半導体素子、導電体ストラップ及びボンディングワイヤ等を封止するエポキシ樹脂などの樹脂封止体を形成し、その後外部端子等を構成するリードフレームの不要部分を樹脂封止体から切り離し整形して半導体装置を完成する。 Similar to the first embodiment, in this embodiment, a cradle is used to hold the semiconductor element 25. First, the semiconductor element 25 and the conductor strap 26 are prepared, and the semiconductor element 25 is placed on a cradle. Next, the conductor strap 26 is brought into contact with the surface where the source electrode (not shown) of the semiconductor element 25 mounted on the cradle is exposed, and the tip of the bonding tool incorporating the ultrasonic vibrator is attached to the conductor strap 26. The conductor strap 26 and the source electrode of the semiconductor element 25 are ultrasonically connected by pressing. In the next step, the semiconductor element 25 to which the conductor strap 26 is connected is mounted on the upper surface of the bed 27 using a solder 29 such as Pb, Sn or Pb-Sn.
In the next step, the gate-side external terminal 233 is electrically connected to the gate electrode using a bonding wire (not shown), and then one end of the external terminal, the semiconductor element, the conductor strap, the bonding wire, and the like are sealed. A resin sealing body such as an epoxy resin is formed, and then unnecessary portions of the lead frame constituting the external terminals and the like are separated from the resin sealing body and shaped to complete the semiconductor device.

この実施例では、予め導電体ストラップを半導体素子に接続してから、半導体素子をベッドに搭載しているので、はんだ厚の不均一に起因する半導体素子の傾きを考慮することなくマウントが可能となり、はんだをより厚くすることが出来る。そのために温度サイクルによるはんだへの応力が緩和でき、半導体装置の長期信頼性を向上させることが可能となる。   In this embodiment, since the conductor strap is connected to the semiconductor element in advance and the semiconductor element is mounted on the bed, mounting is possible without considering the inclination of the semiconductor element due to non-uniform solder thickness. , Solder can be made thicker. Therefore, the stress on the solder due to the temperature cycle can be relaxed, and the long-term reliability of the semiconductor device can be improved.

次に、図７を参照して実施例３を説明する。
図７は、この実施例の半導体装置に用いるリードフレームの他の例を平面図及びこの平面図のＡ領域の拡大断面図である。
この実施例はリードフレームに特徴がある。このリードフレームは、銅やＦｅ−４２Ｎｉなどからなる材料を用い、フレームに支持された外部端子が一体化して形成されているが半導体素子搭載用ベッドは、リードフレームに一体化されて形成されておらず、リードフレームに取り付けられている。 Next, Embodiment 3 will be described with reference to FIG.
FIG. 7 is a plan view of another example of a lead frame used in the semiconductor device of this embodiment and an enlarged cross-sectional view of a region A in this plan view.
This embodiment is characterized by a lead frame. This lead frame is made of a material made of copper, Fe-42Ni, or the like, and the external terminals supported by the frame are integrally formed. The semiconductor element mounting bed is formed integrally with the lead frame. It is not attached to the lead frame.

この半導体装置は、図示はしないがその全体の殆どを、例えば、エポキシ系樹脂などからなる封止樹脂体（モールド樹脂）によって固めて形成されたハウジングに覆われている。また、この半導体装置は、外部端子及び半導体素子を搭載するベッドを有するリードフレーム３３を備えている。リードフレーム３３は、外周に形成されたフレーム３３１と、フレーム３３の対向する２辺から内側に突出した釣りピン３３２と、釣りピン２１２が突出している辺とは隣接した２辺から内側に突出した外部端子（図示しない）と、２辺から突出した外部端子の間に配置されたベッド３７から構成されている。ベッド３７は、フレーム３３１から突出した釣りピン３３２にカシメ接続により固定されている。両者を固定するカシメ部３７１は、ベッド３７の対向する２辺に設けられた突起と釣りピン３３２の先端により構成されている（図７（ｂ）参照）。外部端子のうち半導体素子（図示しない）のソース電極と電気的に接続されるソース側外部端子は、導電体ストラップ（図示しない）によって半導体素子のソース電極と電気的に接続されている。また、図示しないが、ベッド３７裏面がドレイン側外部端子となる。   Although not shown, this semiconductor device is almost entirely covered with a housing formed by sealing with a sealing resin body (mold resin) made of, for example, an epoxy resin. The semiconductor device also includes a lead frame 33 having a bed on which external terminals and semiconductor elements are mounted. The lead frame 33 protrudes inward from two sides adjacent to the frame 331 formed on the outer periphery, the fishing pin 332 protruding inward from two opposite sides of the frame 33, and the side from which the fishing pin 212 protrudes. The bed 37 is arranged between an external terminal (not shown) and an external terminal protruding from two sides. The bed 37 is fixed to the fishing pin 332 protruding from the frame 331 by caulking. The caulking portion 371 for fixing both is constituted by protrusions provided on two opposing sides of the bed 37 and the tip of the fishing pin 332 (see FIG. 7B). A source-side external terminal that is electrically connected to a source electrode of a semiconductor element (not shown) among the external terminals is electrically connected to a source electrode of the semiconductor element by a conductor strap (not shown). Although not shown, the back surface of the bed 37 serves as a drain-side external terminal.

実施例１、２と同様に、この実施例では、半導体素子のソース電極（図示しない）が露出している面に導電体ストラップを当接し、超音波振動子を内蔵するボンディングツール先端を導電体ストラップに押し当て導電体ストラップと半導体素子のソース電極とを超音波接続させる。次いで、導電体ストラップを接続した半導体素子をＰｂ系、Ｓｎ系あるいはＰｂ−Ｓｎ系などのはんだを使用してマウントする。次いで、ゲート側外部端子をゲート電極にボンディングワイヤ（図示しない）を用いて電気的に接続し、その後、外部端子の一端部、半導体素子、導電体ストラップ及びボンディングワイヤ等を封止するエポキシ樹脂などの樹脂封止体を形成し、その後外部端子等を構成するリードフレームの不要部分を樹脂封止体から切り離し整形して半導体装置を完成する。
この実施例では、予め導電体ストラップを半導体素子に接続してから、半導体素子をベッドに搭載しているので、はんだ厚の不均一に起因する半導体素子の傾きを考慮することなくマウントが可能となり、はんだをより厚くすることが出来る。そのために温度サイクルによるはんだへの応力が緩和でき、半導体装置の長期信頼性を向上させることが可能となる。 Similar to the first and second embodiments, in this embodiment, the conductor strap is brought into contact with the surface of the semiconductor element where the source electrode (not shown) is exposed, and the tip of the bonding tool containing the ultrasonic transducer is connected to the conductor. The conductor strap is pressed against the strap and the source electrode of the semiconductor element is ultrasonically connected. Next, the semiconductor element to which the conductor strap is connected is mounted using Pb-based, Sn-based, or Pb-Sn-based solder. Next, the gate-side external terminal is electrically connected to the gate electrode using a bonding wire (not shown), and then an epoxy resin or the like that seals one end of the external terminal, the semiconductor element, the conductor strap, the bonding wire, etc. The resin sealing body is formed, and then unnecessary portions of the lead frame constituting the external terminals and the like are separated from the resin sealing body and shaped to complete the semiconductor device.
In this embodiment, since the conductor strap is connected to the semiconductor element in advance and the semiconductor element is mounted on the bed, mounting is possible without considering the inclination of the semiconductor element due to the non-uniform solder thickness. , Solder can be made thicker. Therefore, the stress on the solder due to the temperature cycle can be relaxed, and the long-term reliability of the semiconductor device can be improved.

本発明の一実施例である実施例１に係る半導体装置の製造方法を説明する工程図。Process drawing explaining the manufacturing method of the semiconductor device which concerns on Example 1 which is one Example of this invention. 実施例１に係る半導体装置の斜視図。1 is a perspective view of a semiconductor device according to Embodiment 1. FIG. 図２のＡ−Ａ線に沿う部分の断面図。Sectional drawing of the part which follows the AA line of FIG. 図２のＢ−Ｂ線に沿う部分の断面図。Sectional drawing of the part which follows the BB line of FIG. 実施例１に係る半導体装置の製造方法における導電体ストラップを半導体素子に接続する工程から半導体素子をベッドに接合する工程までを説明する工程図。Process drawing explaining from the process of connecting the conductor strap to the semiconductor element to the process of joining the semiconductor element to the bed in the manufacturing method of the semiconductor device according to the first embodiment. 本発明の一実施例である実施例２に係る半導体装置に用いるリードフレームの斜視図。The perspective view of the lead frame used for the semiconductor device concerning Example 2 which is one example of the present invention. 本発明の一実施例である実施例３に係る半導体装置に用いるリードフレームの他の例を平面図及びこの平面図のＡ領域の拡大断面図。14 is a plan view of another example of a lead frame used in a semiconductor device according to a third embodiment which is an embodiment of the present invention, and an enlarged cross-sectional view of a region A in the plan view.

符号の説明Explanation of symbols

１・・・半導体装置
２・・・樹脂封止体
３、２３・・・外部端子
４・・・電極
５、２５・・・半導体素子
６、２６・・・導電体ストラップ
７、２７、３７・・・ベッド
８・・・ボンディングワイヤ
１０・・・ボンディングツール
２１、３３・・・リードフレーム
２９・・・はんだ
３１、２３１・・・ソース側外部端子
３２、２３３・・・ゲート側外部端子
３３・・・ドレイン側外部端子
４１・・・ソース電極
４２・・・ゲート電極
２３２、３１１・・・ソース側外部端子の共通部分
２１１、３３１・・・フレーム
２１２、３３２・・・釣りピン
３７１・・・カシメ部 DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 2 ... Resin sealing body 3, 23 ... External terminal 4 ... Electrode 5, 25 ... Semiconductor element 6, 26 ... Conductor strap 7, 27, 37. .. Bed 8 ... Bonding wire 10 ... Bonding tool 21, 33 ... Lead frame 29 ... Solder 31, 23 ... Source side external terminal 32, 233 ... Gate side external terminal 33. .... Drain side external terminal 41 ... Source electrode 42 ... Gate electrode 232, 311 ... Common part of source side external terminal 211, 331 ... Frame 212, 332 ... Fishing pin 371 ... Caulking section

Claims (5)

複数の電極を有する半導体素子と、前記半導体素子を搭載するベッドと、前記複数の電極と電気的に接続された外部端子と、前記複数の電極のうちの１個の電極と前記外部端子のうちの少なくとも１個の外部端子とを電気的に接続する導電体ストラップと、前記半導体素子、前記導電体ストラップ及び前記外部端子をパッケージングする樹脂封止体とを具備した半導体装置を製造する方法において、
前記導電体ストラップを前記半導体素子の前記１個の電極上に超音波接続する工程と、
前記導電体ストラップを前記半導体素子の前記１個の電極上に接続した後、前記ベッド上に前記半導体素子をマウントする工程とを備えたことを特徴とする半導体装置の製造方法。 A semiconductor element having a plurality of electrodes; a bed on which the semiconductor element is mounted; an external terminal electrically connected to the plurality of electrodes; and one of the plurality of electrodes and the external terminal A method of manufacturing a semiconductor device comprising: a conductor strap that electrically connects at least one external terminal; and a resin sealing body that packages the semiconductor element, the conductor strap, and the external terminal. ,
Ultrasonically connecting the conductor strap onto the one electrode of the semiconductor element;
And a step of mounting the semiconductor element on the bed after connecting the conductor strap to the one electrode of the semiconductor element. 前記導電体ストラップを前記半導体素子の前記１個の電極上に超音波接続する工程には前記半導体素子を載置させる受け台を用い、前記受け台は、弾性があり、半導体素子との接触面の摩擦係数が高い材料を用いることを特徴とする請求項１に記載の半導体装置の製造方法。   In the step of ultrasonically connecting the conductor strap to the one electrode of the semiconductor element, a cradle for placing the semiconductor element is used, and the cradle is elastic and has a contact surface with the semiconductor element. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a material having a high friction coefficient is used. 前記半導体素子は、はんだにより前記ベッド上にマウントすることを特徴とする請求項１又は請求項２に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor element is mounted on the bed with solder. 前記ベッドは、上面が前記半導体素子の前記複数の電極のうちの少なくとも他の１個に電気的に接続されており、裏面が前記外部端子の１つを兼ねていることを特徴とする請求項１乃至請求項３のいずれかに記載の半導体装置の製造方法。   The upper surface of the bed is electrically connected to at least one other of the plurality of electrodes of the semiconductor element, and the back surface also serves as one of the external terminals. A method for manufacturing a semiconductor device according to claim 1. 前記半導体素子をマウントする工程において、前記半導体素子は、この半導体素子より面積の小さい受け台上で行うことを特徴とする請求項１乃至請求項４のいずれかに記載の半導体装置の製造方法。   5. The method of manufacturing a semiconductor device according to claim 1, wherein, in the step of mounting the semiconductor element, the semiconductor element is performed on a pedestal having an area smaller than that of the semiconductor element.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012023204A (en) * 2010-07-14 2012-02-02 On Semiconductor Trading Ltd Semiconductor device, and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012023204A (en) * 2010-07-14 2012-02-02 On Semiconductor Trading Ltd Semiconductor device, and method of manufacturing the same

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