JP2008016479A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which can obtain high accuracy of etching processing by enabling continuously to change a concentration of iodine or bromine in a chamber in a dry etching process, easily controlling etching conditions and preventing generation of striation. <P>SOLUTION: This manufacturing method of a semiconductor device includes a dry etching step in which an insulating film 42 covered with a resist mask 44 formed using an ArF photolithographic method is etched in a plasma atmosphere in a chamber 11, and a pattern of the resist mask is transferred to the insulating film. In the dry etching step, an etching gas containing fluorine atoms is introduced into the chamber and at least any one of an iodine gas and bromine gas is introduced, thereby satisfying a condition in which 26% or less of the total of halogen atoms contained in the gas atmosphere in the chamber is at least any one of iodine atoms and bromine atoms and the residue is fluorine atoms. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor device including a step of dry-etching and finely processing an insulating film covered with a resist mask formed using an optical lithography method using an ArF excimer laser as a light source. It relates to a manufacturing method.

  In recent years, along with higher integration and higher speed of LSI, semiconductor devices have been miniaturized and multilayered. In 2004, mass production of a 90 nm node started, and nano-size processing technology of 100 nm or less came to be used for the production of LSI (for example, see Non-Patent Document 1). As one of semiconductor element technologies of such nano-size processing technology, lithography technology can be cited. Among lithography techniques, optical lithography using an ArF excimer laser as a light source (hereinafter referred to as “ArF photolithography”) has been recognized in 2004 as the only mass production technique for the 90 nm node. An ArF excimer laser light source used in the ArF photolithography method is a laser light source having a short wavelength. Therefore, a fine resist mask can be formed by patterning. When the interlayer insulating film covered with such a resist mask is dry-etched to finely process wiring holes, trenches, etc., high processing accuracy is required to obtain a uniform etching shape in the depth direction. ing. In this case, in order to increase anisotropy, it is known to perform etching by introducing a predetermined etching gas in a plasma atmosphere (see, for example, Patent Document 1).

  By the way, as a resist material used in the ArF photolithography method, it has been proposed to use a resist material composed of a compound having no benzene ring so as to have transparency in the vacuum ultraviolet region (for example, non-patent). Reference 2). In the case of this type of resist material, if fine patterning is performed using a laser having a short wavelength, the resist mask becomes weak accordingly, and the plasma resistance is lower than that used in other photolithography methods. .

  For this reason, when etching is performed in a plasma atmosphere, damage is caused by exposure to plasma, and edge roughness occurs in the edge portion of the patterned region of the resist mask (the shape of the resist mask is deformed). If etching is continued in such a state, there is a problem that the shape is transferred to holes or trenches to be formed in the interlayer insulating film, causing striations. In this case, the requirement for high etching processing accuracy cannot be satisfied.

In order to solve such a problem, an etching gas is a halogen-based gas (halogen is F, I, Br), and at least one of I and Br is an atomic composition ratio of 26% or less of the total amount of halogen. Using the fluorocarbon compound gas with the remainder being F, this gas is introduced in a plasma atmosphere, and the interlayer insulating film covered with the resist mask formed using the ArF photolithography method is dry-etched. It has been proposed (see, for example, Patent Document 2).
JP 11-31678 A JP 2006-108484 A Masaru Etsuko, Masataka Endo, Recent Topics on Lithography, Applied Physics, Vol. 73, No. 2 (2004) pp. 199-205 Koji Nozaki and Ei Yano, FUJITSU Sei. Tech. J., 38,1 p3-12 (June 2002)

  As disclosed in Patent Document 2, an etching gas is a halogen-based gas (halogen is F, I, Br), and at least one of I and Br is an atomic composition ratio of 26% or less of the total amount of halogen. In the case of dry etching using a fluorocarbon compound gas with the remainder being F, striation can be suppressed and high etching processing accuracy can be obtained. Since it is introduced into the chamber as atoms constituting a compound or a bromofluorocarbon compound, it is difficult to change iodine or bromine at a continuous concentration in the chamber, and there is a problem in controllability of etching conditions.

  In view of the above problems, the object of the present invention is to continuously change the concentration of iodine or bromine in the chamber in the dry etching process, to easily control the etching conditions, and to suppress the occurrence of striations. An object of the present invention is to provide a method of manufacturing a semiconductor device that can obtain high etching processing accuracy.

  In order to achieve the above object, a semiconductor device manufacturing method according to the present invention is configured as follows.

  According to a first method for manufacturing a semiconductor device (corresponding to claim 1), an insulating film covered with a resist mask formed by using ArF photolithography is etched in a plasma atmosphere in a chamber to form a resist mask pattern. Including a dry etching process for transferring to an insulating film, and further introducing an etching gas containing fluorine atoms into the chamber while introducing at least one of iodine gas and bromine gas. However, it is characterized in that the condition that 26% or less of the total amount of halogen atoms contained in the gas atmosphere in the chamber is at least one of iodine atoms and bromine atoms and the rest is fluorine atoms is satisfied.

  In the method for manufacturing a semiconductor device including the dry etching step, the halogen atoms contained in the gas atmosphere in the chamber, that is, fluorine atoms, iodine atoms, and bromine atoms are made to satisfy the above conditions, Of the fluorine atoms, one that binds to iodine atoms or bromine atoms is generated, thereby reducing fluorine atoms that react with the resist mask. This makes it difficult to remove the edge of the resist mask and eliminates rough edges. Therefore, generation of striation is suppressed and high etching processing accuracy is obtained. In addition, iodine gas or the like is introduced separately from the etching gas containing fluorine atoms, iodine gas or the like is introduced separately, so that the concentration of iodine or bromine in the chamber can be controlled with good controllability. Allows to change continuously. This makes it possible to easily control the etching conditions.

  The second method for manufacturing a semiconductor device (corresponding to claim 2) is preferably the method described above, wherein the iodine gas transports iodine gas generated by sublimation of solid iodine during the dry etching step with a carrier gas. Is characterized by being introduced into the chamber.

  A third method for manufacturing a semiconductor device (corresponding to claim 3) is characterized in that, in the above method, preferably, a raw material that generates iodine gas is disposed in the chamber.

  In a fourth method of manufacturing a semiconductor device (corresponding to claim 4), in the above method, the bromine gas preferably transports bromine gas generated by bubbling liquid bromine by a carrier gas during the dry etching process. This is characterized by being introduced into the chamber.

  A fifth method for manufacturing a semiconductor device (corresponding to claim 5) is characterized in that, in the above method, preferably, a raw material generating iodine gas and / or a raw material generating bromine gas is impregnated into the components in the chamber. It is done.

  A sixth method for manufacturing a semiconductor device (corresponding to claim 6) is characterized in that, in the above method, the pattern width and / or pattern interval of the resist mask is preferably in the range of 32 to 130 nm.

  In a seventh method for manufacturing a semiconductor device (corresponding to claim 7), in the above method, preferably, the insulating film is a silicon nitride film having a relative dielectric constant of 4.0 to 4.7, It is characterized by being used as a hard mask in another subsequent dry etching process for etching the etching material.

  According to an eighth method for manufacturing a semiconductor device (corresponding to claim 8), in the above method, the insulating film is preferably a silicon oxide film containing C or N having a relative dielectric constant of 1.5 to 4.0. In addition, it is characterized by being used as a hard mask in another dry etching process at a later stage for etching a material to be etched in a lower layer.

  A ninth method for manufacturing a semiconductor device (corresponding to claim 9) is preferably the conductive film or polysilicon film in the above method, wherein the material to be etched contains W, Ti, Ta, Co, Ni, Pt, Ru. Or it is characterized by being the laminated film of the said electrically conductive film and a polysilicon film.

  A tenth method for manufacturing a semiconductor device (corresponding to claim 10) is characterized in that, in the above method, preferably, the material to be etched is Al, Cu or a laminated film containing them.

  In an eleventh method for manufacturing a semiconductor device (corresponding to claim 11), in the above method, preferably, the insulating film is a silicon dioxide film, and other dry etching subsequent to etching the underlying polysilicon is performed. Used as a hard mask in the process, and polysilicon is further characterized as being used as a mask in the process of etching the underlying silicon dioxide or silicon nitride.

  In a twelfth semiconductor device manufacturing method (corresponding to claim 12), in the above method, the resist mask preferably has a three-layer structure of ArF resist / SiO / bottom film (for example, coated carbon (C) film). In the dry etching process, the above condition is satisfied when the SiO / bottom film material of the three-layer structure is dry etched.

  According to the present invention, a semiconductor includes a dry etching process in which an insulating film covered with a resist mask formed by using ArF photolithography is etched in a plasma atmosphere in a chamber, and a resist mask pattern is transferred to the insulating film. In the apparatus manufacturing method, the dry etching process satisfies the condition that 26% or less of the total amount of halogen atoms contained in the gas atmosphere in the chamber is at least one of iodine atoms and bromine atoms, and the rest is fluorine atoms. However, since an etching gas containing fluorine atoms is introduced into the chamber, and at least one of iodine gas and bromine gas is separately introduced into the chamber, iodine or bromine in the chamber is also introduced. Can be continuously changed under high controllability, It is possible to control the conditions easily, it is possible to obtain high etching precision by suppressing the occurrence of striations.

  DESCRIPTION OF EMBODIMENTS Preferred embodiments (examples) of the present invention will be described below with reference to the accompanying drawings.

  FIG. 1 is a schematic configuration diagram of a substrate processing apparatus in which a semiconductor device manufacturing method according to a first embodiment of the present invention is performed. The substrate processing apparatus 10 uses discharge plasma (NLD plasma) generated in a region including zero magnetic field as an example, and an exhaust port 12 is provided so that the inside is evacuated by a vacuum evacuation apparatus such as a dry pump. A chamber 11.

  The chamber 11 is formed by a cylindrical side wall 13 made of a dielectric material such as quartz, and includes an upper plasma generation chamber 11a and a lower substrate processing chamber 11b. On the outside of the cylindrical side wall 13, for example, three magnetic field coils 14, 15, and 16 are provided at predetermined intervals to constitute a magnetic field generation unit. In this case, for example, a current in the same direction is supplied to the upper and lower magnetic field coils 14 and 16, and a current in the opposite direction is supplied to the intermediate coil 15. Thereby, the position of the magnetic field zero continuous inside the cylindrical side wall 13 near the level of the intermediate coil 15 is formed, and an annular magnetic neutral line is formed.

  The size of the annular magnetic neutral line can be set as appropriate by changing the ratio of the current flowing through the upper and lower coils 14 and 16 and the current flowing through the intermediate coil 15. The position of can be appropriately set according to the ratio of currents flowing through the upper and lower magnetic field coils 14 and 16. Further, when the current flowing through the intermediate coil 15 is increased, the diameter of the annular magnetic neutral wire is reduced, and at the same time, the gradient of the magnetic field at the position of the magnetic field zero becomes gentle. An antenna 18 for generating a high-frequency electric field is provided between the intermediate coil 15 and the cylindrical side wall 13 and connected to a first high-frequency power source 19 to constitute a magnetic field generating unit. NLD plasma is generated along the annular magnetic neutral line formed by the three magnetic field coils 14, 15, 16.

  In the substrate processing chamber 11b facing the surface formed by the annular magnetic neutral line, a substrate electrode 20 having a circular cross section, which is a substrate mounting portion on which the substrate S to be processed is mounted, is provided via an insulator 20a. It has been. The substrate electrode 20 is connected to the second high-frequency power source 22 via the capacitor 21 and becomes a floating electrode in terms of potential and has a negative bias potential.

  Further, the top plate 23 that partitions the plasma generation chamber 11a is hermetically fixed to the upper portion of the cylindrical side wall 13, and is in a floating state in terms of potential, thereby forming a counter electrode. A first gas introduction part 24 for introducing an etching gas containing fluorine atoms into the chamber 11 is provided on the inner surface of the top plate, and the first gas introduction part 24 is connected to a gas flow rate control part by a pipe 25. Connected to a gas source. From the first gas introduction unit 24, for example, a fluorocarbon compound gas and an argon gas are continuously introduced into the chamber 11 during the dry etching process, for example.

  A second gas introduction unit 26 for introducing one or both of iodine gas and bromine gas is provided at the bottom of the chamber 11, that is, the bottom of the substrate processing chamber 11b. In the second gas introduction part 26, a container 28 is attached to the pipe 27 via valves 29 and 30. A mass flow controller 32 is attached to the pipe 31 located on the inlet side of the container 28. Solid iodine 33 is accommodated in the container 28. The container 28 is kept at an appropriate temperature by a not-shown incubator. In the container 28, solid iodine 33 is sublimated into a gas state, and the generated iodine gas is flow-controlled by the mass flow controller 32. Then, it is transported through a pipe 27 by a carrier gas such as nitrogen and introduced into the chamber 11 at an appropriate timing and time interval. Thus, the iodine gas is individually introduced through an introduction path separate from the etching gas.

  Further, in the second gas introduction part 26, a bubbler container 34 is attached to the pipe 27 via valves 35 and 36. A mass flow controller 38 is attached to a pipe 37 located on the inlet side of the bubbler container 34. In this bubbler container 34, liquid bromine 39 is stored. The bubbler container 34 is maintained at an appropriate temperature by a heat insulator (not shown). According to the bubbler container 34, liquid bromine 39 is bubbled by a carrier gas such as nitrogen whose flow rate is controlled by the mass flow controller 38, and the bromine gas thus generated is transported into the pipe 27, and has an appropriate timing and time in the chamber 11. Introduced at intervals. Thus, bromine gas is individually introduced through an introduction path separate from the etching gas.

  Next, a dry etching process in the method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described.

  FIG. 2 is a flowchart showing a processing procedure by a dry etching process in the method for manufacturing the semiconductor device according to the first embodiment. FIG. 3 is a partial cross-sectional view of the substrate at each step in the dry etching process.

In step S11 shown in FIG. 2, the substrate 40 shown in FIG. 3A is prepared. First, a silicon wafer 41 that has been processed before depositing an oxide film for a device to be manufactured is prepared, a known plasma CVD film is grown to about 100 nm, and an SiO ₂ film 42 that is an insulating film is formed. Form. A resist mask 44 having a groove pattern 43 of 100 nm is formed using ArF photolithography (FIG. 3A). In FIG. 3, the structure produced by the processing steps performed on the silicon wafer 41 is omitted.

  In step S <b> 12, the substrate 40 prepared as described above is placed on the substrate platform 20 in the substrate processing apparatus 10.

  In step S13, after the inside of the chamber 11 is evacuated, an etching gas containing a fluorine atom whose flow rate is controlled is introduced from the first gas introduction unit 24, and the above-described separate introduction path is also used. At least one of iodine gas and bromine gas is introduced through the second gas introduction unit 26. In this case, 26% or less of the total amount of halogen atoms (F, I, Br) contained in the gas atmosphere in the chamber 11 is at least one of iodine atoms (I) and bromine atoms (Br), and the rest is fluorine. The condition of being an atom (F) is satisfied.

In this example, it is assumed that only iodine gas (I) is introduced through the second gas introduction path 26, for example. Therefore, iodine gas controlled to a flow rate such that the amount of iodine atoms in the chamber 11 is 26% or less of the total amount of halogen atoms in the chamber 11 is introduced into the chamber 11. For example, the flow rate of Ar gas is 230 sccm, the flow rate of C ₃ F ₈ gas is 50 sccm, and the flow rate of O ₂ gas is 20 sccm from the first gas introduction unit 24, and I ₂ is introduced from the second gas introduction unit 26. Gas is introduced at a flow rate of 5.7 sccm. And it exhausts from the exhaust port 12 so that the inside of the chamber 11 may become a predetermined fixed pressure.

In step S14, dry etching is performed as follows. For example, the substrate processing apparatus 10 is configured such that the pressure is 2.67 Pa, the antenna high frequency power is 1 kW, the substrate high frequency power is 0.3 kW, and the substrate temperature is 10 ° C. while introducing the above gases into the chamber 11 at the above flow rates. Is set and etching is performed. At this time, the C ₃ F ₈ gas is decomposed in the chamber 11 to generate F radicals and the like. As shown in FIG. 3 (b), F radicals generated in the chamber 11, enters the SiO ₂ surface 42a which is not covered with the resist mask 44, occur ion assisted reaction by bombardment of Ar ions, SiO ₂ Si is removed from the surface as SiF ₄ . Thereby, the etching of SiO ₂ proceeds. At that time, H on the side wall of the resist mask 44 is removed by a radical reaction with F, and the bare C and F are removed by an ion assist reaction. However, since there are atoms of iodine (I) in the chamber 11, I and F combine to form IF ₃ , IF ₅ , IF _7, etc., and F that undergoes radical reaction with the resist mask 44 decreases. Thus, the edge removal of the resist mask is less likely to occur, and the edge roughness can be eliminated.

As another viewpoint, the iodine atoms introduced into the chamber 11 may be adsorbed on the surface of the resist mask, thereby protecting the erosion caused by F on the resist side wall. For example, FIG. 2 in Patent Document 2 shows a striation, which appears to have eroded the side walls of the resist. This means that it is not a phenomenon caused by ion assist caused by ions irradiated from above, but a reaction caused by radicals. Literature (Chemical Handbook, revised third edition, edited by the Chemical Society of Japan, Maruzen Co., Ltd., II-322) According to the binding energy of the H-F is a 566kJmol ^-1, compared to the binding energy 410kJmol ^-1 of H-C It is getting bigger. Therefore, it is considered that H on the surface of the resist side wall is removed by F. Then, C in the resist may be removed by ion assist. On the other hand, the binding energy 295 kJmol ⁻¹ of HI is smaller than the binding energy of HC. Therefore, it is considered that I is not adsorbed on the resist surface and does not remove H from C. In addition, as described in the literature (Physical and Chemical Dictionary, 5th edition, Iwanami Shoten, pages 1532-1533), I and Br are considerably larger in mass than C and F. Therefore, it is considered that even if F is accelerated in the plasma and collides with the resist side wall, it is protected by I or Br. Therefore, it seems that there is a possibility that striation can be prevented. In addition to the effect that F forms IF ₃ , IF ₅ , and IF ₇ and the total amount of F radicals decreases, it is considered that the above mechanism may exist.

In FIG. 3C, the SiO ₂ etching is completed, and the substrate 40 is taken out in step S15. In the dry etching process described above, the sidewall of the resist mask 44 is not removed and edge roughness can be eliminated, so that the insulating film can be etched without causing striations.

In this embodiment, the description has been given of etching the substrate 40 by introducing only iodine gas into the chamber 11 from the second gas introduction unit 26. However, as described above, only the bromine gas from the bubbler vessel 34, not the iodine gas, causes the mass flow controller 38 to reduce the amount of bromine atoms in the chamber 11 to 26% or less of the total amount of halogen atoms in the chamber 11. The flow rate may be controlled to be introduced into the chamber 11. Further, both the iodine gas and the bromine gas are controlled by the mass flow controllers 32 and 38 so that the total amount of iodine atoms and bromine atoms in the chamber 11 is 26% or less of the total amount of halogen atoms in the chamber 11. May be introduced into the chamber 11. Furthermore, in this embodiment, the example in which the pattern width of the resist mask is set to 100 nm is shown, but the pattern width and / or the pattern interval can be a length included in the range of 32 to 130 nm. Furthermore, in this embodiment, the description has been made using SiO ₂ as the insulating film, but a silicon nitride film having a dielectric constant of 4.0 to 4.7 may be used as the insulating film.

Next, a second embodiment of the semiconductor device manufacturing method according to the present invention will be described. In the method of manufacturing a semiconductor device according to the second embodiment, an insulating film (silicon dioxide) in which a pattern is formed by etching the insulating film covered with a resist mask by the method in the dry etching process described in the first embodiment. Film: SiO ₂ film), and then a method of etching an etching target material made of Pt as a lower layer using the insulating film as a hard mask. Since the substrate processing apparatus used in this method is the same apparatus as the substrate processing apparatus 10 described in the first embodiment, a description of the apparatus structure is omitted.

  FIG. 4 is a flowchart showing a processing procedure of a dry etching step and a subsequent step in the method for manufacturing a semiconductor device according to the second embodiment. FIG. 5 is a partial cross-sectional view of the substrate in each step in the dry etching process and subsequent processes.

In step S21 shown in FIG. 4, the substrate 50 is prepared. First, a silicon wafer 51 that has been processed before depositing Pt for a device to be manufactured is prepared, and Pt is deposited to a thickness of 20 nm by sputtering or the like to form a Pt film 52. An oxide film is grown to a thickness of about 100 nm using a known CVD apparatus to form an insulating SiO ₂ film 53. A resist mask 55 having a groove pattern 54 of 100 nm is formed using ArF photolithography (FIG. 5A). In FIG. 5, the structure produced in the processing step applied to the silicon wafer 51 is omitted.

  In step S <b> 22, the substrate 50 prepared as described above is placed on the substrate platform 20 in the substrate processing apparatus 10.

In step S23, the insulating film 53 is etched based on the same conditions as described in the first embodiment. In FIG. 5B, the dry etching of the SiO ₂ film 53 is completed. At this time, the sidewall of the resist mask 55 is not removed and the edge roughness can be eliminated. Therefore, the insulating film 53 is formed without causing striations. It can be etched.

  In step S24, the resist mask 55 is removed.

  Next, in step S25, the Pt film 52 is dry etched using the insulating film 53 as a hard mask. The substrate processing apparatus 10 is also used for the dry etching process of the Pt film 52 under the insulating film 53. At that time, a mixed gas such as chlorine gas and argon gas is used as an etching gas. At this time, since the insulating film 53 without striation is used as a hard mask, the Pt film 52 can also be etched without causing striation.

  In the second embodiment, Pt is used as the material to be etched. However, W, Ti, Co, Ta, Ni, Ru, and a laminated film containing these conductive materials, Al, Cu, and Al are used as the material to be etched. And a laminated film containing Cu may be used.

Next, a third embodiment of the method for manufacturing a semiconductor device according to the present invention will be described. In the method of manufacturing a semiconductor device according to the third embodiment, an insulating film (silicon dioxide) in which a pattern is formed by etching the insulating film covered with a resist mask by the method in the dry etching process described in the first embodiment. Film: SiO ₂ film), and then, an etching target material made of polysilicon below is etched using the insulating film as a hard mask, and further a base insulating film is etched using the etching target material as a mask. Since the substrate processing apparatus used in this method is the same apparatus as the substrate processing apparatus 10 described in the first embodiment, a description of the apparatus structure is omitted.

  FIG. 6 is a flowchart showing a processing procedure by a dry etching step and a subsequent step of the method for manufacturing a semiconductor device according to the third embodiment. FIG. 7 is a partial cross-sectional view of the substrate in each step in the dry etching process and subsequent processes.

In step S31 shown in FIG. 6, the substrate 60 is prepared. First, a silicon wafer 61 that has been processed before depositing a base insulating film for a device to be manufactured is prepared, and an oxide film is grown by about 100 nm at about 900 ° C. using a known oxidation furnace, A SiO ₂ film 62 is formed. Next, polysilicon 63 is deposited. An LP-CVD film is grown to about 100 nm at about 700 ° C. using a known LP-CVD to form a SiO ₂ film 64 as an insulating film. A resist mask 65 having a 100 nm groove pattern is formed using ArF photolithography (FIG. 7A). In FIG. 7, the structure manufactured in the processing step applied to the silicon wafer 61 is omitted.

  In step S <b> 32, the substrate prepared as described above is placed on the substrate platform 20 in the substrate processing apparatus 10.

In step S33, the insulating film 64 is etched based on the same conditions as described in the first embodiment. In FIG. 7B, the dry etching of the SiO ₂ film 64 is completed. At this time, the sidewalls of the resist mask 65 are not removed and the edge roughness can be eliminated. Therefore, the insulating film 64 is formed without causing striations. It can be etched.

  In step S34, the resist is removed (FIG. 7C).

  Next, in step S35, the polysilicon 63 is etched by a dry etching process using the insulating film 64 as a hard mask (FIG. 7D). At this time, since the insulating film 64 without striation is used as a hard mask, the polysilicon 63 can also be etched without causing striation. FIG. 7E shows a state where the insulating film 64 is removed after etching.

  Next, in step S36, the base insulating film 62 is etched using the polysilicon 63 as a mask (FIG. 7F). At this time, since the polysilicon 63 having no striation is used as a mask, the base insulating film 62 can also be etched without striation.

  In the third embodiment, silicon dioxide is used for the base insulating film 62, but SiN may be used.

  Note that the resist masks 44, 55, and 65 used in each of the above embodiments are single-layer resists. However, the resist mask has a three-layer structure of ArF resist / SiO / bottom film, and the dry etching of the SiO / bottom film material can be performed by the dry etching process described in the first embodiment. Here, SiO is a silicon oxide film formed by SOG (Spin on Glass) or plasma CVD, and a coated carbon film or a plasma CVD carbon film can be used as the bottom film. In this embodiment, iodine gas and / or bromine gas are always introduced into the chamber during dry etching, but iodine gas and / or bromine gas are introduced only before the start of dry etching, Iodine atoms or bromine atoms are adsorbed on the surface of the resist mask, and can be used as a protection for the hole of the resist mask or the side wall of the slit during dry etching. Furthermore, iodine or bromine raw material is applied in advance to the surface of a part in the chamber 11 around the sample table, so that elements in the chamber contain iodine raw material and bromine raw material. Good.

  In the substrate processing apparatus 10 used in the first to third embodiments described above, as shown in FIG. 1, one or both of iodine gas and bromine gas are disposed in the bottom region in the chamber 11. The second gas introduction part 26 for introducing the gas is provided. However, as another device configuration, as shown in FIG. 8, either one or both of iodine gas and bromine gas is supplied to the first gas introduction unit 24 via a pipe 100 connected to the pipe 25. You may make it introduce from. That is, iodine gas and / or bromine gas can be introduced into the chamber 11 through the first gas introduction part 24 together with the etching gas. In FIG. 8, elements that are substantially the same as those described in FIG. 1 are denoted by the same reference numerals.

  The configurations, shapes, sizes, and arrangement relationships described in the above embodiments are merely shown to the extent that the present invention can be understood and implemented, and the numerical values and the compositions (materials) of the respective configurations are as follows. It is only an example. Therefore, the present invention is not limited to the described embodiments, and can be variously modified without departing from the scope of the technical idea shown in the claims.

  The present invention is used for carrying out a dry etching process in a method for manufacturing a semiconductor device using a resist mask manufactured by an ArF photolithography method.

It is a schematic block diagram of the substrate processing apparatus with which the manufacturing method of the semiconductor device which concerns on this invention is implemented. It is a flowchart which shows the procedure of the dry etching process in the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. It is a fragmentary sectional view of a substrate showing a dry etching process in a manufacturing method of a semiconductor device concerning a 1st embodiment. It is a flowchart which shows the procedure of the dry etching process in the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention, and a subsequent process. It is a fragmentary sectional view of a substrate showing a dry etching process etc. in a manufacturing method of a semiconductor device concerning a 2nd embodiment. It is a flowchart which shows the procedure of the dry etching process in the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention, and a subsequent process. It is a fragmentary sectional view of a substrate showing a dry etching process etc. in a manufacturing method of a semiconductor device concerning a 3rd embodiment of the present invention. It is a schematic block diagram of another substrate processing apparatus with which the manufacturing method of the semiconductor device which concerns on this invention is enforced.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Substrate processing apparatus 11 Chamber 11a Plasma generation chamber 11b Substrate processing chamber 13 Cylindrical side wall 20 Substrate electrode 24 1st gas introduction part 25 Piping 26 2nd gas introduction part 27 Piping 28 Container 33 Solid iodine 34 Bubbler container 39 Liquid bromine 44, 55, 65 Resist mask 42, 53, 64 Insulating film

Claims (12)

Including a dry etching step of etching an insulating film covered with a resist mask formed using ArF photolithography in a plasma atmosphere in a chamber, and transferring a pattern of the resist mask to the insulating film;
In the dry etching process,
Introducing an etching gas containing fluorine atoms into the chamber, together with introducing at least one of iodine gas and bromine gas,
The condition that 26% or less of the total amount of halogen atoms contained in the gas atmosphere in the chamber is at least one of the iodine atom and the bromine atom, and the remainder is the fluorine atom is satisfied.
A method for manufacturing a semiconductor device.   2. The semiconductor device according to claim 1, wherein the iodine gas is introduced into the chamber by transporting the iodine gas generated by sublimation of solid iodine by a carrier gas during the dry etching process. Production method.   2. The method of manufacturing a semiconductor device according to claim 1, wherein a raw material for generating the iodine gas is disposed in the chamber.   The bromine gas is introduced into the chamber by transporting the bromine gas generated by bubbling liquid bromine with a carrier gas during the dry etching step. A method for manufacturing a semiconductor device according to claim 1.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the raw material that generates the iodine gas and / or the raw material that generates the bromine gas is impregnated into the components in the chamber.   6. The method of manufacturing a semiconductor device according to claim 1, wherein the pattern width and / or pattern interval of the resist mask is included in a range of 32 to 130 nm.   The insulating film is a silicon nitride film having a relative dielectric constant of 4.0 to 4.7, and is used as a hard mask in another subsequent dry etching process for etching a lower etching target material. The manufacturing method of the semiconductor device of any one of Claims 1-6 to do.   The insulating film is a silicon oxide film containing C or N having a relative dielectric constant of 1.5 to 4.0, and is used as a hard mask in another dry etching process in the subsequent stage for etching the underlying etching target material. The method for manufacturing a semiconductor device according to claim 1, wherein the method is manufactured.   9. The material to be etched is made of a conductive film containing W, Ti, Ta, Co, Ni, Pt, or Ru, a polysilicon film, or a laminated film of the conductive film and a polysilicon film. The manufacturing method of the semiconductor device of description.   9. The method of manufacturing a semiconductor device according to claim 7, wherein the material to be etched is Al, Cu or a laminated film containing them. The insulating film is a silicon dioxide film, and is used as a hard mask in another dry etching step subsequent to etching the underlying polysilicon,
Further, the polysilicon is used as a mask in a step of etching the underlying silicon dioxide or silicon nitride.
The method for manufacturing a semiconductor device according to claim 1, wherein: The resist mask has a three-layer structure of ArF resist / SiO / bottom film, and the condition is satisfied during dry etching of the SiO / bottom film material in the three-layer structure during the dry etching step. A method for manufacturing a semiconductor device according to claim 1.

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