JP2008010706A - Circuit apparatus, and its manufacturing method - Google Patents

Circuit apparatus, and its manufacturing method Download PDF

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JP2008010706A
JP2008010706A JP2006180860A JP2006180860A JP2008010706A JP 2008010706 A JP2008010706 A JP 2008010706A JP 2006180860 A JP2006180860 A JP 2006180860A JP 2006180860 A JP2006180860 A JP 2006180860A JP 2008010706 A JP2008010706 A JP 2008010706A
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electrode
insulating layer
circuit
circuit element
conductive layer
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JP2008010706A5 (en
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Masayuki Nagamatsu
正幸 長松
Yasunori Inoue
恭典 井上
Ryosuke Usui
良輔 臼井
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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    • H01L2924/351—Thermal stress

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit apparatus excellent in a reliability of the connection between a wiring substrate and a circuit elemenet mounted on it, and to provide its manufacturing technology. <P>SOLUTION: The circuit apparatus comprises the circuit element 5 having an electrode 4a on its surface, the wiring substrate 12 having an electrode 7c on its surface, an insulating layer 6 provided between the wiring substrate 12 and the circuit element 5, and a conductor part 8 penetraing through the insulating layer 6 and connecting the electrode 4a and the electrode 7c. The wiring substrate 12 has a laminated structure comprising an insulating layer 9, an electrically conductive layer 7 including the electrode 7c formed on the upper surface side of the insulating layer 9, and an electrically conductive layer 10 formed on the lower surface side of the insulating layer 9. Here, the conductor part 8 is integrally provided with the electrode 7c of the electrically conductive layer 7. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、回路装置およびその製造方法に関し、特に配線基板の上に回路素子を搭載した回路装置およびその製造方法に関する。   The present invention relates to a circuit device and a manufacturing method thereof, and more particularly to a circuit device in which a circuit element is mounted on a wiring board and a manufacturing method thereof.

携帯電話、ＰＤＡ、ＤＶＣ、ＤＳＣといったポータブルエレクトロニクス機器の高機能化が加速するなか、こうした製品が市場で受け入れられるためには小型・軽量化が必須となっており、その実現のために高集積のシステムＬＳＩが求められている。一方、これらのエレクトロニクス機器に対しては、より使い易く便利なものが求められており、機器に使用されるＬＳＩに対し、高機能化、高性能化が要求されている。このため、ＬＳＩチップの高集積化にともないそのＩ／Ｏ数が増大する一方でパッケージ自体の小型化要求も強く、これらを両立させるために、半導体部品の高密度な基板実装に適合した半導体パッケージの開発が強く求められている。こうした要求に対応するため、ＣＳＰ（Chip Size Package）と呼ばれるパッケージ技術が種々開発されている。   As portable electronics devices such as mobile phones, PDAs, DVCs, and DSCs are accelerating their functions, miniaturization and weight reduction are indispensable for these products to be accepted in the market. There is a need for a system LSI. On the other hand, these electronic devices are required to be easier to use and convenient, and higher functionality and higher performance are required for LSIs used in the devices. For this reason, as the number of I / Os increases with higher integration of LSI chips, there is a strong demand for miniaturization of the package itself. In order to achieve both of these, a semiconductor package suitable for high-density board mounting of semiconductor components Development is strongly demanded. In order to meet such demands, various package technologies called CSP (Chip Size Package) have been developed.

このＣＳＰでは一主面に外部接続電極（電極パッド）が形成されたウエハをダイシングすることによりパッケージが形成される。このため、ＣＳＰはＬＳＩと同等のサイズにて配線基板（実装基板）に固着することが可能となり、ＣＳＰが実装される側の配線基板を小型化することが可能となる。したがって、ＣＳＰを採用することにより、ポータブルエレクトロニクス機器のセット全体を小型化することも可能となる。   In this CSP, a package is formed by dicing a wafer having external connection electrodes (electrode pads) formed on one main surface. Therefore, the CSP can be fixed to the wiring board (mounting board) with the same size as the LSI, and the wiring board on the side where the CSP is mounted can be downsized. Therefore, by adopting CSP, the entire set of portable electronic devices can be reduced in size.

一般に、ＣＳＰとしての回路素子を配線基板の上に搭載するには、回路素子と配線基板のそれぞれの電極パッドをはんだ等からなる金属バンプを介してフリップチップ接続することにより行う（特許文献１参照）。図６は配線基板上に回路素子を実装した従来の回路装置の構造を概略的に示した断面図である。回路素子（半導体素子）１０１の表面周辺部に第１電極パッド１０２が形成され、この回路素子１０１を搭載するための配線基板１０８の表面に第２電極パッド１０９が形成され、はんだからなる金属バンプ１１４を用いて接着されている。
特開平１０−６４９５５号公報 In general, a circuit element as a CSP is mounted on a wiring board by flip-chip connection between the circuit element and each electrode pad of the wiring board via a metal bump made of solder or the like (see Patent Document 1). ). FIG. 6 is a cross-sectional view schematically showing the structure of a conventional circuit device in which circuit elements are mounted on a wiring board. A first electrode pad 102 is formed on the periphery of the surface of the circuit element (semiconductor element) 101, and a second electrode pad 109 is formed on the surface of the wiring substrate 108 for mounting the circuit element 101. 114 is used for bonding.
JP-A-10-64955

しかしながら、上述した従来の回路装置では、第１電極パッド１０２から第２電極パッド１０９までに至る経路が異なる材料から成るため、接続信頼性に劣る問題があった。具体的には、バンプ１１４にははんだが採用され、各電極パッド（第１電極パッド１０２、第２電極パッド１０９）は一般的に銅から成る。このため、バンプ１１４と各電極パッドとでは材料が異なるため、温度変化に応じて両者の界面には熱応力が発生する。したがって、バンプ１１４と各電極パッドとの接合箇所で断線が発生する恐れがあった。   However, the conventional circuit device described above has a problem of poor connection reliability because the path from the first electrode pad 102 to the second electrode pad 109 is made of different materials. Specifically, solder is employed for the bump 114, and each electrode pad (the first electrode pad 102 and the second electrode pad 109) is generally made of copper. For this reason, since the material is different between the bump 114 and each electrode pad, a thermal stress is generated at the interface between the two according to a temperature change. Therefore, there is a possibility that disconnection may occur at the joint between the bump 114 and each electrode pad.

また、従来の回路装置をプリント実装基板に実装する際（具体的には、回路装置の配線基板１０８の裏面側の電極をプリント実装基板上の電極と接続固定する際）に加わる熱処理によって、回路装置内のバンプ１１４が体積膨張し、回路装置内で剥離の起点となることがあるため、回路装置を実装したプリント実装基板の信頼性が劣化する問題がある。   In addition, when the conventional circuit device is mounted on the printed mounting board (specifically, when the electrode on the back side of the wiring board 108 of the circuit device is connected and fixed to the electrode on the printed mounting board), the heat treatment is applied to the circuit. Since the bump 114 in the device expands in volume and may become a starting point of peeling in the circuit device, there is a problem that the reliability of the printed circuit board on which the circuit device is mounted deteriorates.

本発明はこうした状況に鑑みてなされたものであり、その目的は、配線基板とその上に搭載する回路素子との間の接続信頼性に優れた回路装置およびその製造技術を提供することにある。   The present invention has been made in view of such circumstances, and an object of the present invention is to provide a circuit device excellent in connection reliability between a wiring board and a circuit element mounted thereon and a manufacturing technique thereof. .

上記課題を解決するために、本発明に係る回路装置は、第１の電極を有する回路素子と、第２の電極を有する配線基板と、配線基板上に設けられた絶縁層と、第２の電極から絶縁層内に、この第２の電極と一体的に設けられた導体部と、を備え、絶縁層上に回路素子が設置され、この状態で第１の電極と導体部とが接続されていることを特徴とする。   In order to solve the above problems, a circuit device according to the present invention includes a circuit element having a first electrode, a wiring board having a second electrode, an insulating layer provided on the wiring board, A conductor part integrally provided with the second electrode in the insulating layer from the electrode, and a circuit element is installed on the insulating layer, and in this state, the first electrode and the conductor part are connected to each other. It is characterized by.

この発明によれば、回路装置をプリント実装基板上に実装する際に加わる熱処理によって発生する配線基板と回路素子との剥離による断線などを抑制することができる。このため、回路装置の耐熱信頼性（配線基板とその上に搭載する回路素子との間の接続信頼性）が向上する。これは、第２の電極と導体部とを一体化して形成しているため、その部分に接合界面がなくなり、従来のはんだ等の金属バンプを用いた場合に発生する体積膨張に起因した応力負荷が抑制されるためである。   According to the present invention, it is possible to suppress disconnection due to peeling between the wiring board and the circuit element, which is generated by heat treatment applied when the circuit device is mounted on the printed mounting board. For this reason, the heat resistance reliability (connection reliability between a wiring board and a circuit element mounted thereon) is improved. This is because the second electrode and the conductor portion are integrally formed, so that there is no joint interface at that portion, and the stress load caused by the volume expansion that occurs when using conventional metal bumps such as solder This is because it is suppressed.

上記構成において、第１の電極および導体部とは同一の金属からなることが好ましい。この構成によれば、第１の電極と導体部との熱膨張係数が同じになるので、回路装置の熱応力に対する接続信頼性（耐熱信頼性）をさらに向上させることができる。   In the above configuration, the first electrode and the conductor portion are preferably made of the same metal. According to this configuration, since the thermal expansion coefficients of the first electrode and the conductor portion are the same, the connection reliability (heat resistance reliability) against the thermal stress of the circuit device can be further improved.

上記課題を解決するために、本発明に係る回路装置の製造方法は、第１の電極を有する回路素子を用意する第１の工程と、第１の絶縁層の一方の面側に回路素子の第１の電極を有する面を圧着する第２の工程と、第１の絶縁層に、その他方の面側から第１の電極が露出するように開口部を形成する第３の工程と、開口部内を含む絶縁層上に、第１の電極と接続する第１の導電層を形成する第４の工程と、第１の絶縁層の他方の面側に、少なくとも一層の第２の絶縁層と第２の導電層との積層構造からなる配線基板を形成する第５の工程と、を備え、第１の導電層の一部は配線基板の第２の電極として機能することを特徴とする。   In order to solve the above problems, a method of manufacturing a circuit device according to the present invention includes a first step of preparing a circuit element having a first electrode, and a circuit element on one surface side of the first insulating layer. A second step of pressure-bonding the surface having the first electrode; a third step of forming an opening in the first insulating layer so that the first electrode is exposed from the other surface side; A fourth step of forming a first conductive layer connected to the first electrode on the insulating layer including the inside of the portion; and at least one second insulating layer on the other surface side of the first insulating layer; And a fifth step of forming a wiring substrate having a laminated structure with the second conductive layer, wherein a part of the first conductive layer functions as a second electrode of the wiring substrate.

この発明によれば、回路素子の第１の電極と配線基板とが第１の導電層を介して接続され、従来のはんだバンプを介した接続に比べて、熱応力に対する接続信頼性（耐熱信頼性）が向上した回路装置が容易に製造される。   According to the present invention, the first electrode of the circuit element and the wiring board are connected via the first conductive layer, and the connection reliability against heat stress (heat resistance reliability) is compared with the connection via the conventional solder bump. The circuit device with improved characteristics is easily manufactured.

上記構成において、第１の電極および第１の導電層は同一の材料からなるように製造することが好ましい。この構成によれば、第１の電極と第１の導電層との熱膨張係数を容易に同じとすることができるので、熱応力に対する接続信頼性（耐熱信頼性）がさらに向上した回路装置を製造することができる。   In the above structure, the first electrode and the first conductive layer are preferably manufactured to be made of the same material. According to this configuration, since the thermal expansion coefficients of the first electrode and the first conductive layer can be easily made the same, a circuit device with further improved connection reliability (heat resistance reliability) against thermal stress can be obtained. Can be manufactured.

本発明によれば、配線基板とその上に搭載する回路素子との間の接続信頼性に優れた回路装置およびその製造技術が提供される。   ADVANTAGE OF THE INVENTION According to this invention, the circuit apparatus excellent in the connection reliability between a wiring board and the circuit element mounted on it and its manufacturing technique are provided.

以下、本発明を具現化した実施形態について図面に基づいて説明する。なお、すべての図面において、同様な構成要素には同様の符号を付し、適宜説明を省略する。   DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

（第１実施形態）
図１は本発明の第１実施形態に係る回路装置の概略断面図である。図１に基づいて第１実施形態の回路装置について説明する。 (First embodiment)
FIG. 1 is a schematic cross-sectional view of a circuit device according to a first embodiment of the present invention. The circuit device according to the first embodiment will be described with reference to FIG.

この第１実施形態での回路装置は、その表面に電極４ａを有する回路素子５と、その表面に電極７ｃを有する配線基板１２と、配線基板１２と回路素子５との間に設けられた絶
縁層６と、この絶縁層６を貫通し、電極４ａと電極７ｃとを接続する導体部８を備えている。なお、電極４ａは本発明の「第１の電極」および電極７ｃは本発明の「第２の電極」の一例である。 The circuit device according to the first embodiment includes a circuit element 5 having an electrode 4a on its surface, a wiring board 12 having an electrode 7c on its surface, and insulation provided between the wiring board 12 and the circuit element 5. A layer 6 and a conductor portion 8 that penetrates the insulating layer 6 and connects the electrode 4a and the electrode 7c are provided. The electrode 4a is an example of the “first electrode” in the present invention, and the electrode 7c is an example of the “second electrode” in the present invention.

回路素子５は、Ｐ型シリコン基板などの半導体基板１の表面（下面側）に周知の技術により所定の電気回路（図示せず）が形成され、実装面となる表面（特に周辺部）に電極３が形成されている。この電極３を除いた半導体基板１の表面上の領域には保護膜２が形成されている。さらに電極３のピッチをより広くするために、電極３に接続して再配線パターン４および再配線された電極４ａが形成されている。   The circuit element 5 has a predetermined electric circuit (not shown) formed on the surface (lower surface side) of the semiconductor substrate 1 such as a P-type silicon substrate by a well-known technique, and electrodes on the surface (particularly the peripheral portion) to be the mounting surface. 3 is formed. A protective film 2 is formed in a region on the surface of the semiconductor substrate 1 excluding the electrode 3. In order to further increase the pitch of the electrodes 3, a rewiring pattern 4 and a rewiring electrode 4a connected to the electrodes 3 are formed.

配線基板１２は、絶縁層９、絶縁層９の上面側に形成された電極７ｃを含む導電層７、及び絶縁層９の下面側に形成された導電層１０からなる積層構造を有する。上下の導電層はビアホール９ａ内に設けられた導体部１１によって接続されている。この絶縁層９にはエポキシ樹脂を主成分とする膜が採用され、その厚さは、たとえば、約１００μｍである。また、導電層７，１０には銅（Ｃｕ）等の金属が採用され、その厚さは、たとえば、約３０μｍである。   The wiring substrate 12 has a laminated structure including the insulating layer 9, the conductive layer 7 including the electrode 7 c formed on the upper surface side of the insulating layer 9, and the conductive layer 10 formed on the lower surface side of the insulating layer 9. The upper and lower conductive layers are connected by a conductor portion 11 provided in the via hole 9a. The insulating layer 9 is made of a film mainly composed of an epoxy resin and has a thickness of about 100 μm, for example. The conductive layers 7 and 10 are made of a metal such as copper (Cu) and have a thickness of about 30 μm, for example.

絶縁層６は、回路素子５と配線基板１２との間に設けられている。絶縁層６にはエポキシ樹脂を主成分とする膜が採用され、その厚さは、たとえば、約１００μｍである。なお、エポキシ樹脂を主成分とする絶縁層６は、編み込まれたガラス繊維に樹脂を含浸させたタイプの膜であってもよい。あるいは、絶縁層６に約２μｍ〜１０μｍ程度の直径を有するフィラーが添加された膜であってもよい。このフィラーとしては、アルミナ（Ａｌ２Ｏ３）、シリカ（ＳｉＯ２）、窒化アルミニウム（ＡｌＮ）、窒化シリコン（ＳｉＮ）および窒化ホウ素（ＢＮ）などがある。また、フィラーの重量充填率は約３０％〜約８０％である。 The insulating layer 6 is provided between the circuit element 5 and the wiring board 12. A film mainly composed of an epoxy resin is used for the insulating layer 6 and has a thickness of, for example, about 100 μm. The insulating layer 6 mainly composed of an epoxy resin may be a film of a type in which a woven glass fiber is impregnated with a resin. Alternatively, a film in which a filler having a diameter of about 2 μm to 10 μm is added to the insulating layer 6 may be used. Examples of the filler include alumina (Al 2 O 3 ), silica (SiO 2 ), aluminum nitride (AlN), silicon nitride (SiN), and boron nitride (BN). Moreover, the weight filling rate of the filler is about 30% to about 80%.

導体部８は絶縁層６を貫通して形成された開口部６ａ内に設けられ、回路素子５の電極４ａと配線基板１２の電極７ｃとを電気的に接続している。ここで、導体部８は導電層７の電極７ｃと一体的に設けられている。
（製造方法）
図２〜図４は、図１に示した第１実施形態による回路装置の製造プロセスを説明するための断面図である。次に、図１〜図４を参照して、第１実施形態による回路装置の製造プロセスについて説明する。 The conductor 8 is provided in an opening 6 a formed through the insulating layer 6 and electrically connects the electrode 4 a of the circuit element 5 and the electrode 7 c of the wiring board 12. Here, the conductor portion 8 is provided integrally with the electrode 7 c of the conductive layer 7.
(Production method)
2 to 4 are cross-sectional views for explaining a manufacturing process of the circuit device according to the first embodiment shown in FIG. Next, the manufacturing process of the circuit device according to the first embodiment will be described with reference to FIGS.

図２（Ａ）に示すように、その表面に電極４ａを有する回路素子５を用意する。具体的には、Ｐ型シリコン基板などの半導体基板１の表面（下面側）に周知の技術により所定の電気回路（図示せず）およびその周辺部あるいは上部に電極３を形成する。電極３の材料には一般的にアルミニウム（Ａｌ）等の金属が採用される。この電極３を除いた半導体基板１の表面上の領域に、半導体基板１を保護するための絶縁性の保護膜２を形成する。保護膜２としてはシリコン酸化膜（ＳｉＯ２）やシリコン窒化膜（ＳｉＮ）等が採用される。さらに電極３のピッチをより広くするために銅からなる再配線パターン４および電極４ａを形成する。ここでは、レジストパターン形成、銅めっき処理、及びレジスト除去を２回繰り返して所望の再配線パターン４および電極４ａを形成している。 As shown in FIG. 2A, a circuit element 5 having an electrode 4a on its surface is prepared. Specifically, a predetermined electric circuit (not shown) and an electrode 3 are formed on the periphery or top of the semiconductor substrate 1 such as a P-type silicon substrate by a well-known technique. A metal such as aluminum (Al) is generally used as the material of the electrode 3. An insulating protective film 2 for protecting the semiconductor substrate 1 is formed in a region on the surface of the semiconductor substrate 1 excluding the electrode 3. As the protective film 2, a silicon oxide film (SiO 2 ), a silicon nitride film (SiN), or the like is employed. Further, in order to further widen the pitch of the electrodes 3, a rewiring pattern 4 and an electrode 4a made of copper are formed. Here, a desired rewiring pattern 4 and electrode 4a are formed by repeating resist pattern formation, copper plating treatment, and resist removal twice.

図２（Ｂ）に示すように、回路素子５よりも面積の大きな銅箔７ａ付きの絶縁層６に対して回路素子５をその表面（下面側）から真空下または減圧下で熱圧着する。なお、絶縁層６の厚さは、たとえば、約１００μｍとし、銅箔７ａの厚さは、たとえば、約１０μｍとする。絶縁層６としては先に示した材料が採用される。   As shown in FIG. 2B, the circuit element 5 is thermocompression bonded from the surface (lower surface side) to the insulating layer 6 with the copper foil 7a having a larger area than the circuit element 5 under vacuum or reduced pressure. The thickness of the insulating layer 6 is, for example, about 100 μm, and the thickness of the copper foil 7a is, for example, about 10 μm. The material shown above is employ | adopted as the insulating layer 6. FIG.

回路素子５を絶縁層６に圧着することにより、図２（Ｃ）に示すように、絶縁層６内に
回路素子５の電極４ａを含む再配線パターン４が埋め込まれ、絶縁層６上に回路素子５が固着される。 By pressing the circuit element 5 to the insulating layer 6, the rewiring pattern 4 including the electrode 4 a of the circuit element 5 is embedded in the insulating layer 6 as shown in FIG. Element 5 is fixed.

図２（Ｄ）に示すように、フォトリソグラフィ技術およびエッチング技術を用いて開口部６ａ（図１参照）の形成領域に位置する銅箔７ａを除去する。これにより、絶縁層６の開口部６ａの形成領域が露出される。   As shown in FIG. 2D, the copper foil 7a located in the formation region of the opening 6a (see FIG. 1) is removed using a photolithography technique and an etching technique. Thereby, the formation region of the opening 6a of the insulating layer 6 is exposed.

次に、図３（Ａ）に示すように、銅箔７ａの下方から炭酸ガスレーザまたはＵＶレーザを照射することによって、絶縁層６の露出した表面から電極４ａの表面に達するまでの領域を除去する。これにより、絶縁層６に、約７０μｍの直径を有し、絶縁層６を貫通する開口部６ａを形成する。なお、絶縁層６は本発明の「第１の絶縁層」の一例である。   Next, as shown in FIG. 3A, the region from the exposed surface of the insulating layer 6 to the surface of the electrode 4a is removed by irradiating a carbon dioxide laser or UV laser from below the copper foil 7a. . As a result, an opening 6 a having a diameter of about 70 μm and penetrating through the insulating layer 6 is formed in the insulating layer 6. The insulating layer 6 is an example of the “first insulating layer” in the present invention.

図３（Ｂ）に示すように、無電解めっき法を用いて、銅箔７ａの表面および開口部６ａの内面上に銅を約０．５μｍの厚みでめっきする。続いて、電解めっき法を用いて、銅箔７ａの表面および開口部６ａの内部に銅をめっきする。なお、本実施形態では、めっき液中に抑制剤および促進剤を添加することによって、抑制剤を銅箔７ａの表面上に吸着させるとともに、促進剤を開口部６ａの内面上に吸着させる。これにより、開口部６ａの内面上の銅めっきの厚みを大きくすることができるので、開口部６ａ内に銅を埋め込むことができる。その結果、図３（Ｂ）に示すように、絶縁層６上に約３０μｍの厚みを有する導電層７ｂが形成されるとともに、開口部６ａ内に導体部８が埋め込み形成される。   As shown in FIG. 3B, copper is plated to a thickness of about 0.5 μm on the surface of the copper foil 7a and the inner surface of the opening 6a by using an electroless plating method. Subsequently, copper is plated on the surface of the copper foil 7a and the inside of the opening 6a using an electrolytic plating method. In this embodiment, by adding an inhibitor and an accelerator to the plating solution, the inhibitor is adsorbed on the surface of the copper foil 7a and the accelerator is adsorbed on the inner surface of the opening 6a. Thereby, since the thickness of the copper plating on the inner surface of the opening 6a can be increased, copper can be embedded in the opening 6a. As a result, as shown in FIG. 3B, a conductive layer 7b having a thickness of about 30 μm is formed on the insulating layer 6, and a conductor 8 is embedded in the opening 6a.

図３（Ｃ）に示すように、フォトリソグラフィ技術およびエッチング技術を用いて、導電層７ｂをパターニングする。これにより、電極７ｃおよび所定の配線パターンを含む導電層７が形成される。なお、導電層７および導体部８は本発明の「第１の導電層」の一例である。   As shown in FIG. 3C, the conductive layer 7b is patterned by using a photolithography technique and an etching technique. Thereby, the electrode 7c and the conductive layer 7 including a predetermined wiring pattern are formed. The conductive layer 7 and the conductor 8 are examples of the “first conductive layer” in the present invention.

図３（Ｄ）に示すように、銅箔１０ａ付きの絶縁層９を絶縁層６の下面側から真空下または減圧下で熱圧着する。ここで、絶縁層９の厚さは、たとえば、約１００μｍとし、銅箔１０ａの厚さは、たとえば、約１０μｍとする。絶縁層９としては先に示した絶縁層６と同じ材料が採用される。なお、絶縁層９は本発明の「第２の絶縁層」の一例である。   As shown in FIG. 3D, the insulating layer 9 with the copper foil 10a is thermocompression bonded from the lower surface side of the insulating layer 6 under vacuum or under reduced pressure. Here, the thickness of the insulating layer 9 is about 100 μm, for example, and the thickness of the copper foil 10 a is about 10 μm, for example. As the insulating layer 9, the same material as that of the insulating layer 6 shown above is employed. The insulating layer 9 is an example of the “second insulating layer” in the present invention.

銅箔１０ａ付き絶縁層９を圧着することにより、図４（Ａ）に示すように、絶縁層９内に導電層７が埋め込まれる。これにより、絶縁層６の下面側に配線基板１２（図１参照）の基材となる部分が形成される。   By crimping the insulating layer 9 with the copper foil 10a, the conductive layer 7 is embedded in the insulating layer 9, as shown in FIG. Thereby, the part used as the base material of the wiring board 12 (refer FIG. 1) is formed in the lower surface side of the insulating layer 6. FIG.

図４（Ｂ）に示すように、フォトリソグラフィ技術およびエッチング技術を用いてビアホール９ａ（図１参照）の形成領域に位置する銅箔１０ａを除去する。これにより、絶縁層９のビアホール９ａの形成領域が露出される。   As shown in FIG. 4B, the copper foil 10a located in the formation region of the via hole 9a (see FIG. 1) is removed using a photolithography technique and an etching technique. Thereby, the formation region of the via hole 9a in the insulating layer 9 is exposed.

図４（Ｃ）に示すように、銅箔１０ａの下方から炭酸ガスレーザまたはＵＶレーザを照射することによって、絶縁層９の露出した表面から導電層７の表面に達するまでの領域を除去する。これにより、絶縁層９に、約７０μｍの直径を有し、絶縁層９を貫通するビアホール９ａを形成する。   As shown in FIG. 4C, a region from the exposed surface of the insulating layer 9 to the surface of the conductive layer 7 is removed by irradiating a carbon dioxide laser or UV laser from below the copper foil 10a. As a result, a via hole 9 a having a diameter of about 70 μm and penetrating the insulating layer 9 is formed in the insulating layer 9.

図４（Ｄ）に示すように、無電解めっき法を用いて、銅箔１０ａの表面およびビアホール９ａの内面上に銅を約０．５μｍの厚みでめっきする。続いて、電解めっき法を用いて、銅箔１０ａの表面およびビアホール９ａの内部に銅をめっきする。なお、本実施形態では、めっき液中に抑制剤および促進剤を添加することによって、抑制剤を銅箔１０ａの表面上に吸着させるとともに、促進剤をビアホール９ａの内面上に吸着させる。これにより、ビアホール９ａの内面上の銅めっきの厚みを大きくすることができるので、ビアホール
９ａ内に銅を埋め込むことができる。その結果、図４（Ｄ）に示すように、絶縁層９上に約３０μｍの厚みを有する導電層１０ｂが形成されるとともに、ビアホール９ａ内に導体部１１が埋め込み形成される。 As shown in FIG. 4D, copper is plated to a thickness of about 0.5 μm on the surface of the copper foil 10a and the inner surface of the via hole 9a by using an electroless plating method. Subsequently, copper is plated on the surface of the copper foil 10a and the inside of the via hole 9a using an electrolytic plating method. In this embodiment, by adding an inhibitor and an accelerator to the plating solution, the inhibitor is adsorbed on the surface of the copper foil 10a and the accelerator is adsorbed on the inner surface of the via hole 9a. Thereby, since the thickness of the copper plating on the inner surface of the via hole 9a can be increased, copper can be embedded in the via hole 9a. As a result, as shown in FIG. 4D, a conductive layer 10b having a thickness of about 30 μm is formed on the insulating layer 9, and a conductor portion 11 is embedded in the via hole 9a.

最後に、図１に示したように、フォトリソグラフィ技術およびエッチング技術を用いて、導電層１０ｂをパターニングする。これにより、所定の配線パターンを有する導電層１０が形成される。この結果、基材としての絶縁層９、この絶縁層９の上面側に形成された電極７ｃを含む導電層７、及び絶縁層９の下面側に形成された導電層１０の積層構造を有する配線基板１２が形成される。なお、導電層１０は本発明の「第２の導電層」の一例である。   Finally, as shown in FIG. 1, the conductive layer 10b is patterned by using a photolithography technique and an etching technique. Thereby, the conductive layer 10 having a predetermined wiring pattern is formed. As a result, the wiring having a laminated structure of the insulating layer 9 as the base material, the conductive layer 7 including the electrode 7c formed on the upper surface side of the insulating layer 9, and the conductive layer 10 formed on the lower surface side of the insulating layer 9 A substrate 12 is formed. The conductive layer 10 is an example of the “second conductive layer” in the present invention.

これらの工程により、第１実施形態の回路装置が製造される。   Through these steps, the circuit device of the first embodiment is manufactured.

以上説明した第１実施形態の回路装置およびその製造方法によれば、以下のような効果を得ることができるようになる。
（１）回路装置をプリント実装基板上に実装する際、回路装置に加わる熱処理によって発生する配線基板１２と回路素子５との剥離による断線などを抑制することができる。このため、回路装置の耐熱信頼性（配線基板１２とその上に搭載する回路素子５との間の接続信頼性）が向上する。これは、配線基板１２の電極７ｃと導体部８とを一体化して形成したため、その部分に接合界面がなくなり、従来のはんだ等の金属バンプを用いた場合に発生する体積膨張に起因した応力負荷が抑制されるためである。
（２）電極７ｃと導体部８とが一体化された金属で形成したことで、電極７ｃと導体部８との間に接合界面がなくなるので、使用状況下の温度変化等により熱応力が作用しても断線等は生じず、熱応力に対する回路装置の接続信頼性を向上させることができる。
（３）電極４ａと導体部８とを同一の金属としたことで、電極４ａと導体部８との熱膨張係数が同じなるので、使用状況下の温度変化等によりこの部分に熱応力が作用しても断線等の恐れが少ない構成となる。この結果、熱応力に対する回路装置の接続信頼性をさらに向上させることができる。
（４）回路素子５の電極４ａと配線基板１２とが導体部８と一体化した導電層７を介して接続され、従来のはんだバンプを介した接続に比べて、熱応力に対する接続信頼性が向上した回路装置が容易に製造される。
（５）電極４ａおよび導電層７（特に導体部８）を同一の材料で製造したことで、電極４ａと導電層７（特に導体部８）との熱膨張係数を容易に同じとすることができるので、熱応力に対する接続信頼性がさらに向上した回路装置を製造することができるようになる。（６）回路素子５と配線基板１２とを接続する導体部８および絶縁層６の製造を、配線基板１２を構成する絶縁層９および導電層１０と同じプロセスをそのまま採用して形成できるので、新たな設備投資をすることなく、低コストで回路装置を製造することができる。（７）回路素子５と配線基板１２との間の間隔を絶縁層６の膜厚により容易に制御できるので、回路装置の薄型化を容易に実現することができる。 According to the circuit device and the manufacturing method thereof according to the first embodiment described above, the following effects can be obtained.
(1) When the circuit device is mounted on the printed circuit board, disconnection due to peeling between the wiring board 12 and the circuit element 5 caused by heat treatment applied to the circuit device can be suppressed. For this reason, the heat resistance reliability of the circuit device (connection reliability between the wiring board 12 and the circuit element 5 mounted thereon) is improved. This is because the electrode 7c and the conductor portion 8 of the wiring board 12 are integrally formed, so that there is no bonding interface at that portion, and the stress load caused by the volume expansion generated when a conventional metal bump such as solder is used. This is because it is suppressed.
(2) Since the electrode 7c and the conductor portion 8 are formed of an integrated metal, there is no bonding interface between the electrode 7c and the conductor portion 8, so that a thermal stress acts due to a temperature change or the like under use conditions. However, disconnection or the like does not occur, and the connection reliability of the circuit device against thermal stress can be improved.
(3) Since the electrode 4a and the conductor portion 8 are made of the same metal, the thermal expansion coefficient of the electrode 4a and the conductor portion 8 is the same. Even in this case, there is little risk of disconnection or the like. As a result, the connection reliability of the circuit device against thermal stress can be further improved.
(4) The electrode 4a of the circuit element 5 and the wiring board 12 are connected via the conductive layer 7 integrated with the conductor portion 8, and the connection reliability against the thermal stress is higher than the connection via the conventional solder bump. Improved circuit devices are easily manufactured.
(5) Since the electrode 4a and the conductive layer 7 (especially the conductor part 8) are manufactured from the same material, the thermal expansion coefficients of the electrode 4a and the conductive layer 7 (especially the conductor part 8) can be easily made the same. Therefore, it is possible to manufacture a circuit device with further improved connection reliability against thermal stress. (6) Since the conductor 8 and the insulating layer 6 that connect the circuit element 5 and the wiring board 12 can be formed by directly adopting the same process as that of the insulating layer 9 and the conductive layer 10 constituting the wiring board 12, A circuit device can be manufactured at low cost without making new capital investment. (7) Since the distance between the circuit element 5 and the wiring board 12 can be easily controlled by the film thickness of the insulating layer 6, it is possible to easily realize a thin circuit device.

（第２実施形態）
図５は本発明の第２実施形態に係る概略断面図である。第１実施形態と異なる箇所は、回路素子５に第１実施形態での再配線パターン４および電極４ａを設けず、配線基板１２ａと接続する導体部８ａが半導体基板１上の電極３と直接接続していることである。それ以外については、第１実施形態と同様である。 (Second Embodiment)
FIG. 5 is a schematic cross-sectional view according to the second embodiment of the present invention. The difference from the first embodiment is that the circuit element 5 is not provided with the rewiring pattern 4 and the electrode 4a in the first embodiment, and the conductor portion 8a connected to the wiring board 12a is directly connected to the electrode 3 on the semiconductor substrate 1. Is. The rest is the same as in the first embodiment.

この第２実施形態の回路装置およびその製造方法によれば、以下のような効果を得ることができるようになる。
（８）従来、半導体基板１上の電極３間のピッチは、たとえば、約７０μｍと非常に狭く、このままでははんだバンプ接続が困難であるため、回路素子の小型化を犠牲にして半導体基板１上に再配線パターンおよびそれに連結して設けられた電極を形成していた。これ
により、再配線後の電極間のピッチは約５００μｍとなり、はんだバンプ接続を容易に行えるようにしていた。この実施形態によれば、半導体基板１の電極３を再配線することなく、回路素子５と配線基板１２ａとを接続することができるので、再配線パターン部分の領域削減による回路素子５の小型化、さらには回路装置の小型化を実現することができる。 According to the circuit device and the manufacturing method thereof of the second embodiment, the following effects can be obtained.
(8) Conventionally, the pitch between the electrodes 3 on the semiconductor substrate 1 is very narrow, for example, about 70 μm, and it is difficult to connect the solder bumps as it is. Therefore, on the semiconductor substrate 1 at the expense of miniaturization of circuit elements. A rewiring pattern and an electrode connected to the rewiring pattern are formed. As a result, the pitch between the electrodes after rewiring is about 500 μm so that the solder bumps can be easily connected. According to this embodiment, since the circuit element 5 and the wiring board 12a can be connected without rewiring the electrodes 3 of the semiconductor substrate 1, the circuit element 5 can be downsized by reducing the area of the rewiring pattern portion. Furthermore, the circuit device can be reduced in size.

なお、上記実施形態では、配線基板上に１つの回路素子を搭載した回路装置の例を示したが、本発明はこれに限らず、たとえば、図２（Ｂ）で示した工程において絶縁層上に複数の回路素子を圧着してもよい。この場合、配線基板とそれぞれの回路素子との間で熱応力に対する接続信頼性を向上させることができるようになる。   In the above embodiment, an example of a circuit device in which one circuit element is mounted on a wiring board has been shown. However, the present invention is not limited to this, and for example, on the insulating layer in the process shown in FIG. A plurality of circuit elements may be pressure-bonded to each other. In this case, the connection reliability against thermal stress can be improved between the wiring board and each circuit element.

上記実施形態では、配線基板上に１つの回路素子を搭載した回路装置の製造方法の例を示したが、本発明はこれに限らず、たとえば、回路素子を個別に切断する前のウエハ状態の半導体基板（回路素子となる部分がアレイ状に複数の形成された半導体基板）を絶縁層上に圧着し、上記と同様の工程を経て配線基板部分を形成した後、それをダイシングにより個別に切断して複数の回路装置を製造してもよい。この場合にも個々の回路装置は上記効果を享受することができる。   In the above-described embodiment, an example of a method of manufacturing a circuit device in which one circuit element is mounted on a wiring board has been shown. However, the present invention is not limited to this, and for example, a wafer state before the circuit elements are individually cut. A semiconductor substrate (semiconductor substrate on which a plurality of circuit element portions are formed in an array) is pressure-bonded onto an insulating layer, a wiring substrate portion is formed through the same process as described above, and then cut individually by dicing. Thus, a plurality of circuit devices may be manufactured. Even in this case, each circuit device can enjoy the above-described effect.

上記実施形態では、基材としての絶縁層９、この絶縁層の９上面側に形成された電極７ｃを含む導電層７、及び絶縁層９の下面側に形成された導電層１０の２層配線構造の配線基板１２の例を示したが、本発明はこれに限らず、たとえば、絶縁層９の下面側にさらに絶縁層および配線層を交互に積層した多層配線構造の配線基板としてもよい。   In the above embodiment, the two-layer wiring of the insulating layer 9 as the base material, the conductive layer 7 including the electrode 7c formed on the upper surface side of the insulating layer 9, and the conductive layer 10 formed on the lower surface side of the insulating layer 9 Although the example of the wiring board 12 having the structure is shown, the present invention is not limited to this, and for example, a wiring board having a multilayer wiring structure in which insulating layers and wiring layers are alternately laminated on the lower surface side of the insulating layer 9 may be used.

上記実施形態では、回路素子５に再配線パターン４および電極４ａを形成した例を示したが、本発明はこれに限らず、たとえば、再配線パターン４のみを形成するだけでもよい。また、その形成は、保護膜２上に樹脂層を貼り付け、この樹脂層にレーザ加工によって開口部を形成し、その開口部に銅めっき処理を行い、最後にエッチングして所望の再配線パターンに加工する方法で行ってもよい。   In the above-described embodiment, an example in which the rewiring pattern 4 and the electrode 4a are formed on the circuit element 5 has been described. However, the present invention is not limited thereto, and for example, only the rewiring pattern 4 may be formed. In addition, the resin layer is formed on the protective film 2, an opening is formed in the resin layer by laser processing, copper plating is performed on the opening, and finally, a desired rewiring pattern is etched. You may carry out by the method processed into.

本発明の第１実施形態に係る回路装置の概略断面図。1 is a schematic cross-sectional view of a circuit device according to a first embodiment of the present invention. （Ａ）〜（Ｄ）図１に示した第１実施形態による回路装置の製造プロセスを説明するための断面図。(A)-(D) Sectional drawing for demonstrating the manufacturing process of the circuit apparatus by 1st Embodiment shown in FIG. （Ａ）〜（Ｄ）図１に示した第１実施形態による回路装置の製造プロセスを説明するための断面図。(A)-(D) Sectional drawing for demonstrating the manufacturing process of the circuit apparatus by 1st Embodiment shown in FIG. （Ａ）〜（Ｄ）図１に示した第１実施形態による回路装置の製造プロセスを説明するための断面図。(A)-(D) Sectional drawing for demonstrating the manufacturing process of the circuit apparatus by 1st Embodiment shown in FIG. 本発明の第２実施形態に係る回路装置の概略断面図。The schematic sectional drawing of the circuit apparatus which concerns on 2nd Embodiment of this invention. 従来の回路装置の構造を概略的に示した断面図。Sectional drawing which showed the structure of the conventional circuit device roughly.

符号の説明Explanation of symbols

１・・・半導体基板、２・・・保護膜、３・・・電極、４・・・再配線パターン、４ａ・・・電極、５・・・回路素子、６・・・絶縁層、６ａ・・・開口部、７・・・導電層、７ｃ・・・電極、８・・・導体部、９・・・絶縁層、９ａ・・・ビアホール、１０・・・導電層、１１・・・導体部、１２・・・配線基板   DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Protective film, 3 ... Electrode, 4 ... Rewiring pattern, 4a ... Electrode, 5 ... Circuit element, 6 ... Insulating layer, 6a ..Opening portion, 7 ... conductive layer, 7c ... electrode, 8 ... conductor portion, 9 ... insulating layer, 9a ... via hole, 10 ... conductive layer, 11 ... conductor Part, 12 ... wiring board

Claims (4)

第１の電極を有する回路素子と、
第２の電極を有する配線基板と、
前記配線基板上に設けられた絶縁層と、
前記第２の電極から前記絶縁層内に、この第２の電極と一体的に設けられた導体部と、を備え、
前記絶縁層上に前記回路素子が設置され、この状態で前記第１の電極と前記導体部とが接続されている回路装置。 A circuit element having a first electrode;
A wiring board having a second electrode;
An insulating layer provided on the wiring board;
A conductor portion provided integrally with the second electrode in the insulating layer from the second electrode,
A circuit device in which the circuit element is installed on the insulating layer, and the first electrode and the conductor are connected in this state. 前記第１の電極および前記導体部とは同一の金属からなる請求項１に記載の回路装置。   The circuit device according to claim 1, wherein the first electrode and the conductor are made of the same metal. 第１の電極を有する回路素子を用意する第１の工程と、
第１の絶縁層の一方の面側に前記回路素子の前記第１の電極を有する面を圧着する第２の工程と、
前記第１の絶縁層に、その他方の面側から前記第１の電極が露出するように開口部を形成する第３の工程と、
前記開口部内を含む前記絶縁層上に、前記第１の電極と接続する第１の導電層を形成する第４の工程と、
前記第１の絶縁層の他方の面側に、少なくとも一層の第２の絶縁層と第２の導電層との積層構造からなる配線基板を形成する第５の工程と、
を備え、
前記第１の導電層の一部は前記配線基板の第２の電極として機能することを特徴とした回路装置の製造方法。 A first step of preparing a circuit element having a first electrode;
A second step of pressure bonding the surface of the circuit element having the first electrode to one surface side of the first insulating layer;
A third step of forming an opening in the first insulating layer so that the first electrode is exposed from the other surface side;
A fourth step of forming a first conductive layer connected to the first electrode on the insulating layer including the inside of the opening;
A fifth step of forming a wiring substrate having a laminated structure of at least one second insulating layer and a second conductive layer on the other surface side of the first insulating layer;
With
A part of said 1st conductive layer functions as a 2nd electrode of the said wiring board, The manufacturing method of the circuit apparatus characterized by the above-mentioned. 前記第１の電極および前記第１の導電層は同一の材料からなる請求項３に記載の回路装置の製造方法。   The method for manufacturing a circuit device according to claim 3, wherein the first electrode and the first conductive layer are made of the same material.
JP2006180860A 2006-06-30 2006-06-30 Circuit apparatus, and its manufacturing method Withdrawn JP2008010706A (en)

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