JP2008005001A - Chopper comparator and successive comparison a/d converter employing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a successive comparison A/D converter capable of carrying out high speed A/D conversion at a low voltage. <P>SOLUTION: A chopper comparator disclosed herein is provided with a transmission gate TG 4 for setting an input voltage of the chopper comparator, that is, a voltage at an input terminal of a first capacitor C1 to an initial voltage of 0.5 Vdd. The transmission gate TG 4 comprises a CMOS transmission gate. Further, turning ON/OFF of transmission gates TG3A, TG3B is controlled by a first sampling signal SAMPTG1 and turning ON/OFF of a transmission gate TG4 is controlled by a second sampling signal SAMPTG2. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a chopper comparator and a successive approximation A / D converter using the same.

  Conventionally, a successive approximation A / D converter is built in a microcomputer or the like, but in recent years, a successive approximation A / D converter capable of high-speed conversion at a low voltage is required. A successive approximation type A / D converter using this type of chopper type comparator will be described with reference to FIGS.

  This successive approximation A / D converter uses a comparator unit and a D / A conversion unit using a ladder resistor. The D / A converter is connected between the power supply voltage Vdd and the ground voltage Vss, and n ladder resistors RX1, RX2,... RXn that divide the power supply voltage Vdd, and connection points of these ladder resistors. (N−1) transmission gates TGX1, TGX2,. And a control circuit CONT for selectively turning on -1.

  The comparator unit has a function of comparing the output voltage DAout of the D / A conversion unit and the analog input voltage ANIN, and is configured by a two-stage chopper type comparator. The first stage chopper type comparator is turned on in response to the data sampling signal DATASAMP, is turned on in response to the transmission gate TG1 for applying the analog input voltage ANIN to the first capacitor C1, and the reference sampling signal REFSAMP, and is D / A converted. Part of the output voltage DAout applied to the first capacitor C1, the first inverter IV1 connected to the output terminal of the first capacitor C1, the first inverter IV1 connected to the output terminal of the first capacitor C1, and turned on in response to the sampling signal SAMPTG. A transmission gate TG3A for short-circuiting the input and the output of the first NMOS (M1) which switches according to the A / D conversion start signal / ADSTART.

  The second-stage chopper comparator is provided to amplify the output of the first stage, and is connected to the output terminals of the second capacitor C2 and the second capacitor C2 to which the output of the first inverter IV1 is applied. The second inverter IV2 is turned on in response to the sampling signal SAMPTG, the transmission gate TG3B that short-circuits the input and output of the second inverter IV2, and the second NMOS that is switched in response to the A / D conversion start signal / ADSTART ( M2).

  A latch circuit LH is provided for latching the output of the second-stage chopper comparator based on the A / D conversion result sampling signal RESAMP. The control circuit CONT selectively turns on the transmission gates TGX1, TGX2,... TGXn-1 according to the output of the latch circuit LH.

  The operation of this successive approximation A / D converter will be described with reference to the timing chart of FIG. First, before the start of A / D conversion, the A / D conversion start signal / ADSTART is high, the first NMOS (M1) and the second NMOS (M2) are in the on state, and the first inverter IV1, The input of the second inverter IV2 is fixed to low (ground voltage). This prevents a through current from flowing through the first inverter IV1 and the second inverter IV2.

  Thereafter, when the A / D conversion start signal / ADSTART goes low, the first NMOS (M1) and the second NMOS (M2) are turned off. When the data sampling signal DATASAMP and the sampling signal SAMPTG sequentially become high, the transmission gate TG1 is turned on, the analog input voltage ANIN is applied to the input terminal of the first capacitor C1, and the transmission gates TG3A and TG3B are turned on. The input and output of the first inverter IV1 and the input and output of the second inverter IV2 are short-circuited.

  Then, the input of the first inverter IV1 is set to the threshold value Vt1 of the first inverter IV1, and the input of the second inverter IV2 is set to the threshold value Vt2 of the second inverter IV2. As a result, the first capacitor C1 is charged with a voltage of (ANIN−Vt1).

  Thereafter, when the data sampling signal DATASAMP and the sampling signal SAMPTG sequentially become low, the transmission gate TG1, the transmission gates TG3A, and TG3B are turned off. Thereafter, when the reference sampling signal REFSAMP becomes high, the transmission gate TG2 is turned on, and the output voltage DAout of the D / A converter is applied to the input terminal of the first capacitor C1. At this time, the output voltage DAout is set to Vdd / 2 by the control circuit CONT.

  Then, since the input terminal of the first capacitor C1 changes from ANIN to Vdd / 2, the output terminal of the first capacitor C1, that is, the input of the first inverter IV1 changes to (Vdd / 2−ANIN + Vt1). . Thus, the first inverter IV1 compares the magnitudes of ANIN and Vdd / 2. That is, when ANIN> Vdd / 2, the first inverter IV1 outputs high, and when ANIN <Vdd / 2, the first inverter IV1 outputs low. The output of the first inverter IV1 is amplified by the second-stage chopper comparator, and is latched by the latch circuit LH based on the rising edge of the A / D conversion result sampling signal RESAMP. Thereby, the most significant bit (MSB) is determined.

  After that, the reference sampling signal REFSAMP sequentially becomes high, the output voltage DAout corresponding to the A / D conversion result of the upper bits is sequentially output from the D / A converter, and this is sequentially compared with Vref. For example, if ANIN> Vdd / 2 as a result of the first comparison, the output voltage DAout = 3 / 4Vdd is obtained in the second comparison, and 3 / 4Vdd is compared with ANIN, and one of the most significant bits is compared. The MSB-1 bit, which is the lower bit, is determined. By sequentially performing such comparison operations, the analog input voltage ANIN is converted into an n-bit digital signal.

This type of chopper comparator and a successive approximation A / D converter using the comparator are described in Patent Document 1.
Japanese Patent Laid-Open No. 9-83316

  In the successive approximation A / D converter described above, the analog input voltage ANIN and the output voltage DAout are sampled to the input terminal of the first capacitor C1 of the chopper comparator via the transmission gates TG1 and TG2. The transmission gates TG1 and TG2 are composed of CMOS transmission gates. The transmission gates TG1 and TG2 are as shown in the circuit diagram of FIG.

  When the transmission gates TG1 and TG2 are on, the power supply voltage Vdd is applied to the NMOS gate and the ground voltage Vss is applied to the PMOS. However, as shown in FIG. 5B, when the input voltage is around 0.5 Vdd, the impedances of the transmission gates TG1 and TG2 rapidly increase. Moreover, the tendency becomes more remarkable when Vdd becomes a low voltage.

  Therefore, in the vicinity of ANIN = 0.5 Vdd, when high-speed operation is performed with a low voltage (low power supply voltage Vdd), the first capacitor C1 of the chopper comparator cannot be charged, and the comparison accuracy of the chopper comparator is high. As a result, the A / D conversion accuracy deteriorates. Further, since the transmission gates TG1 and TG2 are turned off after the A / D conversion is completed, the previously converted charge remains, which adversely affects the next sampling.

  The chopper type comparator of the present invention has been made in view of the above-described problems, and includes a capacitor, a first switching circuit that sequentially applies a first signal and a second signal to an input terminal of the capacitor, An inverter connected to the output terminal of the capacitor, and when the first signal is applied to the input terminal of the capacitor, the output terminal and the input terminal of the inverter are short-circuited, and the second input terminal is connected to the input terminal of the capacitor. A second switching circuit that releases the short circuit before the first signal is applied, and an initial input to the capacitor input terminal before the first signal and the second signal are applied to the input terminal of the capacitor. And an initialization circuit for applying a voltage.

  According to the chopper type comparator having such a configuration, the capacitor is charged with an initial voltage (near 0.5 Vdd) at which the impedance of the first switching circuit becomes the highest, and then the first signal and the second signal are supplied. By sequentially sampling to the capacitor, good comparison accuracy can be ensured even at low voltage and high speed operation.

  The successive approximation A / D converter according to the present invention includes a ladder resistor that divides a power supply voltage to generate a plurality of divided voltages, a chopper comparator that compares the reference voltage and the divided voltage, and And a control circuit that selects the divided voltage according to the comparison result of the chopper type comparator, wherein the chopper type comparator is used as the chopper type comparator.

  According to the successive approximation A / D converter having such a configuration, a high-speed A / D conversion at a low voltage is possible by using a chopper type comparator including an initialization circuit.

  According to the chopper type comparator of the present invention, since the initialization circuit is provided, high-speed comparison at a low voltage is possible. Further, according to the successive approximation A / D converter of the present invention, a high-speed A / D conversion at a low voltage is possible by using a chopper comparator provided with an initialization circuit.

  A successive approximation A / D converter using a chopper comparator according to an embodiment of the present invention will be described with reference to FIGS.

  As shown in FIG. 1, the present invention is characterized in that a transmission gate is used as an initialization circuit for setting the input voltage of a chopper comparator, that is, the voltage of the input terminal of the first capacitor C1 to an initial voltage of 0.5 Vdd. This is the point where TG4 is provided. The transmission gate TG4 is composed of a CMOS transmission gate as shown in FIG. The on / off of the transmission gates TG3A and TG3B is controlled by the first sampling signal SAMPTG1, and the on / off of the transmission gate TG4 is controlled by the second sampling signal SAMPTG2. Other configurations are the same as those of the circuit of FIG.

  Next, the operation of the successive approximation A / D converter will be described with reference to the timing chart of FIG. First, before the start of A / D conversion, the A / D conversion start signal / ADSTART is high, the first NMOS (M1) and the second NMOS (M2) are in the on state, and the first inverter IV1, The input of the second inverter IV2 is fixed to low (ground voltage). This prevents a through current from flowing through the first inverter IV1 and the second inverter IV2.

  Thereafter, when the A / D conversion start signal / ADSTART goes low, the first NMOS (M1) and the second NMOS (M2) are turned off. When the first sampling signal SAMPTG1 and the second sampling signal SAMPTG2 become high, the transmission gates TG3A, TG3B, and TG4 are turned on.

  Then, the input and output of the first inverter IV1, the input and output of the second inverter IV2 are short-circuited, and the input terminal of the first capacitor C1 and the output of the first inverter IV1 are short-circuited. The input and output of the first inverter IV1 are set to the threshold value Vt1 of the first inverter IV1, and the input and output of the second inverter IV2 are set to the threshold value Vt2 of the second inverter IV2. When the output of the first inverter IV1 is set to the threshold value Vt1 of the first inverter IV1, the voltage at the input terminal of the first capacitor C1 is initially set to the threshold value Vt1 via the transmission gate TG4. The

  Here, the first inverter IV1 is a CMOS inverter, and the threshold value Vt1 is supplied to the first inverter IV1 by adjusting the size ratio (channel width W / channel length L) of PMOS and NMOS. It can be set to 0.5 Vdd which is half of the power supply voltage Vdd. Then, the voltage at the input terminal of the first capacitor C1 is initialized to 0.5 Vdd.

  Thereafter, when the second sampling signal SAMPTG2 becomes low, the transmission gate TG4 is turned off. Thereafter, when the data sampling signal DATASAMP becomes high, the transmission gate TG1 is turned on and the analog input voltage ANIN is applied to the input terminal of the first capacitor C1. As a result, the first capacitor C1 is charged with a voltage of (ANIN−Vt1).

  At this time, if the analog input voltage ANIN is close to 0.5 Vdd, the impedance of the transmission gate TG1 is high, but the voltage of the input terminal of the first capacitor C1 is already initially set to 0.5 Vdd. Can be minimized. On the other hand, when the analog input voltage ANIN is a value away from 0.5 Vdd, the impedance of the transmission gate TG1 is low, and therefore the voltage (ANIN−Vt1) is high in the first capacitor C1 via the transmission gate TG1. Is charged.

  Thereafter, the operation is the same as that of the conventional circuit, and when the data sampling signal DATASAMP and the sampling signal SAMPTG sequentially become low, the transmission gate TG1, the transmission gates TG3A, and TG3B are turned off. Thereafter, when the reference sampling signal REFSAMP becomes high, the transmission gate TG2 is turned on, and the output voltage DAout of the D / A converter is applied to the input terminal of the first capacitor C1. At this time, the output voltage DAout is set to Vdd / 2 by the control circuit CONT.

  Then, since the input terminal of the first capacitor C1 changes from ANIN to Vdd / 2, the output terminal of the first capacitor C1, that is, the input of the first inverter IV1 changes to (Vdd / 2−ANIN + Vt1). . Thus, the first inverter IV1 compares the magnitudes of ANIN and Vdd / 2. That is, when ANIN> Vdd / 2, the first inverter IV1 outputs high, and when ANIN <Vdd / 2, the first inverter IV1 outputs low.

  The output of the first inverter IV1 is amplified by the second-stage chopper comparator, and is latched by the latch circuit LH based on the rising edge of the A / D conversion result sampling signal RESAMP. Thereby, the most significant bit (MSB) is determined.

  After that, the reference sampling signal REFSAMP sequentially becomes high, the output voltage DAout corresponding to the A / D conversion result of the upper bits is sequentially output from the D / A converter, and this is sequentially compared with Vref. For example, if ANIN> Vdd / 2 as a result of the first comparison, the output voltage DAout = 3 / 4Vdd is obtained in the second comparison, and 3 / 4Vdd is compared with ANIN, and one of the most significant bits is compared. The MSB-1 bit, which is the lower bit, is determined. By sequentially performing such comparison operations, the analog input voltage ANIN is converted into an n-bit digital signal.

  As described above, since the voltage of the input terminal of the first capacitor C1 is initially set to 0.5 Vdd, a high-speed comparison operation with the reference voltage is possible even when the analog input voltage ANIN is around 0.5 Vdd. As a result, high-speed A / D conversion can be performed with high accuracy.

1 is a circuit diagram of a successive approximation A / D converter according to an embodiment of the present invention. FIG. 3 is a timing diagram of the successive approximation A / D converter according to the embodiment of the present invention. It is a circuit diagram of a successive approximation A / D converter of a conventional example. It is a timing diagram of the successive approximation type A / D converter of the conventional example. It is the circuit diagram of a transmission gate, and its characteristic diagram.

Explanation of symbols

C1 first capacitor C2 second capacitor IV1 first inverter IV2 second inverter LH latch circuit M1 first NMOS M2 second NMOS
RX1, RX2, ... RXn Ladder resistors TG1, TG2, TG3A, TG3B, TG4 Transmission gates TGX1, TGX2, ... TGXn-1 Transmission gates

Claims (5)

A capacitor;
A first switching circuit for sequentially applying a first signal and a second signal to an input terminal of the capacitor;
An inverter connected to the output terminal of the capacitor;
When the first signal is applied to the input terminal of the capacitor, the output terminal and the input terminal of the inverter are short-circuited, and the short circuit is released before the second signal is applied to the input terminal of the capacitor. A second switching circuit that
An initialization circuit that applies an initial voltage to the input terminal of the capacitor before the first signal and the second signal are applied to the input terminal of the capacitor. The first switching circuit includes a first transmission gate to which a first signal is applied, and a second transmission gate to which a second signal is applied. Chopper type comparator. 2. The chopper type comparator according to claim 1, wherein the second switching circuit includes a third transmission gate connected between an output terminal and an input terminal of the inverter. 2. The chopper type comparator according to claim 1, wherein the initialization circuit includes a fourth transmission gate connected between an output terminal of the inverter and an input terminal of the capacitor. A ladder resistor that divides a power supply voltage to generate a plurality of divided voltages, a chopper comparator that compares a reference voltage with the divided voltage, and the divided voltage selected according to the comparison result of the chopper comparator And a control circuit that
5. A successive approximation A / D converter using the chopper type comparator according to claim 1 as the chopper type comparator.

Images