JP2008004625A - Storage element and memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable storage element by inhibiting an increase in temperature of an insulation layer region. <P>SOLUTION: The storage element 3 has a storage layer 17 for keeping information by a magnetization state of a magnetic material. A magnetization fixing layer 31 is provided on the storage layer 17 via an intermediate layer 16 made of an insulator. The orientation of the magnetization M1 of the storage layer 17 is changed by impregnating electrons which are spin-polarized in the lamination direction to have the information recorded in the layer 17. A coefficient of thermal conductivity of ferromagnetic layers 17, 15 and 13 constituting the storage layer 17 or the magnetization fixing layer 31 is 30 W/(km) or higher. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention comprises a storage layer for storing the magnetization state of a ferromagnetic layer as information and a magnetization fixed layer whose magnetization direction is fixed, and a current is passed in a direction perpendicular to the film surface to spin-polarized electrons. The present invention relates to a memory element that changes the magnetization direction of the memory layer by injecting, and a memory including the memory element, and is suitable for application to a nonvolatile memory.

In information devices such as computers, DRAMs with high speed and high density are widely used as random access memories.
However, since DRAM is a volatile memory in which information disappears when the power is turned off, a nonvolatile memory in which information does not disappear is desired.

  As a candidate for a non-volatile memory, a magnetic random access memory (MRAM) that records information by magnetization of a magnetic material has attracted attention and is being developed (for example, see Non-Patent Document 1).

  In the MRAM, current is supplied to two types of address lines (word lines and bit lines) that are substantially orthogonal to each other, and the magnetization of the magnetic layer of the magnetic memory element at the intersection of the address lines is caused by a current magnetic field generated from each address line. Inverted information is recorded.

A schematic diagram (perspective view) of a general MRAM is shown in FIG.
A drain region 108, a source region 107, and a gate electrode 101 constituting a selection transistor for selecting each memory cell are formed in a portion separated by the element isolation layer 102 of the semiconductor substrate 110 such as a silicon substrate. Has been.
A word line 105 extending in the front-rear direction in the figure is provided above the gate electrode 101.
The drain region 108 is formed in common to the left and right selection transistors in the drawing, and a wiring 109 is connected to the drain region 108.
A magnetic storage element 103 having a storage layer whose magnetization direction is reversed is disposed between the word line 105 and the bit line 106 disposed above and extending in the horizontal direction in the drawing. The magnetic memory element 103 is composed of, for example, a magnetic tunnel junction element (MTJ element).
Further, the magnetic memory element 103 is electrically connected to the source region 107 via the horizontal bypass line 111 and the vertical contact layer 104.
By applying current to each of the word line 105 and the bit line 106, a current magnetic field is applied to the magnetic memory element 103, thereby reversing the magnetization direction of the memory layer of the magnetic memory element 103 and recording information. be able to.

In order to stably hold recorded information in a magnetic memory such as MRAM, it is necessary that a magnetic layer (storage layer) for recording information has a certain coercive force.
On the other hand, in order to rewrite the recorded information, a certain amount of current must be passed through the address wiring.
However, as the elements constituting the MRAM are miniaturized, the amount of current required for reversing the direction of magnetization tends to increase. On the other hand, the address wiring also becomes thin, so that a sufficient current cannot flow.

Accordingly, attention has been paid to a memory having a configuration using magnetization reversal by spin injection as a configuration capable of performing magnetization reversal with a smaller current (for example, Patent Document 1, Patent Document 2, Non-Patent Document 2, and Non-Patent Document 3). reference).
Magnetization reversal by spin injection is to cause magnetization reversal in another magnetic material by injecting spin-polarized electrons that have passed through the magnetic material into another magnetic material.

  For example, when a current is passed through a giant magnetoresistive element (GMR element) or a magnetic tunnel junction element (MTJ element) in a direction perpendicular to the film surface, magnetization of at least a part of the magnetic layer of these elements is performed. Can be reversed.

  Magnetization reversal by spin injection has an advantage that magnetization reversal can be realized without increasing current even if the element is miniaturized.

7 and 8 are schematic views of a memory having a configuration using the above-described magnetization reversal by spin injection. 7 is a perspective view, and FIG. 8 is a cross-sectional view.
A drain region 58, a source region 57, and a gate electrode 51 constituting a selection transistor for selecting each memory cell are formed in a portion separated by the element isolation layer 52 of the semiconductor substrate 60 such as a silicon substrate. Has been. Among these, the gate electrode 51 also serves as a word line extending in the front-rear direction in FIG.
The drain region 58 is formed in common with the left and right selection transistors in FIG. 7, and a wiring 59 is connected to the drain region 58.
A storage element 53 having a storage layer in which the direction of magnetization is reversed by spin injection is disposed between the source region 57 and the bit line 56 disposed above and extending in the left-right direction in FIG.
The storage element 53 is configured by, for example, a magnetic tunnel junction element (MTJ element). In the figure, reference numerals 61 and 62 denote magnetic layers. Of the two magnetic layers 61 and 62, one magnetic layer is a magnetization fixed layer whose magnetization direction is fixed, and the other magnetic layer is a magnetization direction. A changing magnetization free layer, that is, a storage layer is used.
The storage element 53 is connected to the bit line 56 and the source region 57 via the upper and lower contact layers 54, respectively. As a result, a current can be passed through the memory element 53 to reverse the magnetization direction of the memory layer by spin injection.

In the case of a memory configured to use such magnetization reversal by spin injection, the device structure can be simplified as compared with the general MRAM shown in FIG. 9, and therefore high density can be achieved. , Also has the feature.
Further, by utilizing magnetization reversal by spin injection, there is an advantage that the write current does not increase even when the element is miniaturized as compared with a general MRAM in which magnetization reversal is performed by an external magnetic field.

  In the case of an MRAM, a write wiring (word line or bit line) is provided separately from a memory element, and information is written (recorded) by a current magnetic field generated by passing a current through the write wiring. Therefore, a sufficient amount of current required for writing can be passed through the write wiring.

On the other hand, in a memory configured to use magnetization reversal by spin injection, it is necessary to reverse the magnetization direction of the storage layer by performing spin injection with a current flowing through the storage element.
Since the current is directly supplied to the memory element and information is written (recorded) as described above, the memory cell is configured by connecting the memory element to a selection transistor in order to select a memory cell to be written. In this case, the current flowing through the memory element is limited to the magnitude of the current that can flow through the selection transistor (the saturation current of the selection transistor).
Therefore, it is necessary to perform writing with a current lower than the saturation current of the selection transistor, and it is necessary to improve the efficiency of spin injection and reduce the current flowing through the memory element.

Also, in order to increase the read signal, it is necessary to secure a large rate of change in magnetoresistance. To that end, a memory element having a tunnel insulating layer (tunnel barrier layer) as an intermediate layer in contact with both sides of the memory layer is required. The configuration is effective.
When the tunnel insulating layer is used as the intermediate layer as described above, the amount of current flowing through the memory element is limited in order to prevent the tunnel insulating layer from being broken down. From this viewpoint, it is necessary to suppress the current during spin injection.

  The following equation holds for dielectric breakdown of an insulating barrier such as an insulating layer (see Non-Patent Document 4, for example).

（ただし、Ａ₀は定数、ΔＨ₀は活性化エネルギー、ａはeffective dipole moment(有効双極子モーメント)、Ｅは印加電圧、Ｋ_Ｂはボルツマン定数、Ｔは絶対温度、ＴＦは破壊時間である。）

(However, A ₀ is a constant, [Delta] H ₀ is the activation energy, a is Effective dipole Moment (effective dipole moment), E is the applied voltage, K _B is the Boltzmann constant, T is the absolute temperature, TF is the failure time. )

Nikkei Electronics 2001.1.22 (pages 164-171) Phys. Rev. B 54.9353 (1996) J. et al. Magn. Mat. 159. L1 (1996) J. et al. of Appl. Phys. , Vol. 84, no. 3, (1998) JP 2003-17782 A US Pat. No. 6,256,223

In general, in an element such as a semiconductor in which an insulating layer is used, since the insulating layer has a thickness of 3 nm or more and has a relatively high breakdown voltage, dielectric breakdown hardly occurs.
In contrast, in a memory element using spin injection, when a tunnel insulating layer is used as an intermediate layer, a large current of ³ to 10 MA / cm ² must flow through the tunnel insulating layer having a thickness of about 1 nm. . For this reason, when a steady current is passed through the memory element, the temperature of the insulating layer portion is increased by 200 ° C. to 300 ° C., and the insulating layer is easily broken.

  When formula (1) relating to dielectric breakdown described above is transformed into the relationship between breakdown voltage and temperature, formula (2) below is obtained. The applied voltage E corresponds to the withstand voltage.

From equation (2), it can be seen that the higher the temperature, the lower the breakdown voltage.
Therefore, it is considered that the breakdown voltage can be improved by preventing the temperature of the memory element from rising.

  In order to solve the above-described problem, the present invention provides a memory element having high reliability and a memory having this recording element by suppressing a temperature rise in an insulating layer portion.

The storage element of the present invention has a storage layer that retains information according to the magnetization state of a magnetic material, and a magnetization fixed layer is provided via an intermediate layer for the storage layer, the intermediate layer is made of an insulator, By injecting spin-polarized electrons in the stacking direction, the magnetization direction of the storage layer changes, information is recorded on the storage layer, and the ferromagnetic layer constituting the storage layer or magnetization fixed layer The thermal conductivity is 30 W / (K · m) or more.
The memory of the present invention includes a memory element having a memory layer that holds information according to the magnetization state of the magnetic material, and two types of wirings that intersect each other, and the memory element has the configuration of the memory element of the present invention. A memory element is arranged near the intersection of two types of wiring and between the two types of wiring, and a current in the stacking direction flows through the memory element through these two types of wiring.

According to the configuration of the above-described storage element of the present invention, the storage layer that retains information according to the magnetization state of the magnetic material is provided, and the magnetization fixed layer is provided to the storage layer via the intermediate layer. Is made of an insulator, and by injecting spin-polarized electrons in the stacking direction, the magnetization direction of the storage layer changes and information is recorded in the storage layer, so a current flows in the stacking direction. Information can be recorded by injecting spin-polarized electrons.
Further, since the thermal conductivity of the ferromagnetic layer constituting the storage layer or the magnetization fixed layer is 30 W / (K · m) or more, even if heat is generated in the intermediate layer made of an insulator, the storage layer or magnetization Heat can be easily dissipated through the ferromagnetic layer constituting the fixed layer. As a result, it is possible to prevent dielectric breakdown of the intermediate layer due to the temperature rise and to suppress the temperature rise of the memory element, so that information can be stably recorded and held.

According to the configuration of the memory of the present invention described above, the memory element includes a memory element having a memory layer that holds information according to the magnetization state of the magnetic material, and two types of wiring intersecting each other. The memory element is arranged near the intersection of two types of wiring and between the two types of wiring, and current in the stacking direction flows through the memory element through these two types of wiring. Information can be recorded by spin injection by passing a current in the stacking direction of the memory element through the wiring.
In addition, since it is possible to prevent dielectric breakdown of the intermediate layer of the memory element and suppress an increase in the temperature of the memory element, it is possible to stably record and hold information.

According to the above-described present invention, it is possible to stably record and hold information, and thus it is possible to configure a storage element with excellent characteristic balance.
Thereby, an operation error can be eliminated and a sufficient operation margin of the memory element can be obtained.
In addition, dielectric breakdown of the intermediate layer of the memory element can be prevented.
Therefore, a highly reliable memory that operates stably can be realized.

First, an outline of the present invention will be described prior to description of specific embodiments of the present invention.
In the present invention, information is recorded by reversing the magnetization direction of the storage layer of the storage element by the spin injection described above. The memory layer is made of a magnetic material such as a ferromagnetic layer, and holds information by the magnetization state (magnetization direction) of the magnetic material.

The basic operation of reversing the magnetization direction of the magnetic layer by spin injection is perpendicular to the film surface of a storage element composed of a giant magnetoresistive element (GMR element) or a magnetic tunnel junction element (MTJ element). A current exceeding a certain threshold is passed in the direction. At this time, the polarity (direction) of the current depends on the direction of magnetization to be reversed.
When a current having an absolute value smaller than this threshold is passed, magnetization reversal does not occur.

In the present invention, a magnetic tunnel junction (MTJ) element is formed using a tunnel insulating layer made of an insulator as a nonmagnetic intermediate layer between the storage layer and the magnetization fixed layer in consideration of the saturation current value of the selection transistor. Constitute.
By constructing a magnetic tunnel junction (MTJ) element using a tunnel insulating layer, a magnetoresistance change rate (MR ratio) is compared with a case where a giant magnetoresistive effect (GMR) element is constructed using a nonmagnetic conductive layer. This is because the read signal intensity can be increased.

However, in the case where a memory element composed of an MTJ element using a tunnel insulating layer is configured, if a voltage higher than the withstand voltage of the insulating film is applied when a current is passed, the memory element is destroyed.
At this time, the voltage at which the memory element is destroyed can be calculated phenomenologically by the above-described equations (1) and (2).

In the present invention, as expressed by the above formula (2), it is considered to actively lower the temperature of the memory element by utilizing the fact that the breakdown voltage (breakdown voltage) increases as the temperature decreases.
Generally, when a steady current is passed through a resistor, Joule heat is generated, so heat is generated in proportion to the square of the current passed through the memory element. In the case of MRAM, current is passed through a word line for writing and writing is performed using a magnetic field generated by the current. Therefore, dielectric breakdown is not a concern, but in the case of a spin injection memory, a relatively weak current is used. Since reading is performed at (10 μA to 50 μA) and writing is performed at a relatively strong current (300 μA to 1 mA), a temperature rise of 100 ° C. to 300 ° C. occurs during writing.

  The breakdown of the insulating film often occurs at the time of writing. This is because a higher voltage is applied at the time of writing than at the time of reading, and the amount of current increases.

In order for a memory element composed of an MTJ element to exist as a memory, the tunnel insulating layer must have a breakdown voltage sufficiently higher than a threshold voltage for reversing the magnetization direction.
As can be seen from the above equation (2), the higher the temperature, the lower the breakdown voltage. For this reason, it is required to suppress the increase in the temperature of the memory element as much as possible so that the withstand voltage does not fall below the threshold voltage.
For example, when the temperature reaches 100 ° C. when the thermal equilibrium state is reached, the 200 mV withstand voltage is lowered.

Therefore, in the present invention, the thermal conductivity of the ferromagnetic layer constituting the storage layer or the magnetization fixed layer sandwiching the tunnel insulating layer is set to 30 W / (K · m) or more, so that heat is released to the wiring and tunnel insulation is achieved. Avoid accumulation of heat in the layer.
Further preferably, in a memory including a memory element, a wiring material having a thermal conductivity of 30 W / (K · m) or more is used for a wiring for passing a current in a stacking direction for performing spin injection to the memory element. Make it easier for heat to escape from the wiring. More preferably, a material having a thermal conductivity of 30 W / (K · m) or more is used for the material of the wiring connected to the memory element and the material of the electrode of the memory element connected to the wiring.
If a material having a thermal conductivity of less than 30 W / (K · m) is used for the magnetic layer and the wiring material sandwiching the tunnel insulating layer, the temperature of the tunnel insulating layer increases with the thermal conductivity. .

Examples of the ferromagnetic layer material (ferromagnetic material) having a thermal conductivity of 30 W / (K · m) or more include Ni, CoFe, CoFeAl, and CoFeB (for example, composition of Co40Fe40B20; the numbers are atomic%). Can be mentioned.
Moreover, Cu, Al, Ta, W etc. are mentioned as a material of wiring and an electrode which has the heat conductivity of 30 W / (K * m) or more.
The thermal conductivity of various ferromagnetic materials is shown in Table 1, and the thermal conductivity of various wiring materials is shown in Table 2.

By the way, it is generally known that if the current flowing through the memory element is set to a short pulse current, the temperature rise of the memory element is reduced.
However, since there is no means for actually measuring the temperature rise due to the pulse current, how the temperature rise value varies depending on the pulse width was calculated using simulation (see FIG. 4).
From this result, it is understood that the element temperature is constant at a pulse width of 1 μs (microseconds) or more, but the element temperature does not reach a constant state at a short pulse width of less than 1 μs. It can be seen that at 1 ns (nanosecond), the temperature hardly increases.
That is, when using a pulse width of 10 ns or more and 100 ns rather than using a pulse current having a pulse width of 1 μs or more, the thermal conductivity of the ferromagnetic layer sandwiching the tunnel insulating layer is 30 W / ( K · m) or more works effectively.
As a result, in the memory using spin injection, since the heat generation of the element is suppressed as much as possible, the breakdown voltage of the element is increased, and the reliability of the memory itself is improved.

Furthermore, by using magnesium oxide (MgO) as the material of the tunnel insulating layer, the magnetoresistance change rate (MR ratio) is made larger than when aluminum oxide that has been generally used so far is used. can do.
In general, the spin injection efficiency depends on the MR ratio, and the higher the MR ratio, the higher the spin injection efficiency and the lower the magnetization reversal current density.
Therefore, by using magnesium oxide as the material of the tunnel insulating layer, which is an intermediate layer, and simultaneously using the memory layer having the above-described structure, the write threshold current due to spin injection can be reduced, and information can be written (recorded) with a small current. )It can be performed. In addition, the read signal intensity can be increased.
As a result, the MR ratio (TMR ratio) can be ensured, the write threshold current by spin injection can be reduced, and information can be written (recorded) with a small current. In addition, the read signal intensity can be increased.

  When the tunnel insulating layer is formed of a magnesium oxide (MgO) film, it is more desirable that the MgO film is crystallized and the crystal orientation is maintained in the 001 direction.

In the present invention, the intermediate layer between the storage layer and the magnetization fixed layer is made of magnesium oxide (tunnel insulating layer), for example, aluminum oxide, aluminum nitride, SiO ₂ , Bi ₂ O ₃ , MgF ₂ , CaF, SrTiO ₂ , AlLaO ₃ , Al—N—O, and other various insulators, dielectrics, and semiconductors can also be used.

In order to obtain excellent MR characteristics when magnesium oxide is used for the intermediate layer, it is generally required that the annealing temperature is set to a high temperature of 300 ° C. or higher, desirably 340 ° C. to 360 ° C. This is higher than the annealing temperature range (250 ° C. to 280 ° C.) in the case of aluminum oxide conventionally used for the intermediate layer.
This is to promote phase separation between the oxide and the magnetic layer to form a matching interface, and at the same time, it is necessary to form an appropriate internal structure or crystal structure of the barrier layer such as magnesium oxide. Conceivable.

  For this reason, excellent MR characteristics can be obtained by using a heat-resistant ferromagnetic material so that the ferromagnetic layer of the memory element is resistant to this high temperature annealing.

The sheet resistance value of the tunnel insulating layer needs to be controlled to about several tens of Ωμm ² or less from the viewpoint of obtaining a current density necessary for reversing the magnetization direction of the storage layer by spin injection.
In the tunnel insulating layer made of the MgO film, the film thickness of the MgO film needs to be set to 1.5 nm or less in order to make the sheet resistance value in the above range.

In addition, it is desirable to make the memory element small so that the magnetization direction of the memory layer can be easily reversed with a small current.
Accordingly, the area of the memory element is preferably 0.04 μm ² or less.

Note that it is also possible to directly stack a storage layer having the above-described configuration conditions and another ferromagnetic layer having a different material or composition range. It is also possible to stack a ferromagnetic layer and a soft magnetic layer, or to stack a plurality of ferromagnetic layers via a soft magnetic layer or a nonmagnetic layer. The effect of the present invention can be obtained even when stacked in this way.
In particular, when a configuration in which a plurality of ferromagnetic layers are laminated via a nonmagnetic layer, the strength of the interaction between the ferromagnetic layers can be adjusted. Even if it becomes below, the effect that it becomes possible to suppress so that a magnetization reversal current may not become large is acquired. The material of the nonmagnetic layer in this case is Ru, Os, Re, Ir, Au, Ag, Cu, Al, Bi, Si, B, C, Cr, Ta, Pd, Pt, Zr, Hf, W, Mo. , Nb or their alloys can be used.

The magnetization fixed layer preferably has unidirectional anisotropy, and the storage layer preferably has uniaxial anisotropy.
Moreover, it is preferable that each film thickness of a magnetization fixed layer and a memory layer is 1 nm-30 nm.

  The other configuration of the storage element can be the same as a conventionally known configuration of the storage element that records information by spin injection.

The magnetization fixed layer has a configuration in which the magnetization direction is fixed only by the ferromagnetic layer or by using the antiferromagnetic coupling between the antiferromagnetic layer and the ferromagnetic layer.
In addition, the magnetization fixed layer has a single-layered ferromagnetic layer structure or a laminated ferrimagnetic structure in which a plurality of ferromagnetic layers are stacked via a nonmagnetic layer.
When the magnetization pinned layer has a laminated ferrimagnetic structure, the sensitivity of the magnetization pinned layer to the external magnetic field can be reduced. Therefore, unnecessary magnetization fluctuations in the magnetization pinned layer due to the external magnetic field are suppressed, and the memory element operates stably. Can be made. Furthermore, the film thickness of each ferromagnetic layer can be adjusted, and the leakage magnetic field from the magnetization fixed layer can be suppressed.
Co, CoFe, CoFeB, or the like can be used as the material of the ferromagnetic layer constituting the magnetization fixed layer having the laminated ferrimagnetic structure. Moreover, Ru, Re, Ir, Os etc. can be used as a material of a nonmagnetic layer.

Examples of the material of the antiferromagnetic layer include magnetic materials such as FeMn alloy, PtMn alloy, PtCrMn alloy, NiMn alloy, IrMn alloy, NiO, and Fe ₂ O ₃ .
In addition, nonmagnetic elements such as Ag, Cu, Au, Al, Si, Bi, Ta, B, C, O, N, Pd, Pt, Zr, Hf, Ir, W, Mo, and Nb are included in these magnetic materials. Can be added to adjust the magnetic properties and other physical properties such as crystal structure, crystallinity and material stability.

  In addition, the film configuration of the storage element has no problem whether the storage layer is disposed above the magnetization fixed layer or the lower layer.

  As a method for reading information recorded in the memory layer of the memory element, a ferromagnetic layer that flows through the insulating layer is provided by providing a magnetic layer serving as a reference of information via a thin insulating film in the memory layer of the memory element. Reading may be performed by a tunnel current or may be performed by a magnetoresistive effect.

Next, embodiments of the present invention will be described.
As an embodiment of the present invention, a schematic configuration diagram (perspective view) of a memory is shown in FIG.
In this memory, a storage element capable of holding information in a magnetized state is arranged near the intersection of two types of address lines (for example, a word line and a bit line) orthogonal to each other.
That is, the drain region 8, the source region 7, and the gate electrode 1 that constitute a selection transistor for selecting each memory cell in a portion separated by the element isolation layer 2 of the semiconductor substrate 10 such as a silicon substrate, Each is formed. Of these, the gate electrode 1 also serves as one address wiring (for example, a word line) extending in the front-rear direction in the figure.
The drain region 8 is formed in common to the left and right selection transistors in the figure, and a wiring 9 is connected to the drain region 8.

The storage element 3 is disposed between the source region 7 and the other address wiring (for example, bit line) 6 disposed above and extending in the left-right direction in the drawing. The storage element 3 has a storage layer composed of a ferromagnetic layer whose magnetization direction is reversed by spin injection.
The storage element 3 is arranged near the intersection of the two types of address lines 1 and 6.
The storage element 3 is connected to the bit line 6 and the source region 7 through upper and lower contact layers 4, respectively.
As a result, a current in the vertical direction can be passed through the storage element 3 through the two types of address lines 1 and 6, and the magnetization direction of the storage layer can be reversed by spin injection.

A cross-sectional view of the memory element 3 of the memory according to the present embodiment is shown in FIG.
As shown in FIG. 2, the storage element 3 is provided with a fixed magnetization layer 31 in the lower layer with respect to the storage layer 17 in which the direction of the magnetization M1 is reversed by spin injection. The antiferromagnetic layer 12 is provided under the magnetization fixed layer 31, and the magnetization direction of the magnetization fixed layer 31 is fixed by the antiferromagnetic layer 12.
An insulating layer 16 serving as a tunnel barrier layer (tunnel insulating layer) is provided between the storage layer 17 and the magnetization fixed layer 31, and the storage layer 17 and the magnetization fixed layer 31 constitute an MTJ element.
A base layer 11 is formed below the antiferromagnetic layer 12, and a cap layer 18 is formed on the storage layer 17. The base layer 11 and the cap layer 18 also serve as a lower electrode and an upper electrode of the memory element 3.

The magnetization fixed layer 31 has a laminated ferrimagnetic structure.
Specifically, the magnetization fixed layer 31 has a configuration in which two ferromagnetic layers 13 and 15 are stacked via a nonmagnetic layer 14 and antiferromagnetically coupled.
Since each of the ferromagnetic layers 13 and 15 of the magnetization fixed layer 31 has a laminated ferrimagnetic structure, the magnetization M13 of the ferromagnetic layer 13 is directed to the right, and the magnetization M15 of the ferromagnetic layer 15 is directed to the left. It has become. Thereby, the magnetic fluxes leaking from the ferromagnetic layers 13 and 15 of the magnetization fixed layer 31 cancel each other.

The material of the ferromagnetic layers 13 and 15 of the magnetization fixed layer 31 is not particularly limited, and an alloy material composed of one or more of iron, nickel, and cobalt can be used. Furthermore, transition metal elements such as Nb, Zr, Gd, Ta, Ti, Mo, Mn, and Cu, and light elements such as Si, B, and C can also be included. Alternatively, the ferromagnetic layers 13 and 15 may be configured by directly stacking a plurality of films of different materials (not via a nonmagnetic layer) such as a CoFe / NiFe / CoFe stacked film.
As the material of the nonmagnetic layer 14 constituting the laminated ferrimagnetic pinned layer 31, ruthenium, copper, chromium, gold, silver or the like can be used.
Although the film thickness of the nonmagnetic layer 14 varies depending on the material, it is preferably used in the range of approximately 0.5 nm to 2.5 nm.

In the present embodiment, in particular, the storage layer 17 of the storage element 3 is configured to be a ferromagnetic layer having a thermal conductivity of 30 W / (K · m) or more.
As the material of such a ferromagnetic layer, for example, the aforementioned Ni, CoFe, CoFeAl, CoFeB (for example, composition of Co40Fe40B20; the number is atomic%), or the like can be used.

Further, in the present embodiment, at least one of the base layer 11 and the cap layer 18 that also serve as electrodes in the memory element 3 in FIG. 2 and the wiring such as the contact layer 4 and the bit line 6 in FIG. A material having a thermal conductivity of 30 W / (K · m) or more is used.
As materials for such electrodes and wiring, the above-described Cu, Al, Ta, W, etc. can be used.

Furthermore, in this embodiment, when the insulating layer 16 that is an intermediate layer is a magnesium oxide layer, the magnetoresistance change rate (MR ratio) can be increased.
By increasing the MR ratio in this way, the efficiency of spin injection can be improved, and the current density required for reversing the direction of the magnetization M1 of the storage layer 17 can be reduced.

  The memory element 3 of the present embodiment is manufactured by continuously forming the base layer 11 to the cap layer 18 in a vacuum apparatus, and then forming a pattern of the memory element 3 by processing such as etching. Can do.

  According to the above-described embodiment, the storage layer 17 of the storage element 3 is a ferromagnetic layer having a thermal conductivity of 30 W / (K · m) or higher, so that the thermal conductivity of the storage layer 17 is high, Since the heat generated in the tunnel insulating layer 16 can be easily dissipated through the storage layer 17, the temperature of the insulating layer 16 can be lowered. Thereby, it is possible to prevent the dielectric breakdown of the insulating layer 16 and to suppress the temperature rise of the memory element 3.

  Further, according to the present embodiment, at least one of the base layer 11 and the cap layer 18 that also serve as electrodes in the memory element 3 in FIG. 2 and the wiring such as the contact layer 4 and the bit line 6 in FIG. By using a material having a thermal conductivity of 30 W / (K · m) or higher, the electrodes 11 and 18 and the wirings 4 and 6 have high thermal conductivity, so that the heat released through the memory layer 17 is transferred to the electrodes 11 and 18. It is possible to escape easily (outside of the memory element 3) through the wirings 4 and 6. Thereby, it becomes possible to suppress the temperature rise of the memory element 3.

According to the present embodiment, the temperature rise of the storage element 3 can be suppressed, so that information can be stably recorded and held, and the storage element 3 having excellent characteristic balance can be obtained. Can be configured. Thereby, an operation error can be eliminated and a sufficient operation margin of the memory element 3 can be obtained.
Therefore, a highly reliable memory that operates stably can be realized.

Further, the memory having the memory element 3 shown in FIG. 2 and having the configuration shown in FIG. 1 has an advantage that a general semiconductor MOS formation process can be applied when the memory is manufactured. For example, it is possible to withstand annealing at 340 ° C. to 360 ° C. without deteriorating the magnetic characteristics of the memory layer 17.
Therefore, a memory including the memory element 3 of the present embodiment can be applied as a general-purpose memory.

(Example)
Here, in the configuration of the memory element of the present invention, the temperature dependence of the temperature and breakdown voltage of the memory element was examined by selecting the material and film thickness of each layer, such as the ferromagnetic material that specifically constitutes the memory layer. .
As shown in FIG. 1 and FIG. 7 in an actual memory, there are switching semiconductor circuits and the like in addition to the memory element. Here, a study was performed using a wafer on which only the memory element was formed.

A thermal oxide film having a thickness of 300 nm was formed on a silicon substrate having a thickness of 0.725 mm, and the memory element 3 having the configuration shown in FIG. 2 was formed thereon.
Specifically, in the memory element 3 having the configuration shown in FIG. 2, the material and thickness of each layer are as follows: the underlayer 11 is a Ta film with a thickness of 3 nm, the antiferromagnetic layer 12 is a PtMn film with a thickness of 20 nm, and the magnetization The ferromagnetic layer 13 constituting the fixed layer 31 is a CoFe film having a thickness of 2 nm, the ferromagnetic layer 15 is a CoFeB film having a thickness of 2.5 nm, and the nonmagnetic layer 14 constituting the magnetization fixed layer 31 having a laminated ferrimagnetic structure is formed. An Ru film of 0.8 nm, an insulating layer (barrier layer) 16 serving as a tunnel insulating layer is selected as a magnesium oxide film, a storage layer 17 is selected as a ferromagnetic layer, and a cap layer 18 is selected as a Ta film having a thickness of 5 nm. A Cu film (not shown) having a thickness of 100 nm (to be a word line described later) was provided between the antiferromagnetic layer 12 and the antiferromagnetic layer 12 to form each layer.
In the above film configuration, the composition of the PtMn film was Pt50Mn50 (atomic%), and the composition of the CoFe film was Co90Fe10 (atomic%). For the ferromagnetic layer of the memory layer 17, a ferromagnetic material described later was used.

Each layer other than the insulating layer 16 made of a magnesium oxide film was formed using a DC magnetron sputtering method.
The insulating layer 16 made of a magnesium oxide (MgO) film was formed using an RF magnetron sputtering method.
Further, after each layer of the memory element 3 was formed, a heat treatment was performed at 10 kOe · 360 ° C. for 2 hours in a magnetic field heat treatment furnace, and an orderly heat treatment was performed on the PtMn film of the antiferromagnetic layer 12.

Next, after masking the word line portion by photolithography, the word line (lower electrode) was formed by performing selective etching with Ar plasma on the laminated film other than the word line. At this time, except for the word line portion, the substrate was etched to a depth of 5 nm.
Thereafter, a mask of the pattern of the memory element 3 was formed by an electron beam drawing apparatus, and selective etching was performed on the laminated film to form the memory element 3. Except for the memory element 3 portion, the etching was performed up to the Cu layer of the word line.

Note that in order to generate a spin torque necessary for magnetization reversal in the memory element, it is necessary to pass a sufficient current through the memory element, and thus it is necessary to suppress the resistance value of the tunnel insulating layer.
Therefore, the pattern of the memory element 3 is an ellipse having a minor axis of 0.09 μm and a major axis of 0.18 μm, and the area resistance value (Ωμm ² ) of the memory element 3 is 20 Ωμm ² .

Next, the portions other than the memory element 3 portion were insulated by sputtering of Al ₂ O ₃ having a thickness of about 100 nm.
Thereafter, a bit line to be an upper electrode and a measurement pad were formed using photolithography.
In this way, a sample of the memory element 3 was produced.

  As described above, the characteristics of each sample of the produced memory element 3 were evaluated as follows.

<Measurement of element temperature>
For the purpose of examining the actual element temperature, the temperature change of the pin magnetic field of the magnetization fixed layer 31 was measured.
In the measurement of the pin magnetic field of the magnetization fixed layer 31, the substrate temperature is 25 ° C., 40 ° C., 60 ° C., 80 ° C., 100 ° C., 120 ° C. while the temperature is controlled by heating the measurement substrate on which the wafer is mounted. The pin magnetic field at each substrate temperature was measured while changing the temperature. The pin magnetic field has a property of weakening linearly as the temperature is increased. By using this property, the element temperature at a certain pin magnetic field can be estimated. The applied voltage was increased from 100 mV to 1 V in units of 10 mV, the pin magnetic field at that time was measured, and the actual temperature of the memory element 3 at a certain applied voltage was calculated. Further, the amount of current flowing through the memory element 3 was calculated from the applied voltage and the resistance value.

Then, by measuring the thickness of the magnesium oxide film of the insulating layer 16 of the memory element 3, the two types of memory elements 3 (element A and element B) having different resistance values are measured. went. The thickness of the magnesium oxide film of the insulating layer 16 is 0.75 nm for the element A and 0.8 nm for the element B.
As a measurement result, FIG. 3 shows the relationship between the current flowing through the memory element 3 and the temperature rise when the current of the memory element 3 is not flowing.

  FIG. 3 shows that although the degree of temperature rise varies depending on the resistance value of the memory element 3, the temperature rise increases as the amount of current flowing through the memory element 3 increases.

<Measurement of pressure resistance>
In order to evaluate the breakdown characteristics of the memory element, the breakdown voltage (breakdown voltage) may be measured.
This breakdown voltage measurement can be performed as follows.
A pulse voltage of 10 μs to 100 ms was applied to the memory element 3 to increase the voltage value in steps of 100 mV to 10 mV, and measurement (step stress method) was performed until the memory element 3 was destroyed. The voltage at the time of destruction was taken as the breakdown voltage of the memory element 3.
When changing the substrate temperature, the measurement substrate on which the wafer is placed is heated with a heater and the substrate temperature is controlled at 25 ° C., 40 ° C., 60 ° C., 80 ° C., 100 as in the case of measuring the pin magnetic field. The pressure resistance at that time was measured using the step stress method while changing the temperature to 120 ° C.

<Temperature simulation>
The temperature of the memory element 3 was calculated using ANSYS which is a commercially available temperature simulator.
A cross-sectional view of the model used in the calculation in the stacking direction is shown in FIG.
The upper electrode 19 is 220 nm thick, the cap layer 18 is 5 nm thick, the ferromagnetic layer (memory layer) 17 is 2 nm thick, the insulating layer 16 is a 1 nm thick MgO film, and the ferromagnetic layer 15 is 3 nm thick. The magnetic layer 14 is a 0.8 nm thick Ru film, the magnetic layer 13 is a 2.0 nm thick CoFe (Co 90% Fe 10%) film, the antiferromagnetic layer 12 is a 30 nm thick PtMn film, and the lower electrode 11 is a film. The thickness was set to 30 nm, the embedded insulating material 20 was set to SiO ₂ , and the thickness of the substrate 21 was set to 525 μm. When viewed from the xy direction, the shape of the element portion is 50 nm × 100 nm, and the electrode portion is a rectangle of 10 μm × 2 μm.
As another calculation condition, the temperature of the substrate 21 was fixed at 25 ° C., and current was set to flow from the lower electrode 11 and flow out to the upper electrode 19. The current was calculated using a pulse width of 1 ns (nanosecond; the same applies hereinafter), 10 ns, 100 ns, 1 μs (microsecond; the same applies hereinafter), 10 μs, and 100 μs, and a steady current. The shape of the pulse current was a trapezoid, and it was assumed that the pulse current increased to the target current with a pulse width of 0.2 (seconds) and decreased to 0 with a pulse width of 0.2 (seconds).

First, the thermal conductivity of the ferromagnetic layer of the memory layer 17 is fixed to the value of the thermal conductivity of CoFe, and the pulse width is changed to 1 ns, 10 ns, 100 ns, 1 μs, 10 μs, and 100 μs, and the current of each pulse width is changed. The average temperature in the insulating layer (MgO) 16 when flowing was calculated. This calculation was performed for three types of conditions: a substrate temperature of 25 ° C. and a current amount of 500 μA, a substrate temperature of 25 ° C. and a current amount of 300 μA, and a substrate temperature of 100 ° C. and a current amount of 300 μA.
As a calculation result, the relationship between the pulse width and the temperature rise of the insulating layer 16 under each condition is shown in FIG. The vertical axis in FIG. 4 indicates the temperature of the insulating layer 16.

From FIG. 4, it can be seen that, regardless of the substrate temperature and the amount of current, when the pulse width is 1 μs or more, the temperature does not change (after the temperature rises) and the thermal equilibrium state is reached even if the pulse width is increased. .
On the other hand, in the 1 ns region with a short pulse width, even when a current of 500 μA is passed, the difference from the substrate temperature is small and there is almost no temperature change.
It can be seen that in the region with a pulse width of 10 ns to 1 μs, the temperature rise increases as the pulse width is increased. Therefore, as described above, the ferromagnetic layer 17 that sandwiches the tunnel insulating layer when a write operation is performed using a pulse width of 10 ns to 100 ns rather than using a pulse current having a large pulse width of 1 μs or more. , 15 is effectively set to 30 W / (K · m) or more.

Further, in order to obtain the thermal conductivity of the ferromagnetic layer so that the temperature of the element does not increase so much and the withstand voltage does not decrease, the pulse width of the applied current is set to 1 μs, and the ferromagnetic layers 17 and 15 sandwiching the insulating layer 16 are interposed. The thermal conductivity of each of the ferromagnetic layers 17 and 15 was changed with the same thermal conductivity, and the temperature rise of the insulating layer 16 was obtained by calculation. The thermal conductivities [W / (K · m)] of the ferromagnetic layers 17 and 15 are 0.03, 0.3, 3.0, 30, and 100, and the current amount is 300 μA and the current amount is 500 μA. Each calculation was performed.
As a calculation result, the relationship between the thermal conductivity of the ferromagnetic layers 17 and 15 and the temperature rise of the insulating layer 16 is shown in FIG.

From FIG. 5, it can be seen that the temperature begins to rise when the thermal conductivity of the ferromagnetic layers 17 and 15 is set to 30 W / (K · m) or less at any current amount.
That is, if the thermal conductivity of the ferromagnetic layers 17 and 15 is set to 30 W / (K · m) or more, the temperature hardly increases, the breakdown voltage of the element increases, and the reliability as a memory is improved. become.

  In the above-described embodiment, the storage layer 17 is configured to be a ferromagnetic layer having a thermal conductivity of 30 W / (K · m) or more, but instead of the storage layer, a ferromagnetic layer ( For example, in the memory element 3 of FIG. 2, the ferromagnetic layers 13 and 15) may be a ferromagnetic layer having a thermal conductivity of 30 W / (K · m) or more. Further, both the storage layer and the magnetization fixed layer may be a ferromagnetic layer having a thermal conductivity of 30 W / (K · m) or more.

  In addition, with regard to the electrodes and wiring, if all are made of a material having a thermal conductivity of 30 W / (K · m) or more, it will not exceed that, but at least one of the materials has a thermal conductivity of 30 W / If it is (K · m) or more, an effect of easily releasing heat to the outside of the memory element can be obtained.

  Furthermore, the present invention is not limited to the film configuration of the memory element 3 shown in the above-described embodiments, and various film configurations can be employed.

  In each of the embodiments described above, the magnetization fixed layer 31 has a laminated ferrimagnetic structure including the two ferromagnetic layers 13 and 15 and the nonmagnetic layer 14. For example, the magnetization fixed layer is a single-layer ferromagnetic layer. You may comprise by.

  The present invention is not limited to the above-described embodiment, and various other configurations can be taken without departing from the gist of the present invention.

1 is a schematic configuration diagram (perspective view) of a memory according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of the memory element in FIG. 1. It is a figure which shows the temperature rise of a memory element when an electric current is applied. It is a figure which shows the relationship between the pulse width of a pulse current, and the temperature of an insulating layer. It is a figure which shows the relationship between the heat conductivity of the ferromagnetic layer which pinches | interposes an insulating layer, and the temperature rise of an insulating layer. It is sectional drawing of the model used for the temperature calculation by ANSYS. It is a schematic block diagram (perspective view) of a memory using magnetization reversal by spin injection. It is sectional drawing of the memory of FIG. It is the perspective view which showed the structure of the conventional MRAM typically.

Explanation of symbols

3 Memory element, 11 Underlayer, 12 Antiferromagnetic layer, 13, 15 Ferromagnetic layer, 14 Nonmagnetic layer, 16 Tunnel insulating layer, 17 Memory layer, 18 Cap layer, 31 Magnetization fixed layer

Claims (5)

It has a storage layer that holds information according to the magnetization state of the magnetic material,
A magnetization fixed layer is provided via an intermediate layer for the storage layer,
The intermediate layer is made of an insulator;
By injecting spin-polarized electrons in the stacking direction, the magnetization direction of the storage layer changes, and information is recorded on the storage layer.
The memory element, wherein the ferromagnetic layer constituting the memory layer or the magnetization fixed layer has a thermal conductivity of 30 W / (K · m) or more. A storage element having a storage layer for retaining information by the magnetization state of the magnetic material;
Two types of wiring crossing each other,
The storage element is provided with a magnetization fixed layer via an intermediate layer with respect to the storage layer, the intermediate layer is made of an insulator, and the storage layer is injected with spin-polarized electrons. The direction of magnetization of the magnetic layer changes, information is recorded on the storage layer, and the thermal conductivity of the ferromagnetic layer constituting the storage layer or the fixed magnetization layer is 30 W / (K · m) or more. Yes,
The storage element is disposed near the intersection of the two types of wiring and between the two types of wiring,
A memory in which a current in the stacking direction flows in the memory element through the two types of wirings.   The memory according to claim 2, wherein the thermal conductivity of the material of the two types of wiring is 30 W / (K · m) or more.   The material of the wiring connected to the memory element or the material of the electrode of the memory element connected to the wiring has a thermal conductivity of 30 W / (K · m) or more. 2. The memory according to 2.   The memory according to claim 2, wherein a pulse width of the current in the stacking direction flowing through the memory element is 10 nanoseconds or more and 100 nanoseconds or less.

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