JP2008003201A - Method of manufacturing semiconductor device and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device capable of evading mulfunction, and to provide the semiconductor device. <P>SOLUTION: A resist film is exposed by using a light shielding mask which covers a first resist region corresponding to a channel region, a source side low concentration region and a drain side low concentration region of a semiconductor layer and a second resist region swelled out of the first resist region to the direction where a gate electrode is disposed, in the resist film formed on a semiconductor film and, therefore, the first resist region is hardly exposed even when exposure light enters the region covered with the light shielding mask by diffraction and the like. Since the first resist region is hardly exposed, it is made possible to prevent the resist film in the first resist region from being removed in a resist film removal process and, further, it is made possible to prevent impurity ions from being injected into the channel region in a first impurity injection process. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

  Electro-optical devices such as liquid crystal devices, organic electroluminescence (EL) devices, and plasma displays have a structure in which a large number of dot regions are arranged in a matrix, and TFT (Thin film) is used as a switching element for driving the dot regions. Many transistors have an active matrix structure provided with a transistor.

  In general, a TFT is provided with an insulating film on a semiconductor layer, and the semiconductor layer and the gate electrode are opposed to each other through the insulating film. The semiconductor layer of the TFT is generally formed of amorphous silicon or polycrystalline silicon. In particular, a polycrystalline silicon TFT manufactured only by a low-temperature process is widely used in electro-optical devices such as the above-described liquid crystal devices and organic EL devices because electrons or holes have a large electric field mobility.

As the TFT structure, for example, an LDD (Lightly Doped Drain) structure and a GOLD (Gate-drain Overlapped LDD) structure are widely known.
In the LDD structure, a region of the semiconductor layer that overlaps the gate electrode in plan view (a region immediately below) is a channel region, and a region outside the channel region is a source-side low-concentration region in which impurities are implanted at a low concentration, and The drain side is a low concentration region. Out of the semiconductor layer, regions outside the source-side low concentration region and the drain-side low concentration region are a source-side high concentration region and a drain-side high concentration region into which high-concentration impurities are implanted. With this configuration, the off-current value can be suppressed.

  The GOLD structure is similar to the LDD structure in that the semiconductor layer has a channel region, a low concentration / high concentration source region and a drain region, but the channel region is narrower than the LDD structure. The source-side low concentration region and the drain-side low concentration region are provided so as to overlap a part of the region immediately below the gate electrode. By overlapping the source-side lightly doped region and the drain-side lightly doped region with the region immediately below the end of the gate electrode, the hot carrier phenomenon can be suppressed.

As a method for forming a TFT having an LDD structure and a TFT having a GOLD structure, for example, a method described in Patent Document 1 is known. Specifically, after forming a thin film with silicon, a resist film is formed on the silicon thin film. When forming the resist film, halftone exposure is performed using a photomask on which a diffraction grating is formed, thereby forming regions having different resist film thicknesses on the silicon thin film. Of the resist film, a thick resist film is formed in a portion on the channel region of the semiconductor layer, and a thin resist film is formed in a portion on the source side high concentration region and the drain side high concentration region. When impurity ions are irradiated from above the resist film after forming the resist film, the impurity ions are blocked in the thick region of the resist film (on the channel region) due to the thickness of the resist film and do not reach the silicon thin film. Impurity ions permeate in the thin region of the resist film, reach the silicon thin film, and are implanted. Thus, a channel region and a high concentration source / drain region are formed. Thereafter, the silicon thin film is etched to form a gate insulating layer and a gate electrode, and impurities are again implanted into the semiconductor layer using the gate electrode as a mask to form a structure having regions with different impurity concentrations.
JP 2002-151523 A

However, in the above method, exposure light may wrap around the portion covered with the photomask during exposure, and a part of the resist film on the semiconductor layer, particularly the resist on the channel region of the semiconductor layer, may be slightly exposed. . Since the exposed portion of the resist is removed, a part of the resist on the channel region is removed and thinned. When impurities are implanted from above such a resist film, the impurities are implanted into a part of the channel region of the semiconductor layer. In this case, current leakage occurs in the channel region, which causes a malfunction.
In view of the circumstances as described above, an object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device capable of avoiding malfunction.

  In order to achieve the above object, a semiconductor device manufacturing method according to the present invention includes a semiconductor layer having a channel region, a source-side low concentration region, a source-side high concentration region, a drain-side low concentration region, and a drain-side high concentration region, A method of manufacturing a semiconductor device comprising: an insulating layer provided on the semiconductor layer; and a gate electrode provided in a predetermined direction so as to face the semiconductor layer with the insulating layer interposed therebetween, A semiconductor film forming step of forming a semiconductor film on the semiconductor film; a resist film forming step of forming a resist film on the semiconductor film; and the channel region, the source side low concentration region, and the drain side low concentration region of the resist film. A first resist region corresponding to the second resist region, a second resist region protruding from the first resist region in the predetermined direction where the gate electrode is provided, and the source-side high concentration And the light transmission of the portion covering the third resist region rather than the light transmittance of the portion covering the first resist region and the second resist region. A first exposure step of exposing the resist film using a photomask having a high rate; a resist film removal step of removing an exposed portion of the resist film; and the resist film removal step, A first impurity implantation step for implanting a first impurity into the semiconductor film from above the resist film; and a semiconductor layer for forming a semiconductor layer by etching the semiconductor film using the resist film as a mask after the first impurity implantation step After the forming step, the semiconductor layer forming step, the resist film peeling step for peeling the resist film from the semiconductor layer, and the resist film peeling step An insulating layer forming step of forming the insulating layer on the semiconductor layer; and a gate electrode forming step of forming the gate electrode at a position corresponding to the channel region on the insulating layer after the insulating layer forming step; And a second impurity implantation step of implanting a second impurity into the semiconductor layer from above the gate electrode.

  According to the present invention, of the resist film formed on the semiconductor film, the first resist region corresponding to the channel region of the semiconductor layer, the source-side low concentration region, and the drain-side low concentration region, and the first resist region to the gate electrode Since the resist film is exposed using a photomask that covers the second resist region that protrudes in the direction in which the first resist is provided, the first resist can be used even when the exposure light reaches the region covered by the photomask. The area is hardly exposed. Since the first resist region is hardly exposed, the resist film in the first resist region can be prevented from being removed in the resist film removing step, and the impurity in the channel region of the semiconductor layer can be prevented in the first impurity implantation step. Can be prevented from being injected. Thus, current leakage can be prevented from occurring in the channel region, and malfunction can be avoided.

Preferably, the method further includes a second exposure step of exposing at least a part of the second resist region in the resist film after the first exposure step and before the resist film removing step.
According to the present invention, after the first exposure step and before the resist film removal step, the method further includes a second exposure step of exposing at least a part of the second resist region of the resist film. Then, a part of the exposed second resist region is removed. Therefore, in the semiconductor layer forming step, the semiconductor layer is formed using the resist film in a state where a part of the second resist region is removed as a mask. For example, a photomask that exposes only a part of the second resist region is formed in advance, and it is only necessary to replace the photomask after the first exposure step and irradiate the resist film with exposure light again. The semiconductor layer can be formed compactly without going through complicated steps.

In the second exposure step, it is preferable to expose at least a portion of the resist film that is in contact with the second resist region and a portion of the first resist region that is in contact with the second resist region.
According to the present invention, in the second exposure step, at least the portion of the resist film that is in contact with the second resist region and the second resist region in the first resist region is exposed. The second resist region and the portion of the first resist region that are in contact with the second resist region are removed. For this reason, in the semiconductor layer forming step, the semiconductor layer is formed using the resist film in a state where the second resist region and the portion of the first resist region in contact with the second resist region are removed as a mask. . Thereby, the shape of the semiconductor layer can be adjusted without providing a separate process.

  A semiconductor device according to the present invention includes a semiconductor layer having a channel region, a source-side low concentration region, a source-side high concentration region, a drain-side low concentration region, and a drain-side high concentration region, and an insulating layer provided on the semiconductor layer And a gate electrode provided in a predetermined direction so as to face the semiconductor layer through the insulating layer, wherein at least a part of the channel region of the semiconductor layer is It protrudes in the direction in which the gate electrode is provided.

  According to the present invention, since at least a part of the channel region of the semiconductor layer protrudes in the direction in which the gate electrode is provided, the dimension of the outer edge of the channel region can be increased. In the process of forming a semiconductor device, impurities are easily implanted into the outer edge of the channel region, and when the impurities are implanted, current leaks through the outer edge of the channel region. In the present invention, since the electrical resistance value of the outer edge of the channel region can be increased by increasing the outer edge size of the channel region, even if impurities are implanted into the outer edge of the channel region, current leakage Is less likely to occur. As a result, a semiconductor device that is less prone to malfunction can be obtained.

[First Embodiment]
A first embodiment of the present invention will be described with reference to the drawings. In the following drawings, the scale is appropriately changed to make each member a recognizable size.
(LCD panel)
FIG. 1 is a plan view showing the overall configuration of the liquid crystal panel according to the present embodiment.
As shown in the figure, the liquid crystal panel 1 has a TFT array substrate 2 and a counter substrate 3 made of a transparent material such as glass, for example, and is bonded by a sealing material 4 provided therebetween. It is configured. A liquid crystal layer 5 is sealed in a region surrounded by the sealing material 4.

  A peripheral parting 6 made of a light shielding material is formed inside the sealing material 4. A region surrounded by the peripheral parting 6 is a light modulation region 12 in which light from the outside is modulated. In the light modulation region 12, dot regions 13 that can transmit light are arranged in a matrix. A region between the dot regions 13 is a light shielding region 14 where light is shielded.

  A data line driving circuit 7 and an external circuit mounting terminal 8 are formed along one side of the TFT array substrate 2 in a region outside the sealing material 4, and the scanning line driving circuit is formed along two sides adjacent to the one side. 9 is formed. On the remaining side of the TFT array substrate 2, a plurality of wirings 10 are provided for connecting between the scanning line driving circuits 9 provided on both sides of the image display area. In addition, an inter-substrate conductive material 11 for providing electrical continuity between the TFT array substrate 2 and the counter substrate 3 is disposed at a corner portion of the counter substrate 3.

FIG. 2A and FIG. 2B are plan views showing an enlarged dot region 13 of the liquid crystal panel 1. FIG. 3 is a diagram showing a configuration along the section AA in FIG.
As shown in FIG. 2A, a rectangular pixel electrode 31 is provided in the dot region 13 of the liquid crystal panel 1, and the data line 26, the scanning line 24, and the scanning line 14 are arranged along the dot region 13 in the light shielding region 14. A capacitance line 34 is provided.

  As shown in FIG. 3, a base protective film 21 made of a silicon oxide film or the like is formed on the entire inner surface (facing surface facing the counter substrate 3) 2 a of the TFT array substrate 2. A semiconductor layer 22 made of a semiconductor such as silicon is provided in the light shielding region 14 on the base protective film 21.

  The semiconductor layer 22 has a channel region 22a at the center in the left-right direction in the drawing. The region adjacent to the left of the channel region 22a in the figure is the source side low concentration region 22b, and the region adjacent to the left of the source side low concentration region 22b is the source side high concentration region 22c. The region on the right side of the channel region 22a in the drawing is the drain side low concentration region 22d, and the region on the right side of the drain side low concentration region 22d in the drawing is the drain side high concentration region 22e.

  FIG. 2B is a diagram illustrating a planar configuration of the semiconductor layer 22. The semiconductor layer 22 has a horizontal direction in the drawing as a longitudinal direction and a vertical direction in the drawing as a short direction. Of the semiconductor layer 22, the channel region 22 a, the source-side low concentration region 22 b, and the drain-side low concentration region 22 d have a portion (protrusion 22 p) that protrudes in the extending direction (vertical direction in the drawing) of the gate electrode 24 a. Yes. Further, as shown in FIGS. 2A and 3, the semiconductor layer 22 has an extending portion (reference numeral 33) extending from the drain side high concentration region 22e to the pixel electrode 31 side (see FIG. 2). 2 (b) omitted). The semiconductor layer 22 and the extended portion 33 are electrically connected.

  As shown in FIG. 3, the gate insulating layer 23 is provided on the semiconductor layer 22 and the extended portion 33. The gate insulating layer 23 is made of, for example, a silicon oxide film, and is provided so as to cover the entire surface of the base protective film 21 including the semiconductor layer 22 and the extending portion 33. A gate electrode 24 a is provided in a region on the gate insulating layer 23 that overlaps the channel region 22 a of the semiconductor layer 22 in plan view. As shown in FIG. 2A, the gate electrode 24a has a configuration in which a part of the above-described scanning line 24 protrudes and extends toward the dot region 13, and is wider than the scanning line 24 (extending direction). ) Is wide. The gate electrode 24a, the semiconductor layer 22, and the gate insulating layer 23 constitute a TFT 40. In the present embodiment, the TFT 40 has an LDD structure in which the semiconductor layer 22 has the above-described regions 22a to 22e, and the gate electrode 24a overlaps the channel region 22a of the semiconductor layer 22 in plan view.

  As shown in FIGS. 2A and 3, a capacitor line 34 is provided in a region of the gate insulating layer 23 that overlaps with the extended portion 33 in plan view, and the extended portion 33, the capacitive line 34, Are arranged opposite to each other with the gate insulating layer 23 interposed therebetween to constitute a storage capacitor 35. Hereinafter, the extended portion 33 is referred to as a lower electrode 33 of the storage capacitor 35, and the capacitor line 34 is referred to as an upper electrode 34 of the storage capacitor 35. In the storage capacitor 35, electric charges can be held between the lower electrode 33 and the upper electrode 34.

  As shown in FIG. 3, the first insulating layer 25 is provided on the gate electrode 24 a and the upper electrode 34. The first insulating layer 25 is made of, for example, a silicon oxide film, and is formed so as to cover the entire surface of the gate insulating layer 23 including the gate electrode 24 a and the upper electrode 34. A data line 26 and a source line 27 are provided on the first insulating layer 25.

  The data line 26 is connected to the source-side high concentration region 22 c of the semiconductor layer 22 through a contact hole 28 that penetrates the gate insulating layer 23 and the first insulating layer 25. One end (left side in the figure) of the source line 27 is connected to the drain side high concentration region 22 e of the semiconductor layer 22 through a contact hole 29 that penetrates the gate insulating layer 23 and the first insulating layer 25. A second insulating layer 30 is provided on the data line 26 and the source line 27. The second insulating layer 30 is made of, for example, a silicon oxide film, and is formed so as to cover the entire surface of the first insulating layer 25 including the data line 26 and the source line 27.

  A pixel electrode 31 is provided on the second insulating layer 30. The pixel electrode 31 is made of a transparent conductive material such as ITO, and is connected to the other end (right side in the figure) of the source line 27 through a contact hole 32. An alignment film 36 is provided on the pixel electrode 31. The alignment film 36 is formed so as to cover the entire surface of the second insulating layer 30 including the pixel electrode 31.

  A light shielding portion 37, a common electrode 38, and an alignment film 39 are provided on the inner surface (facing surface facing the TFT array substrate 2) 3 a of the counter substrate 3. The light shielding portion 37 is provided in the light shielding region 14 so as to cover the semiconductor layer 22 and the like described above. The common electrode 38 is made of, for example, a transparent conductive member such as ITO, and is provided on almost the entire inner surface 3 a of the counter substrate 3 including the light shielding portion 37. The alignment film 39 is provided on the entire surface of the common electrode 38.

  A liquid crystal layer 5 for light modulation is sealed between the TFT array substrate 2 and the counter substrate 3. The liquid crystal layer 5 is made of, for example, liquid crystal molecules such as a fluorine-based liquid crystal compound or a non-fluorine-based liquid crystal compound, and is in contact with both the alignment film 36 on the TFT array substrate 2 side and the alignment film 39 on the counter substrate 3 side. Between the two substrates. The alignment of the liquid crystal molecules is regulated by the alignment film 36 and the alignment film 39 so as to be oriented in a predetermined direction when a non-selection voltage is applied.

(TFT manufacturing method)
Next, a manufacturing method of the TFT 40 having the LDD structure in the liquid crystal panel 1 configured as described above will be described with reference to FIGS. 4-17 is a figure which shows the manufacturing method of TFT in order of a process, FIGS. 4-6 is a schematic sectional drawing, FIGS. 7-17 is a top view.

First, a translucent substrate (TFT array substrate 2) such as a glass substrate cleaned by ultrasonic cleaning or the like is prepared. The surface temperature of the TFT array substrate 2 is set to about 150 to 450 ° C., and as shown in FIG. 4, a base protective film 21 made of a silicon oxide film or the like is formed on the entire surface of the TFT array substrate 2 to a thickness of 100 to 500 nm by plasma CVD or the like. A film is formed to a thickness. As the source gas used in this step, a mixed gas of monosilane and dinitrogen monoxide, TEOS (tetraethoxysilane, Si (OC ₂ H ₅ ) ₄ ) and oxygen, disilane and ammonia, and the like are preferable.

  When the base protective film 21 is formed, as shown in FIG. 5, an amorphous semiconductor film 50 made of amorphous silicon is formed on the entire surface of the base protective film 21 to a thickness of 30 to 100 nm by plasma CVD or the like. To do. The amorphous semiconductor film 50 thus formed is subjected to laser annealing to polycrystallize the amorphous semiconductor film 50 into a semiconductor film 50 made of polycrystalline silicon (semiconductor film forming step). As the source gas used in this step, disilane or monosilane is suitable. After the semiconductor film 50 is formed, a resist film 51 is formed on the entire surface of the semiconductor film 50 as shown in FIG. 6 (resist film forming step).

  FIG. 7 is a view showing a portion where the semiconductor layer 22 is formed in the TFT array substrate 2 on which the resist film 51 is formed. Of the region where the semiconductor layer 22 is formed, a region overlapping the channel region 22a, the source-side low concentration region 22b, and the drain-side low concentration region 22d in plan view is defined as a first resist region 61. A region that has substantially the same width as the first resist region 61 (the length in the horizontal direction in FIG. 7) and protrudes from the first resist region 61 in the vertical direction in FIG. A region overlapping the source side high concentration region 22c and the drain side high concentration region 22e of the semiconductor layer 22 in plan view is defined as a third resist region 63.

  Next, as shown in FIG. 8, the resist film 51 is exposed while being covered with a photomask (halftone mask) (first exposure step). The first resist region 61 and the second resist region 62 are masked by the light shielding region 52 so that the exposure light is completely shielded, and the third resist region 63 is covered by the halftone region 53. A mask is formed.

  The halftone region 53 has three types of reticle regions: a reticle region that blocks exposure light, a reticle region that completely transmits exposure light, and a reticle region that partially transmits exposure light. Of these, a diffraction grating pattern (such as a slit) is provided in the reticle region that partially transmits the exposure light, so that the light intensity of the transmitted light can be controlled. As described above, the halftone region 53 has three kinds of reticle regions, so that the light transmittance is higher than that of the light shielding region 52.

  After the alignment, when the exposure light is irradiated to the resist film 51 covered with the light shielding region 52 and the halftone region 53, the light shielding region 52 and the halftone region 53 of the resist film 51 are exposed as shown in FIG. The region 64 that is not covered by any part is irradiated with the entire exposure light as it is, and an exposure reaction occurs up to the surface of the semiconductor film. The third resist region 63 covered with the halftone region 53 is irradiated with a part of the exposure light, and an exposure reaction occurs from the surface of the resist film 51 to a predetermined thickness portion. As for the first resist region 61 and the second resist region 62 covered with the light shielding region 52, most of the exposure light is shielded by the light shielding region 52, and very little exposure light diffracted by the light shielding region 52 is exposed to the first resist region. 61 and only the peripheral portion 65 of the second resist region 62 are irradiated. In the first resist region 61 and the second resist region 62, only an exposure reaction occurs on the surface layer of the peripheral portion 65.

  Next, as shown in FIG. 10, the photomask is replaced with a light shielding mask 54, and the resist film 51 is exposed again (second exposure step). The light shielding mask 54 is a photomask that completely blocks exposure light. The light shielding mask 54 has a size and shape that can cover the first resist region 61 and the third resist region 63 in the resist film 51. In FIG. 10, it is formed in, for example, a rectangle. As shown in FIG. 10, the light shielding mask 54 is disposed so that the first resist region 61 and the third resist region 63 are completely covered by the light shielding mask 54 and the second resist region 62 is exposed. When the resist film 51 is irradiated with exposure light in a state covered with the light-shielding mask 54, an exposure reaction occurs in the second resist region 62 as shown in FIG.

  Next, the portion of the resist film 51 where the exposure reaction has occurred is removed (resist film removal step). As shown in FIG. 12, the area covered with the light shielding area 52 at the time of exposure remains almost unremoved. The remaining film thickness is preferably 200 nm or more. In the region covered with the halftone region 53, a part of the surface side of the resist film 51 is removed, and the resist film 51 on the semiconductor film 50 side remains. The remaining film thickness is preferably about 50 nm to 200 nm. All regions 64 not covered by either the light shielding region 52 or the halftone region 53 are removed. All of the second resist region 62 exposed in the second exposure step is also removed. As a result, the resist film 51 remains only in the first resist region 61 and the third resist region 63, and the film thickness of the first resist region 61 is formed larger than the film thickness of the third resist region 63. It will be. The semiconductor film 50 is exposed at the portion where the resist film 51 is completely removed.

Next, as shown in FIG. 13, the TFT array substrate 2 is irradiated with high-concentration impurity ions (phosphorus ions) from above the resist film 51, and impurity ions are implanted into the semiconductor film 50 (first impurity implantation step). Impurity ions are implanted at a dose of, for example, 0.1 × 10 ¹⁵ to about 10 × 10 ¹⁵ / cm ² . The impurity ions irradiated to the third resist region 63 having a small thickness in the resist film 51 pass through the third resist region 63 in a high concentration state, and the impurity ions are implanted into the semiconductor film 50. On the other hand, the impurity ions irradiated to the first resist region 61 having a large thickness in the resist film 51 cannot pass through the first resist region 61 and do not reach the semiconductor film 50.

  After implanting ions into the semiconductor film 50, the semiconductor film 50 is etched using the resist film 51 as a mask as shown in FIG. 14 to form the semiconductor layer 22 (semiconductor layer forming step). After the semiconductor film 50 is etched, when the resist film 51 is entirely removed as shown in FIG. 15 (resist film peeling step), the patterned semiconductor layer 22 is exposed. As the etching method of the semiconductor film 50, various methods such as dry etching or wet etching are applicable. In the semiconductor layer 22, impurity ions are not implanted into a region overlapping the first resist region 61 in plan view, and impurity ions are implanted into a region overlapping the third resist region 63 in plan view. As described above, the source side high concentration region 22 c and the drain side high concentration region 22 e are formed in the semiconductor layer 22.

  Next, the gate insulating layer 23 is formed on the entire surface of the TFT array substrate 2 including the semiconductor film 50 by plasma CVD, sputtering, or the like (insulating layer forming step). When the gate insulating layer 23 is formed, a conductive film is formed over the entire surface of the gate insulating layer 23, and the conductive film is etched to form a gate electrode 24a so as to straddle the central portion of the semiconductor layer 22 in the vertical direction in the figure. (Gate electrode forming step).

Next, using the gate electrode 24a as a mask, for example, low concentration impurity ions (phosphorus ions) are implanted at a dose of about 0.1 × 10 ¹³ to about 10 × 10 ¹³ / cm ² , and both sides of the gate electrode 24a are implanted. In this region, the source side low concentration region 22b and the drain side low concentration region 22d are formed (second impurity implantation step). The region covered with the gate electrode 24a becomes a channel region 22a into which impurity ions are not implanted. In this manner, the semiconductor layer 22 having the channel region 22a, the source side low concentration region 22b, the source side high concentration region 22c, the drain side low concentration region 22d, and the drain side high concentration region 22e is gated through the gate insulating layer 23. A semiconductor device having a so-called LDD structure disposed opposite to the electrode 24a is formed.

  As described above, in this embodiment, the first resist corresponding to the channel region 22a, the source-side low concentration region 22b, and the drain-side low concentration region 22d of the semiconductor layer 22 in the resist film 51 formed on the semiconductor film 50. Since the resist film 51 is exposed using the light shielding region 52 that covers the region 61 and the second resist region 62 that protrudes from the first resist region 61 in the direction in which the gate electrode 24 a is provided, the exposure light is exposed to the light shielding region 52. The first resist region 61 can be hardly exposed even when it goes around the region covered with. Since the first resist region 61 is hardly exposed, the resist film 51 in the first resist region 61 can be prevented from being removed in the resist film removing step, and the channel region 22a is removed in the first impurity implantation step. Impurity ions can be prevented from being implanted. As a result, current leakage can be prevented from occurring in the channel region 22a, and malfunction can be avoided.

  In the present embodiment, an example in which a diffraction grating is used as a halftone mask is shown. However, any means can be used as long as it uses a light intensity difference.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. Similar to the first embodiment, in the following drawings, the scale is appropriately changed to make each member a recognizable size. Moreover, about the component same as 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted. In this embodiment, the configuration of the semiconductor layer of the TFT and a part of the manufacturing process of the TFT are different from those of the first embodiment, and this point will be mainly described.

FIG. 18 is a plan view showing the configuration of the TFT of the liquid crystal panel according to this embodiment.
As shown in the figure, the semiconductor layer 122 of the TFT 140 is formed in a rectangular shape in plan view, with the horizontal direction in FIG. 18 being the longitudinal direction and the vertical direction being the short direction. The difference from the first embodiment is that the channel region 122a, the source side low concentration region 122b and the drain side low concentration region 122d do not protrude in the extending direction of the gate electrode 124a. About another structure, it is the same as that of 1st Embodiment.

  In order to form the semiconductor layer 122 having such a configuration, a photomask different from the photomask used in the first embodiment is used in the second exposure step in the manufacturing process of the semiconductor device described in the first embodiment. That's fine. In the first embodiment, the light shielding mask 54 that exposes only the second resist region 62 is used. However, in the present embodiment, as shown in FIG. 19, the first resist region 161 and the third resist region 163 of the semiconductor layer 122 In other words, a light shielding mask that covers a rectangular shape, that is, a light shielding mask 154 that covers the central portion of the semiconductor layer 122 in the short-side direction is used.

  The exposure mask 154 is aligned so that the exposure mask 154 covers the central portion of the semiconductor layer 122 in the lateral direction. The lateral side edge of the semiconductor layer 122 by alignment, that is, the second resist region 162, a portion of the first resist region 161 in contact with the second resist region 162, and a part of the third resist region 163 Is exposed. When the exposure light is irradiated to the resist layer 151 covered with the light shielding mask 154, the exposed portion is exposed as shown in FIG.

  As described above, according to the present embodiment, since the edge side in the short direction of the semiconductor layer 122 is exposed, this exposed region is removed in the resist layer removing step, and the light shielding mask 154 is thus removed. As a result, a rectangular area covered with a flat surface remains. In the semiconductor layer forming step, the semiconductor layer 122 having a rectangular shape in plan view is formed using the remaining rectangular region in plan view as a mask. In this manner, the shape of the semiconductor layer 122 can be adjusted without providing a separate process.

  In the present embodiment, an exposure mask 154 that exposes the second resist region 162, a portion of the first resist region 161 in contact with the second resist region 162, and a part of the third resist region 163 is taken as an example. For example, the second resist region 162 and only the portion of the first resist region 161 that contacts the second resist region 162 are exposed, that is, only the portion of the semiconductor layer 122 that protrudes in the short direction is exposed. Of course, such an exposure mask may be used.

The technical scope of the present invention is not limited to the above-described embodiment, and appropriate modifications can be made without departing from the spirit of the present invention.
In the above embodiment, the TFT having the LDD structure has been described as an example. However, the present invention is not limited to this, and the present invention can also be applied to a TFT having the GOLD structure, for example. Moreover, although the example which doped n type phosphorus ion as an impurity was given in the said embodiment, even if it is a case where p type (for example, boron ion etc.) is doped, of course, application of this invention is possible.

1 is a plan view showing an overall configuration of a liquid crystal panel according to a first embodiment of the present invention. The top view which shows the structure of the dot area | region of the liquid crystal panel which concerns on this embodiment. FIG. 3 is a cross-sectional view illustrating a configuration of a dot region of the liquid crystal panel according to the present embodiment. Process drawing which shows the manufacturing process of TFT of the liquid crystal panel which concerns on this embodiment. The process drawing. The process drawing. The process drawing. The process drawing. The process drawing. The process drawing. The process drawing. The process drawing. The process drawing. The process drawing. The process drawing. The process drawing. The process drawing. The top view which shows the structure of TFT of the liquid crystal panel which concerns on 2nd Embodiment of this invention. Process drawing which shows the manufacturing process of TFT of the liquid crystal panel which concerns on this embodiment. The process drawing.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal panel 2 ... TFT array substrate 13 ... Dot region 22 ... Semiconductor layer 22a ... Channel region 22b ... Source side low concentration region 22c ... Source side high concentration region 22d ... Drain side low concentration region 22e ... Drain side high concentration region 23 ... Gate insulating layer 24a ... Gate electrode 25 ... Gate insulating layer 50 ... Semiconductor film 51 ... Resist film 52, 54 ... Light shielding mask 53 ... Halftone mask 61 ... First resist region 62 ... Second resist region 63 ... Third resist region

Claims (4)

A semiconductor layer having a channel region, a source-side low-concentration region, a source-side high-concentration region, a drain-side low-concentration region, and a drain-side high-concentration region, an insulating layer provided on the semiconductor layer, and via the insulating layer A method of manufacturing a semiconductor device comprising a gate electrode provided in a predetermined direction so as to face the semiconductor layer,
A semiconductor film forming step of forming a semiconductor film on the substrate;
A resist film forming step of forming a resist film on the semiconductor film;
Of the resist film, a first resist region corresponding to the channel region, the source-side low concentration region, and the drain-side low concentration region, and the first resist region protrudes in the predetermined direction in which the gate electrode is provided. And the second resist region and the third resist region corresponding to the source-side high concentration region and the drain-side high concentration region, and the light transmittance of the portion covering the first resist region and the second resist region A first exposure step of exposing the resist film using a photomask having a high light transmittance in a portion covering the third resist region;
A resist film removing step of removing the exposed portion of the resist film;
A first impurity implantation step for implanting a first impurity into the semiconductor film from above the resist film after the resist film removing step;
A semiconductor layer forming step of forming the semiconductor layer by etching the semiconductor film using the resist film as a mask after the first impurity implantation step;
After the semiconductor layer forming step, a resist film peeling step for peeling the resist film from the semiconductor layer;
After the resist film peeling step, an insulating layer forming step for forming the insulating layer on the semiconductor layer;
After the insulating layer forming step, a gate electrode forming step of forming the gate electrode at a position corresponding to the channel region on the insulating layer;
And a second impurity implantation step of implanting a second impurity into the semiconductor layer from above the gate electrode. 2. The method according to claim 1, further comprising a second exposure step of exposing at least a part of the second resist region of the resist film after the first exposure step and before the resist film removing step. The manufacturing method of the semiconductor device as described in any one of Claims 1-3. The said 2nd exposure process WHEREIN: At least the part which touches the said 2nd resist area | region among the said 2nd resist area | region and the said 1st resist area | region among the said resist films is exposed. A method for manufacturing a semiconductor device. A semiconductor layer having a channel region, a source-side low concentration region, a source-side high concentration region, a drain-side low concentration region, and a drain-side high concentration region, an insulating layer provided on the semiconductor layer, and via the insulating layer A semiconductor device comprising a gate electrode provided in a predetermined direction so as to face the semiconductor layer,
In the semiconductor device, at least a part of the channel region protrudes in a direction in which the gate electrode is provided.

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