JP2007526484A - System and method for regulating temperature during burn-in - Google Patents

Abstract

Systems and methods for reducing temperature dissipation during burn-in testing are described. Each device under test is exposed to a body bias voltage. The body bias voltage can be used to control the junction temperature (eg, the temperature measured at the device under test). The body bias voltage applied to each device under test can be adjusted from device to device to achieve essentially the same junction temperature in each device.

Description

Related US patent applications

  This application is filed with the E.C. application filed Mar. 1, 2004, entitled “System and Method for Reduce Burning Burn-in” with agent case number TRAN-P281 assigned to the assignee of the present invention. Related to US patent application Ser. No. 10 / 791,241 by Sheng et al., Which is hereby incorporated by reference in its entirety.

  This application is filed with E.C. of application filed Mar. 1, 2004, entitled “System and Method for Reducing Temperature Burning Burn-in” with agent case number TRAN-P283 assigned to the assignee of the present invention. Related to US Patent Application No. 10 / 791,099 by Sheng et al., Which is incorporated herein by reference in its entirety.

  Embodiments herein relate to semiconductor device burn-in. They also relate to systems and methods for controlling temperature during burn-in.

  Semiconductor devices (eg, microprocessors) are screened for defects by performing a burn-in operation that exposes the apparatus to test conditions, including high temperature test conditions. However, due to variations in burn-in power, ambient temperature, airflow, and heat sink performance, all devices under test may not experience the same temperature during testing.

  Variation in the wafer manufacturing process is a main cause of variation in burn-in power. Variations in the manufacturing process can cause leakage currents that differ by 100 percent between parts. The leakage current from the chip is proportional to the number of transistors on the chip, while the leakage current is inversely proportional to the critical dimension of the transistor. Increasing the number of transistors and reducing the size of transistors are currently accelerating in chip manufacturing, but they are exacerbating the situation. A solution that can improve the problems caused by burn-in power variation would be advantageous.

  Thus, a system and / or method for controlling the temperature during burn-in would be beneficial so that all devices experience essentially the same temperature during burn-in.

  Accordingly, a system and / or method for controlling temperature during burn-in testing is disclosed. In one embodiment, each device under test (device under test) is exposed to a body bias voltage. The body bias voltage can be used to control the “junction temperature” (eg, the temperature measured at the device under test). The body bias voltage applied to each device under test can be adjusted from device to device to achieve essentially the same junction temperature in each device.

  Systems and methods for reducing temperature dissipation during burn-in testing are described. Each device under test is exposed to a body bias voltage. The body bias voltage can be used to control the junction temperature (eg, the temperature measured at the device under test). The body bias voltage applied to each device under test can be adjusted from device to device so that essentially the same junction temperature is achieved in each device.

  Reference will now be made in detail to various embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with these embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be understood by one skilled in the art that the present invention may be practiced without the use of these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention.

  Some portions of the detailed descriptions that follow are presented in terms of operational procedures, logic blocks, processing, and other symbolic representations of data bits within a computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. Procedures, logic blocks, processes, etc., both in this document and generally, are considered a consistent series of steps or instructions that lead to the desired result. A step is one that requires physical manipulation of physical quantities. Typically, these quantities take the form of electrical or magnetic signals that can be stored, transferred, combined, compared, and otherwise manipulated in a computer system, but not necessarily. Calling these signals by bits, bytes, values, elements, symbols, characters, terms, numbers, etc. has proven to be often convenient, mainly because of their common usage.

  It should be borne in mind, however, that these and similar terms are all associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. As will be apparent from the following description, unless otherwise specified, throughout the present invention, such as “apply”, “select”, “measure”, “adjust”, “adjust”, “access”, etc. Descriptions that use the terminology include manipulating data represented as physical (electronic) quantities in computer system registers and memory to store, communicate, or store computer system memory or registers or other such information. It should also be understood that it refers to the operation and process of a computer system or similar intelligent electronic computing device (eg, flowchart 400 of FIG. 4) that translates into other data that is also represented as a physical quantity in the display device. .

  The following description of embodiments of the present invention was formed in a surface N-well via an n-type doped conductive sub-surface region when a p-type substrate and an N-well process are utilized. The coupling of a body bias voltage to a p-type field effect transistor (pFET) or a p-type metal oxide semiconductor field effect transistor (p-type MOSFETS) is described. However, embodiments in accordance with the present invention provide an n-type formed in a surface P-well via a p-type doped conductive sub-surface region when an n-type substrate and a P-well process are utilized. The present invention is similarly applicable to coupling a body bias voltage to a type FET (nFET) or an n-type MOSFET. Therefore, the embodiment according to the present invention. It is also well suited for semiconductors formed on either p-type or n-type materials.

  FIG. 1 shows a top view of a pFET 50 (or p-type MOSFET) formed in an N-well 10 when a p-type substrate and N-well process are utilized in accordance with one embodiment of the present invention. N-well 10 has n-type doping. A region of a semiconductor device doped with an n-type dopant has one type of conductivity, while a region doped with a p-type dopant has another type of conductivity. In general, different dopant concentrations are utilized in different regions of a semiconductor device.

  In the present embodiment, the pFET 50 has a body bias voltage Vnw applied to its bulk, that is, the body terminal B. As shown in FIG. 1, the pFET 50 has a gate G, a drain D (p-type doping), a source S (p-type doping), and a bulk / body terminal B. In particular, bulk / body terminal B is coupled to N-well 10. Thus, the voltage applied to bulk / body terminal B is received by N-well 10. In the case of the body bias, the bulk / body terminal B receives the body bias voltage Vnw. Therefore, the body bias voltage Vnw is applied to the N well 10.

  The pFET 50 is body biased to affect its performance. Without body bias, source S and bulk / body terminal B are coupled. When body biased, source S and bulk / body terminal B are not coupled. The body bias allows to control the potential difference between the source S of the pFET 50 and the bulk / body terminal B, thereby providing the ability to control the threshold voltage level of the pFET 50. Other parameters such as the leakage current associated with pFET 50 can also be controlled thereby. Increasing the threshold voltage decreases the leakage current. Therefore, a leakage current can be reduced by using a body bias that increases the threshold voltage.

  Burn-in operation to detect integrated circuit defects is typically stress temperature (eg, 150 ° C.), stress voltage (eg, 1.5 times the nominal operating voltage), and lower operating frequency (typically higher than normal operating frequency). Executed several orders of magnitude slower).

  FIG. 2 illustrates a number of devices under test (DUTs) 101, 102,... Configured for burn-in operation according to one embodiment of the invention. . . An exemplary apparatus 100 is included, including N (eg, an integrated circuit device). In an embodiment of the present invention, integrated circuit devices 101, 102,. . . N is illustrated by the pFET 50 of FIG. As described above, the integrated circuit devices 101, 102,. . . N may instead be an nFET.

  The integrated circuits 101, 102,. . . N can be arranged on one printed wiring board 110, which is integrated circuit devices 101, 102,. . . A socket for accepting N may be included. Since it is desirable to operate the device under test at a high temperature, the wiring board 110 is generally disposed in a temperature chamber capable of adjusting the temperature at a test temperature (eg, 150 ° C.). A typical burn-in test chamber can include a number of wiring boards.

  Wiring board 110 includes, for example, various power supplies, test controllers and / or instruments, and integrated circuit devices under test 101, 102,. . . N includes wiring traces that carry electrical signals between N. In the present embodiment, the wiring board 110 includes an operating voltage supply distribution system 151 and a test control distribution system 152. It should be understood that distribution systems 151 and 152 can be configured using buses, point-to-point, individual topology logic, and the like.

  Test control distribution system 152 includes test controller 150 and integrated circuit devices under test 101, 102,. . . N and the integrated circuit devices under test 101, 102,. . . A signal is transmitted to N. As will be described in more detail below, the test controller 150 includes an integrated circuit device under test 101, 102,. . . A voltage source, a temperature monitoring device, and an ambient temperature sensor are also coupled to measure and control electrical parameters related to N power consumption and temperature.

  The test control device 150 can be disposed on the wiring board 110. However, due to various factors (e.g., the physical size and / or nature of the equipment used to implement the test controller 150), embodiments according to the present invention make components of the test controller 150 a test environment. It is well suited to be placed somewhere else within (eg, on a separate wiring board coupled to wiring board 110 or outside the thermal test chamber). For example, if the test controller 150 is implemented as a workstation computer, placing such a workstation in a thermal test chamber is generally impractical due to its size and operating temperature range.

  Using a test unit controller that may or may not be part of the test controller 150, the integrated circuit devices 101, 102,. . . N can be stimulated with a test pattern sequence and / or a test command to access the results. Embodiments in accordance with the present invention are well suited for a wide variety of test unit controllers and test methods, including, for example, Joint Test Action Group (JTAG) boundary scan and Array Built-in Self Test (ABIST).

  The operating voltage supply distribution system 151 includes an operating voltage source 140 and integrated circuit devices under test 101, 102,. . . N is bound. The operating voltage source 140 includes the integrated circuit devices 101, 102,. . . Provides the voltage (Vdd) and current that activates N. In this embodiment, the operating voltage source 140 is also coupled to the test controller 150 by, for example, a bus 156 so that the operating voltage source 140 can receive a control signal from the test controller 150.

  In this embodiment, each of the integrated circuit devices 101, 102,. . . N is a positive body bias voltage generator 121, 122,. . . To N. Positive body bias voltage generators 121, 122,. . . N is the integrated circuit device under test 101, 102,. . . A positive body bias voltage is provided to an n-type well located under the N pFET device. Such body bias allows the threshold voltage of the pFET device to be adjusted, for example to reduce the leakage current of the pFET device. In one embodiment, generators 121, 122,. . . The body bias voltage provided by N is in the range of about 0-5 volts. In the present embodiment, the positive body bias voltage generators 121, 122,. . . N is also coupled to test controller 150 by, for example, bus 157 so that the body bias voltage generator can receive control signals from test controller 150.

  Similarly, each integrated circuit device 101, 102,. . . N is the respective negative body bias voltage generator 131, 132,. . . To N. Negative body bias voltage generators 131, 132,. . . N is the integrated circuit device under test 101, 102,. . . A negative body bias voltage is provided to a p-type well located under the N nFET device. Such body bias makes it possible to adjust the threshold voltage of the nFET device, for example to reduce the leakage current of the nFET device. In one embodiment, generators 131, 132,. . . The body bias voltage provided by N is in the range of about 0-10 volts. In the present embodiment, the negative body bias voltage generators 131, 132,... Are arranged so that the body bias voltage generator can receive a control signal from the test controller 150. . . N is also coupled to test controller 150 by bus 157, for example.

  In an embodiment of the present invention, positive body bias generators 121, 122,. . . N and negative body bias voltage generators 131, 132,. . . It should be understood that N can be located on the wiring board 110 or can be located outside the wiring board 110.

  Generally, body bias voltage generators 121, 122,. . . N and 131, 132,. . . N is a variable voltage source. Their output voltages can be set to specific values (within a certain range). Such specific values are preferably set digitally (eg, by a command from the test controller 150), but are not required. The body bias current is typically on the order of low microamperes per integrated circuit. Therefore, the bias voltage generators 121, 122,. . . N and 131, 132,. . . N can be a relatively small and inexpensive voltage source.

  In this embodiment, the apparatus 100 also includes an ambient temperature monitor 160 that measures the ambient temperature within the test chamber. The ambient temperature measurement value is reported to the test controller 150 via the bus 154, for example. The apparatus 100 can include more than one ambient temperature monitor.

  Still referring to FIG. 2, each of the integrated circuit devices 101, 102,. . . N is a temperature monitor 111, 112,. . . To N. Temperature monitors 111, 112,. . . N is the respective integrated circuit device under test 101, 102,. . . Measure the temperature at N. The temperature measurement value is reported to the test controller 150 via the bus 153, for example.

  FIG. 3 is a cross-sectional side view of an integrated circuit device 101 configured for burn-in testing in accordance with one embodiment of the present invention. FIG. 3 shows the integrated circuit device 101 connected to the wiring board 110 by a number of pins 350. In this embodiment, the integrated circuit device 101 includes a ball grid array (BGA) 340, a package 330, a die 320, and a heat sink 310. It should be understood that the elements comprising integrated circuit device 101 are merely exemplary and the invention is not limited to use with the integrated circuit illustrated by FIG.

  In the present embodiment, the temperature monitor 111 is located between the heat sink 310 and the die 320. The temperature monitor 111 can be a thermocouple, for example. Temperature monitor 111 is connected to trace 315, which can then be connected to bus 153 of FIG. 2, or can represent a portion thereof.

  The temperature measured at the integrated circuit device under test is referred to herein as the “junction temperature”. In the example of FIG. 3, the junction temperature refers to the temperature of the die 320.

Referring to FIG. 2, the integrated circuit devices under test 101, 102,. . . The junction temperature (T _junction ) of N can be approximated according to the following relational expression.
T _junction = T _ambient + Pθ _i [1]
_Where T _ambient is the ambient temperature measured by ambient temperature monitor 160, P is the power consumed by the integrated circuit device, and θ _i is the thermal resistance of the integrated circuit device (eg, from die 320 of FIG. The thermal resistance associated with the transfer of heat to the air.

The power consumption (P) is a function of both the operating voltage supplied to the integrated circuit and the body bias voltage applied to the integrated circuit. In embodiments of the present invention, as will be appreciated, the junction temperature may be reduced for all integrated circuit devices 101, 102,. . . Since the power consumption P can be adjusted to be basically the same with respect to N, θ _i can be set to all the integrated circuit devices under test 101, 102,. . . N can be treated as a constant.

  The operation of the apparatus 100 of FIG. 2 according to one embodiment of the present invention will now be described. In summary, the power consumption of the integrated circuit (P in Equation [1]) can be adjusted by adjusting the threshold voltage of the integrated circuit even if the operating voltage of the integrated circuit is kept constant. The threshold voltage can be adjusted by adjusting the body bias voltage supplied to the body bias well located below the active semiconductor of the integrated circuit. By adjusting the threshold voltage of the integrated circuit, it is possible to increase or decrease the leakage current of the integrated circuit, which is an important component of the power consumption P of the integrated circuit, especially during low frequency operation, for example during a burn-in process. Thus, control of power consumption is achieved by controlling the leakage current, and leakage current is controlled by controlling the body bias voltage.

In the embodiment of the present invention, the junction temperature (T _junction ) of the integrated circuit under test is basically constant at the _ambient temperature (T _ambient ) and the thermal resistance (θ _i ), as shown by the above formula [1]. , It can be controlled by controlling the power (P) consumed by the integrated circuit. The power (P) consumed by the integrated circuit operating at a constant operating voltage can be controlled by the body bias voltage applied to the integrated circuit.

Referring to FIG. 2, a specific junction temperature (eg, 150 ° C.) is selected for burn-in testing. The ambient temperature of the thermal test chamber can also be specified. Each of the integrated circuit devices 101, 102,. . . The thermal resistance (θ _i ) associated with N is also a known quantity that is at least a sufficient approximation. The voltage supplied by the operating voltage source 140 is also known. With this information, each integrated circuit device 101, 102,. . . An initial value of the magnitude of the body bias voltage to be applied to N can be estimated.

  However, each integrated circuit device 101, 102,. . . N is a temperature monitor 111, 112,. . . Since N is individually monitored, it is not necessary to determine the magnitude of the body bias voltage to be initially applied to the device under test. Instead, the magnitude of the body bias voltage to be applied can be determined empirically by measuring the junction temperature and then adjusting the body bias voltage to achieve the desired junction temperature for burn-in testing. it can.

  After the burn-in test operation is initiated, each of the integrated circuit devices 101, 102,. . . The N junction temperature is monitored. If any device under test experiences a junction temperature different from that desired for burn-in testing, the body bias voltage of the device under test can be adjusted (increased or decreased) until the junction temperature returns to the desired value. . In the present embodiment, the integrated circuit devices 101, 102,. . . N is respectively a respective positive body bias voltage generator 121, 122,. . . N and negative body bias voltage generators 131, 132,. . . The body bias voltage associated with N and thus applied to one device under test can be adjusted without affecting the body bias voltage applied to the other device under test.

  Each of the integrated circuit devices 101, 102,. . . The body bias voltage applied to N can be automatically adjusted by the test controller 150 based on feedback from the temperature monitor, or can be manually adjusted.

  Thus, each integrated circuit device 101, 102,. . . The junction temperature of N can be controlled by controlling the body bias voltage applied to each device. This method can handle variations between devices under test so that each device is exposed to the same test temperature.

  For example, some devices under test are exposed to higher ambient temperatures than others because the ambient temperature in the test chamber may not be uniform. When this occurs, the junction temperature is a function of the ambient temperature (see Equation [1] above) and is reflected in the measured junction temperature. Thus, the junction temperatures of the higher temperature region devices in the test chamber are adjusted by adjusting the body bias voltage applied to these devices until their respective junction temperatures reach the desired test temperature. be able to.

  In a similar manner, variations in heat sink performance between devices under test can be addressed. There may be other variables that affect the junction temperature, and variations between the various devices under test can be introduced. In general, reducing device-to-device variation so that each device under test is exposed to essentially the same burn-in test temperature by applying different back bias voltages to different devices under test as needed Can do.

  In addition, the body bias voltage can be adjusted over the course of the burn-in test to account for changes in test conditions that may occur over time. For example, as the test chamber begins to heat, the body bias voltage can be adjusted not only to maintain the desired junction temperature, but also to control the ambient temperature within an acceptable range.

  FIG. 4 is a flowchart 400 of a method for controlling temperature during a burn-in test in accordance with one embodiment of the present invention. Although specific steps are disclosed in flowchart 400, such steps are exemplary. That is, the present invention is well suited to performing various other steps or variations of the steps shown in flowchart 400. It should be understood that the steps of flowchart 400 may be performed in a different order than presented.

In block 410 of FIG. 4, an operating voltage is applied to the device under test.
At block 420, a body bias voltage is applied to the device under test. The magnitude of the body bias voltage is selected so that a specific test temperature is achieved in the device under test. In one embodiment, the device under test comprises a p-type metal oxide semiconductor (PMOS) device and the body bias voltage is in the range of about 0-5 volts. In other embodiments, the device under test comprises an n-type metal oxide semiconductor (NMOS) device and the body bias voltage is in the range of about 0-10 volts.

  At block 430, the temperature of the device under test (eg, junction temperature) is measured.

  At block 440, the magnitude of the body bias voltage applied to the device under test is adjusted by the necessary amount if necessary to maintain the desired test temperature (eg, junction temperature) at the device under test. . The flowchart 400 then returns to block 430. With this method, the temperature is continuously measured during burn-in, and the body bias voltage is adjusted to maintain the correct junction temperature during burn-in.

  For example, referring to FIG. 2, the integrated circuit device 101 under test receives an operating voltage supplied by a voltage source 140. The integrated circuit device 101 under test also has a body bias from either a positive body bias voltage generator 121 (if the device 101 is an NFET device) or a negative body bias voltage generator 131 (if the device 101 is a PFET device). Receive voltage. The temperature of the integrated circuit device 101 under test is measured using a temperature monitor 111. The temperature of the integrated circuit device 101 under test is provided to the test controller 150. If the temperature of the integrated circuit device 101 under test is lower or higher than the desired test temperature, the test controller 150 provides the device with either the positive body bias voltage generator 121 or the negative body bias voltage generator 131. The body bias voltage to be adjusted can be adjusted. Similarly, when the temperature measured by the ambient temperature monitor 160 increases, the test controller 150 provides to the integrated circuit device 101 under test by either the positive body bias voltage generator 121 or the negative body bias voltage generator 131. The body bias voltage applied can be adjusted to maintain the desired test temperature of the device.

  In summary, embodiments of the present invention provide a system and method for controlling the temperature during burn-in so that all devices experience essentially the same temperature during burn-in. Thus, basically all devices under test can be placed under the same test conditions. As a result, without it, the sources of uncertainty introduced into the test results are eliminated.

  Although all devices under test have been described for tests that are exposed to essentially the same test temperature, it should be understood that embodiments of the present invention can also be used to test devices under a range of temperatures simultaneously. . For example, by exposing various devices under test to different body bias voltages, some devices can be tested at one junction temperature while other devices can be tested at another junction temperature.

  In addition, although a test has been described in which the device under test is exposed to a test temperature that remains essentially constant during burn-in operation, embodiments of the invention are also used to change the temperature during the test. Please understand that you can. For example, by changing the body bias voltage in a controlled manner during burn-in, the junction temperature during burn-in also changes in a controlled manner.

  Embodiments of the present invention, that is, systems and methods for controlling temperature during burn-in, are thus described. Although the invention has been described in specific embodiments, it should be understood that the invention should not be construed as limited by such embodiments, but rather construed according to the claims that follow.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIG. 3 shows a plan view of a p-type field effect transistor (pFET) formed in an N-well according to an embodiment of the present invention. 2 illustrates an exemplary arrangement of integrated circuit devices configured for burn-in testing according to one embodiment of the present invention. 1 is a cross-sectional side view of an integrated circuit device configured for burn-in testing according to one embodiment of the present invention. 4 is a flowchart of a method for controlling temperature during a burn-in test according to an embodiment of the present invention.

Claims (23)

A device under test adapted to receive a body bias voltage;
A voltage source for providing the body bias voltage to the device under test;
A wiring board for coupling the device under test and the voltage source;
Including
An apparatus for burn-in testing, wherein the device under test is configured to be exposed to a test temperature adjusted according to the body bias voltage.   The apparatus of claim 1, wherein the body bias voltage is selected to achieve a specific test temperature measured at the device under test.   The apparatus according to claim 1, further comprising a test control device coupled to the device under test via the wiring board.   The apparatus of claim 1, further comprising a second voltage source for providing an operating voltage to the device under test.   The apparatus of claim 1, wherein the device under test comprises a p-type metal oxide semiconductor (PMOS) device.   The apparatus of claim 5, wherein the body bias voltage is in the range of about 0-5 volts.   The apparatus of claim 1, wherein the device under test comprises an n-type metal oxide semiconductor (NMOS) device.   The apparatus of claim 7, wherein the body bias voltage is in the range of about 0 to −10 volts. A burn-in test method for a device under test,
Applying an operating voltage to the device under test;
Applying to the device under test a body bias voltage selected to achieve a specific test temperature measured at the device under test;
Measuring temperature at the device under test;
Including methods.   The method of claim 9, further comprising adjusting the body bias voltage to adjust the temperature of the device under test.   The method of claim 9, wherein the device under test comprises a p-type metal oxide semiconductor (PMOS) device.   The method of claim 11, wherein the body bias voltage is in the range of about 0-5 volts.   The method of claim 9, wherein the device under test comprises an n-type metal oxide semiconductor (NMOS) device.   The method of claim 13, wherein the body bias voltage is in the range of about 0 to −10 volts. A plurality of devices under test, each device under test adapted to receive a body bias voltage, and configured to monitor the temperature of each device under test;
A voltage source for providing a body bias voltage applied to the device under test;
A wiring board including circuitry that individually couples each device under test to the voltage source so that each device under test can receive a different body bias voltage;
Including burn-in test equipment.   The apparatus according to claim 15, further comprising a test control device coupled to the device under test via the wiring board.   The apparatus of claim 15, further comprising a voltage source for supplying an operating voltage to the device under test.   The apparatus of claim 15, wherein the device under test comprises a p-type metal oxide semiconductor (PMOS) device.   The apparatus of claim 18, wherein the body bias voltage is in a range of about 0-5 volts.   The apparatus of claim 18, wherein the device under test comprises an n-type metal oxide semiconductor (NMOS) device.   21. The apparatus of claim 20, wherein the body bias voltage is in the range of about 0-10 volts.   The apparatus according to any one of claims 15 to 21, wherein a body bias voltage applied to the device under test is selected to achieve a specific test temperature measured at the device under test. 9. Apparatus according to any one of the preceding claims, wherein the adjustment of the test temperature is processed by adjusting the body bias voltage and the device under test is exposed to a burn-in test temperature.

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