JP2007507025A - Processor array, fabric structure, surface covering structure, and method for transferring power between a plurality of processor elements locally adjacent to each other - Google Patents

Abstract

In a processor array having a plurality of processor elements connected to each other, even if an electrical short circuit occurs, a failure of the entire processor array is avoided.
A processor element is disclosed that includes a plurality of power interfaces, a plurality of power switches, and a defect inspection unit for inspecting whether a short circuit to a connected adjacent processor element has occurred in the power interface. To do. When a short circuit does not occur, each power switch is closed and power is supplied to each power interface.
[Selection] Figure 1

Description

Detailed Description of the Invention

  The present invention relates to a processor array, a fabric structure, a surface covering structure, and a power transmission method between a plurality of processor elements disposed locally adjacent to each other.

  Patent Document 1 describes a processor array including a plurality of processor elements. Each processor element includes an image forming element such as a light emitting diode, a memory, a plurality of data communication interfaces, and a plurality of power supply interfaces.

  These individual processor elements are freely located locally in the processor array and are linked to the immediately adjacent processor elements by the data communication interface of the processor elements for exchanging electronic messages. ing. These processor element groups in which processor elements located immediately adjacent to each other by a power supply interface are connected to each other are connected to a common voltage source.

  As described above, Patent Document 1 discloses a circuit network including distributed processor groups or processor element groups in which power is supplied from a common voltage source. Such circuitry is susceptible to electrical shorts that occur there. In connection with the use of a common voltage source, the occurrence of a single electrical short will result in an overall failure of the network of processor elements.

  Further, a self-organization method of processor elements (that is, a method of automatically determining the position of a processor element in a processor array with respect to a reference position) is also described in Patent Document 1. Each position is determined by exchanging electronic messages locally only between processor elements located immediately next to each other.

  Another problem (generally occurring in an arbitrary network of processor elements) of a circuit network composed of processor element groups described in Patent Document 1 is placed at a reference position in order to output information. In other words, processor element groups having different path lengths from the interface processor are driven synchronously. Here, the interface processor supplies data to all the processor elements of the processor array.

  Japanese Patent Application Laid-Open No. 2004-228561 discloses various network circuits including a circuit network including processing elements and a connection control mechanism controlled by a program for classifying the processing elements under program control. Here, each processing element is connected to an adjacent processing element via a connecting portion.

  Patent Document 3 discloses a power supply bus system including a voltage supply device for controlling supply of voltage to the bus system. This voltage supply device checks whether the resistance of the voltage output is sufficiently high and controls the voltage supply to the bus system accordingly.

  U.S. Pat. No. 6,089,089 discloses an interconnected LED network suitable for clothing.

Publications cited herein are as follows:
DE 101 58 784 A1 DE 37 88 758 T2 DE 196 43 014 C1 US 2003/0100837 A1

  As will be described in detail below, a network of processor elements is always used to display symbols and symbol strings, such as letters and arrows, even when the processor elements in the processor array are defective. Fully functional and operable. However, when displaying symbols and symbol strings, it is necessary to mask these defective processor elements and send a message containing information displayed by the imaging element. Also, it is necessary to reconfigure the routing path connected by the routing branch around the defective processor element. In addition, while displaying symbols and graphics, all image points in the frame that exist in the network composed of image forming element groups, that is, exist in the circuit network composed of processor elements. Need to be driven synchronously.

  Depending on the number of image points, a data transfer rate “number of image points included in an image per second” occurs.

  These two above requirements greatly increase the bandwidth requirement for data channels between processor elements in order to transmit electronic messages with displayed symbols and graphics. If some of the processor elements in the processor array are damaged and the routing channels or routing paths need to be integrated, the data transfer rate required for the integrated channels is further increased. Therefore, an excessive transmission rate is required to achieve the required bandwidth.

  An object of the present invention is to avoid a failure of the entire processor array even if an electrical short circuit occurs in a processor array having a plurality of processor elements connected to each other.

  This object is achieved by a processor arrangement, a fabric structure, a surface covering structure and a method for power transmission between a plurality of processor elements arranged locally adjacent to one another, having the features of the independent claims.

The processor array includes a plurality of processor elements. Each processor element comprises:
At least one processor.
A plurality of power supply interfaces for transmitting power from a plurality of processor elements adjacent to the processor element, and a plurality of power supply interfaces for transmitting power to a plurality of processor elements adjacent to the processor element .
A plurality of power switches respectively assigned to each power interface, which can supply power to each power interface or not supply power as desired.
At least one short-circuit test unit for checking whether an electrical short circuit has occurred to an adjacent processor element electrically connected to each processor;
A control unit configured to close each power switch and supply power to the power interface when there is no short circuit in the power interface.

  Further, in the processor array of the present invention, only processor elements that are locally arranged next to each other are exchanged at least to a certain extent in order to exchange electronic messages and to transmit power. ing.

  Furthermore, a fabric structure comprising the above processor array is provided. Here, the processor is arranged in the fabric structure. Further, the woven structure includes conductive single fibers that connect the processors to each other and conductive data transmission single fibers that connect the processors to each other.

  Finally, electrically non-conductive single fibers are provided in the woven structure. This textile structure can be used to coat a surface, preferably to coat a floor, wall or ceiling.

  The fabric structure can be used in any desired fabric including, for example, curtains, roll-up blinds made of fabric, or Venetian blinds.

  The fabric structure includes a plurality of processor elements for processing electronic data. The plurality of processor elements can be supplied with power through conductive single fibers similarly provided in the fabric structure. The plurality of processor elements can receive supply of data to be processed and transmit the data via a data transmission single fiber.

  With the above configuration, the woven structure is particularly effective in that it can be manufactured in a wider area than the prior art and can be easily cut into a desired shape. Thus, the fabric structure can be adapted to any desired surface that is covered by the fabric structure. Since the individual processor elements are already coupled to one another in the fabric structure, there is no need to later couple the processor elements and sensors and / or actuators that may be provided to one another.

  In other words, the plurality of processor elements are embedded in a fabric structure that is clad (attached) to the surface.

  Individual processor elements are preferably capable of exchanging electronic messages with other processor elements in the fabric structure via a data transmission monofilament. This is because of the additionally provided elements, i.e. it is preferable that the position of each processor element in the fabric structure can be determined locally with respect to a predetermined reference position, i.e. self-organization can be performed. . In the present invention, the self-organization is preferably performed according to the method described in Patent Document 1.

  Thus, even if the fabric structure is cut into a predetermined shape and the connection lines between the processor elements or the individual processor elements are broken or removed by this cutting, the processor elements do not use other external information. It is possible to determine the position of oneself within a certain area very easily.

  Therefore, when the processor elements are self-organized, a fabric structure for mass sales can be formed very simply and inexpensively. In order to perform the coating with the fabric structure, the fabric structure can be adjusted to a predetermined shape. Also, where the processor elements in the area covered by the fabric structure are uniquely addressed to uniquely address each processor element in the fabric structure, despite the fact that other electronic devices are woven into the fabric. It is not necessary to pay attention to the arrangement.

  The surface covering structure has a woven structure on which the surface covering is fixed. This fixing is preferably performed by adhesion and / or lamination and / or vulcanization.

  When using the method described in Patent Document 1 and the processor array described in Patent Document 1, only local information is used, and electronic messages are exchanged between processor elements arranged immediately adjacent to each other. .

  Thus, this procedure is very robust against failures and failures that occur in individual processor elements or in individual coupling between two processor elements, for example when cutting a fabric structure into a predetermined shape.

  In a method for transmitting power between a plurality of processor elements disposed locally adjacent to each other, each processor element includes the above-described elements. In this method, the processor element is connected to the power supply interface of the processor element. To determine whether there is an electrical short to an adjacent processor element coupled to (ie, connected to) the processor element. If there is no electrical short in the power interface, the corresponding power switch is closed. Thereby, electrical energy is supplied to the power supply interface and to a processor element adjacent to the processor element.

  According to the present invention, as described above, an electronic circuit in a processor element of the processor array and a corresponding method are provided. With these, a controlled configuration of the power path is provided in a controlled manner without the risk of electrical shorts between the two processor elements destroying the entire processor array.

  Specifically, the region causing the electrical short is determined by the method and the array. Then, while forming a channel for supplying power, the region is masked and automatically deactivated.

  Preferred embodiments of the invention are described in the dependent claims.

  The embodiments of the present invention described below relate to a processor array, a fabric structure, a surface covering structure, and a method for transmitting power between a plurality of processor elements that are locally adjacent to each other.

  In one form of the invention, at least some of the processor elements (ie, at least a portion of the processor elements) comprise sensors and / or actuators coupled to the processor. In this case, sensor data and / or actuator data are transmitted as electronic messages between processor elements arranged adjacent to each other.

  In one form of the invention, the at least one short circuit inspection unit comprises a current limiting device. With this form of the invention, it is possible to reliably and easily test for an electrical short without risking the processor element itself being tested.

  In another form of the invention, a current limiting device is assigned to each power switch. Here, at least some power switches are set as power limit switches. This configuration of the present invention allows the processor element of the present invention, and hence the processor array of the present invention, to be easily and inexpensively manufactured.

  The processor elements of the processor array are preferably arranged in a matrix consisting of rows and columns.

  Furthermore, in one form of the invention, the processor array comprises at least one interface processor. This interface processor serves as a message interface for the processor array and can “inject” electronic messages into the processor array, ie, transmit electronic messages to the processor array. Accordingly, in the electronic message, sensor data and / or actuator data is transmitted from and transmitted to the interface processor.

  In one form of the invention, the conductive monofilament is set to be used to supply power to a plurality of processor elements.

  In the woven fabric structure, the conductive data transmission single fiber may have electrical conductivity, that is, conductivity.

  In another form of the woven structure, the conductive data transmission monofilament has optical conductivity.

  The plurality of processor elements can be arranged in a regular pattern of fabric structure, preferably a regular rectangular or square pattern.

  Each processor element of the plurality of processor elements is arranged adjacent to one another by a conductive monofilament and a conductive data transmission monofilament, i.e. four neighbors each in the case of a regular rectangular pattern It is particularly preferred to be connected to a processor element.

  The sensor of the present invention included in the processor element is preferably configured as a pressure sensor, a heat sensor, a noise sensor, a light sensor, or a volume sensor.

  In one embodiment of the present invention, the actuator provided in the processor element is configured as an image forming element, a sound wave generating element, or a vibration generating element.

  In other words, each processor element integrates at least one actuator. This actuator is, for example, an image forming unit or a sound generation unit. The actuator is preferably a liquid crystal display unit or a polymer electronic display unit, but in general, it may be any display unit or any speaker that generates sound waves, and generally any electromagnetic wave generating unit. These elements may be used. As another actuator provided in the processor element, there is a vibration generating element.

  In another form of the invention, in a processor array, electronic messages are exchanged between a first processor element and a second processor element adjacent to the first processor element to establish a distance between the first processor element and a reference position. Thus, a plurality of processor elements are set. Each electronic message includes, as an item, distance information indicating the distance from the reference position of the processor element that transmits the message or the processor element that receives the message. Further, the plurality of processor elements can determine each distance to the reference position and / or store each distance to the reference position based on the distance information item of the received message. Is set.

  In order to perform self-organization and to determine a distance information item that specifies the distance of each processor element in the processor array from a predetermined reference position, these processor elements are in accordance with Patent Document 1. It is particularly preferable that it is set.

  The surface covering structure is preferably formed as a wall covering structure, a floor covering structure, or a ceiling covering structure.

  This surface covering structure may have a fabric in which conductive wires are uniformly woven, covering at least a partial region of the fabric structure.

  In order to avoid “electric smog”, a fabric woven with conductive wires can be used around the human body. In this way, the “electric smog” can be shielded. In this case, it should be noted that certain areas (especially those above the capacitive sensor) do not have to be covered by the shield.

The present invention is particularly suitable for use in the following application areas.
・ Home automation, especially for improving convenience at home.
A warning system that determines the location of the intruder and the weight of the intruder (it is optional to determine the weight).
-Automatic guidance to visitors at trade shows, exhibitions or museums.
For emergency guidance systems, for example on airplanes or trains, to show passengers the route to the emergency exit.
A fabric-concrete structure that can use a woven structure to detect possible damage and inform the user of the damage if appropriate.
-Obtain information to collect statistics on how long a customer stays in a store area.

  The woven fabric structure of the present invention is preferably composed of a conductive single fiber, preferably a conductive warp single fiber and a conductive weft, in addition to a basic fabric made of synthetic fibers (electrically non-conductive single fibers). Contains monofilament. The conductive single fiber is preferably made of, for example, copper, polymer single fiber, carbon single fiber, or other conductive wires. In the case of using a metal wire, it is preferable to coat with a noble metal such as gold or silver in order to prevent corrosion due to moisture or when it may come into contact with a highly reactive solvent. Alternatively, the metal single fiber may be insulated by applying an insulating paint such as polyester, polyamidineamide, or polyurethane.

  In addition to the conductive fiber, an optical fiber made of plastic or glass may be used as the data transmission single fiber. The woven fabric that is the basis of the woven structure is preferably formed to a thickness suitable for the thickness of the microelectronic element to be integrated. The microelectronic element is also referred to as a microprocessor module below, and is, for example, a sensor, a light emitting diode, and / or a microprocessor. The sensor may be, for example, a pressure sensor, a heat sensor, a noise sensor, a light sensor, or a volume sensor.

  The spacing between the optically and / or electrically conductive fibers is preferably selected to match the connection pattern of the integrated processor elements.

  Although the following embodiments describe a carpet structure, the present invention is not limited to carpets and is suitable for devices suitable for coating or cladding a surface, generally with adjacent processor devices. It can be applied to all processor arrays and all processor elements that need to detect electrical shorts.

  The textile structure of the present invention with integrated microelectronic elements and / or sensors and / or actuators (e.g. small indicator lamps) is essentially fully functional and can be fixed to various surface coatings. Is.

  In this case, as the surface coating, for example, non-conductive fabric, floor covering made of carpet, parquet, plastic, curtain, roll-up blind, wallpaper, insulating mat, tent roof, stucco layer, screed, and And fiber concrete. The fixing is preferably performed by adhesion, lamination, or vulcanization.

In another configuration of the invention, the processor array is provided with both:
At least one interface processor that provides a message interface to the processor array;
A group of processors in which, at least to some extent, only processors that are locally located next to each other are interconnected to exchange electronic messages.
An actuator assigned to each processor in the processor group and connected to the corresponding processor. Here, in the electronic message, the actuator data is transmitted by the interface processor.
At least one clock oscillation device for synchronously clocking a plurality of processors;
A unit for assigning a time stamp to an electronic message having actuator data based on the actuator data. Here, the electronic message having the actuator data is to be transmitted to a processor element in order to execute an operation at a predetermined time, and the operation is executed by each processor element. This specifies the number of cycles until.

  Note that in this regard, a synchronous clock is not necessarily required.

  The processor array may include a processor element distance memory that stores the distance of each processor from the interface processor.

  Furthermore, a time stamp determination unit may be provided that is adjusted to determine the time stamp required for the electronic message using the distance of each processor element from the interface processor.

  The processors of the processor array are preferably arranged in a matrix consisting of rows and columns.

In one form of the invention, the processor array described above is included in a fabric structure,
The processor and / or sensor and / or actuator are arranged in the fabric structure,
The woven structure includes a conductive single fiber that connects processors, a conductive data transmission single fiber that connects processors, and a non-conductive single fiber.

  In the woven structure, the conductive single fibers may be adjusted so that the single fibers can be used to power multiple processors and / or sensors and / or actuators.

  In the above woven structure, the conductive data transmission single fiber has conductivity, and preferably has optical conductivity.

The actuator
・ Image forming elements,
・ Sound wave generating element, or
-It is preferable that it is set as at least one of the vibration generating elements.

  In the surface covering structure, the surface covering is preferably fixed to the woven structure.

  In a preferred surface covering structure, the surface covering is adhered to the fabric structure and / or laminated to the fabric structure and / or vulcanized.

The surface coating structure according to one aspect of the present invention is
・ Wall covering structure,
・ Floor covering structure or
・ It is formed as a ceiling covering structure.

  Further, in a certain surface covering structure, a fabric layer in which conductive wires are uniformly woven is applied to at least a partial region of the woven structure.

  Embodiments of the invention are shown in the drawings and are described in detail below.

  In the drawings, the same members are denoted by the same reference symbols.

  FIG. 1 is a diagram showing a fabric structure of the present invention as a coarse fabric having conductive single fibers and integrated microelectronic elements. In FIG. 1, four regions (a), (b), (c), and (d) are shown.

  FIG. 2 is a diagram showing a fabric structure according to an embodiment of the present invention, and shows a fabric structure in which a dark carpet is fixed in a partial region.

  FIG. 3 is a schematic diagram illustrating a processor array of one embodiment of the present invention provided in a woven structure.

  FIG. 4 is a schematic diagram illustrating a processor element according to an embodiment of the present invention.

  FIG. 5 is a schematic diagram of a processor array illustrating the problem of processor element failures.

  FIG. 6 is a schematic diagram illustrating a processor array of one embodiment of the present invention in which the processor elements of the processor array are driven synchronously in a predetermined manner.

  FIG. 1 shows a schematic diagram illustrating a processor array incorporated into a fabric structure 100 of one embodiment of the present invention.

  The fabric structure 100 of the present invention has a coarse woven fabric formed from non-conductive single fibers 101 as a basic structure. Furthermore, the woven structure 100 includes a conductive first single fiber 102 and a conductive second single fiber 107. The conductive first single fiber 102 is used as a grounding means for the microelectronic element 103 integrated in the fabric structure 100 as necessary. The conductive second single fiber 107 is used to supply power to the processor element 103 integrated in the woven structure 100.

  Furthermore, the woven structure 100 has two data transmission single fibers 104 having conductivity. These conductive data transmission monofilaments are used to transmit data from the integrated processor element 103 and to transmit data to the integrated processor element.

  The conductive single fibers 102 and 107 and the conductive data transmission single fibers 104 are preferably arranged in a square pattern in the woven fabric, and a square pattern of intersection points 105 is formed in the woven structure 100.

  The area of such an intersection is shown in FIG.

  Further, in the region of the intersection 105 shown in FIG. 1 b), the conductive single fibers 102, 107 and the conductive data transmission single fibers 104 are removed, so that a hole is formed in the woven structure 100. Is formed.

  In the area c) of FIG. 1, the processor element 103 is arranged in the hole of the fabric structure 100. In order to supply power to the processor element 103 and to provide a data transmission line for the processor element 103, the processor element 103 is connected with conductive single fibers 102 and 107 and a conductive data transmission single fiber 104. Has been.

  In the fabric structure 100 of the present invention, the processor element 103 is disposed at each intersection 105 between the conductive single fibers 102 and 107 and the conductive data transmission single fiber 104, and then reaches the processor element 103 from four sides. It is preferable to connect to the conductive single fibers 102 and 107 and the conductive data transmission single fiber 104.

  The processor element 103 can be connected to the conductive single fibers 102 and 107 and the conductive data transmission single fiber 104 through contact with each other through a flexible printed board, or by so-called wire bonding. it can. As an alternative, this contact may be made by gluing.

  The processor element enclosed in the area d) in FIG. 1 to insulate the connection area (contact point) between the processor element 103 and the conductive single fibers 110, 107 and the conductive data transmission single fiber 104. 103 and a protective material 106 for further providing mechanical strength and water resistance are schematically shown.

  The fabric structure 100 of the present invention includes one processor element 103 for each intersection 105. Such an “intelligent” fabric structure 100 is capable of forming a base layer or intermediate layer of coatings covering walls or floors, or other types of technical fibers.

  For example, it may be used as a layer of fiber concrete structure. The processor element 103 of the fabric structure 100 may be coupled to a plurality of various sensors and / or actuators. These may be, for example, an LED (light emitting diode), a display element, or a display device, and display information transmitted to the processor element 103 or display sensor data obtained by the processor element 103 as an interface processor. For transmission to the evaluation system.

  FIG. 2 shows one embodiment of a so-called intelligent carpet comprising the processor array of the present invention.

  In the lower right of FIG. 2 is shown an open basic woven fabric 200 in which conductive single fibers 102, 104 and 107 are woven in a square pattern. In the rough woven fabric 200, a processor element 103 is disposed at an intersection 105 between the conductive single fibers 102, 104, and 107. Thus, a regular pattern is formed that includes the processor elements 103 in contact with the supply and data lines on the four sides. The processor element 103 is further provided with an enclosure and a light emitting diode and / or a pressure sensor.

  Furthermore, the carpet is secured to the woven structure 100 as shown in the lower left of FIG.

  The fabric structure 100 of the present invention comprising an integrated processor element 103 having integrated microelectronic elements, in particular actuators such as sensors and / or small indicator lamps, is secured to various surface coatings. In essence, it is fully functional. Examples include non-conductive fabrics, carpet floor coverings, parquet, plastic, curtains, roll-up blinds, wallpaper, insulation mats, tent roofs, plaster layers, screed, and fiber concrete. It is done.

  This fixing is preferably performed by adhesion, lamination, or vulcanization. In order to avoid the occurrence of “electric smog” around the human body, a fabric in which conductive wires are uniformly woven may be used for the fabric structure surface of the present invention for shielding purposes. In this case, it should be noted that a specific area (eg, the area above the capacitive sensor) may not be covered by the shield.

  The fabric structure of the present invention with integrated microelectronic elements is preferably connected to a central control unit such as a personal computer at one end of the fabric structure.

  Using a simple algorithm, the processor elements themselves begin to be organized by the method described in US Pat. When a fabric structure with a network containing processor elements is connected, ie activated, a learning phase begins, after which each processor element knows its exact physical position in this pattern.

  In addition, the path of the data stream through this pattern is automatically formed. Here, sensor information or display information relating to the damaged area of the fabric structure is transmitted via this path. Damaged areas are detected and avoided by self-organization of the network. As a result, the network including the microelectronic module is operable even when the fabric structure 100 is cut into a predetermined shape for each application. Furthermore, the self-organization can save the trouble of manually installing the network including the microelectronic module.

  FIG. 3 is a schematic diagram illustrating a processor array 300 of the fabric structure 100 of FIGS. 1 and 2 with a plurality of processor elements 103 embedded in the fabric element as described above.

  As described with reference to FIG. 1, the processor element 103 is disposed at each of the intersections 105 of two fabric monofilaments that are disposed substantially perpendicular to each other.

  In 1st other embodiment, the monofilament for textiles itself shall have electroconductivity. In another embodiment of the present invention, when the textile monofilament is non-conductive, as described above, by providing the textile monofilament with the conductive wires 102, 104, 107, the electric signal is transmitted. Can be transmitted.

  The processor elements 103 arranged immediately adjacent to each other in the fabric structure 100 are connected to each other by conductive textile fibers or by electric wires 102, 104, 107, whereby electronic messages are exchanged.

  Furthermore, a processor serving as an entrance is provided as the interface processor 301. The interface processor is connected to at least one of the processor elements 103 of the fabric element 100 for writing messages to the processor array 300 and reading messages from the processor array. In addition, an evaluation system 302 coupled to the interface processor 301 is provided. The evaluation system 302 is configured as a personal computer that evaluates sensor data obtained from the sensor of the processor element 103 and transmitted from the processor array 100 via the interface processor 301. The evaluation system 302 performs, for example, statistical monitoring of data and threshold inspection.

  The processor of the processor element 103 determines its position with respect to the interface processor 102 through self-organization by a method as described in Patent Document 1.

  The processor group of the processor array 100 is arranged in a tree structure having different hierarchical levels with respect to the interface processor 301. In this topology, the hierarchy level is to be understood as a distance with respect to the message flow and is defined by the number of other processors located between the processor of interest and the portal processor.

  The processors in the processor array 300 are clocked to be synchronized by a wide area synchronous clock oscillator (not shown).

  FIG. 4 shows the structure of the processor element 103 in detail.

  As described above, the processor element 103 has four ports (a first port 401, a second port 402, a third port 403, and a fourth port 404). Each port has a first operating voltage terminal 401a, 402a, 403a, 404a for applying a first operating potential VDD and a second power supply terminal 401b, 402b, 403b, 404b (preferably, each port 401, 402, 403 and 404 have a ground terminal for applying a ground potential.

  Each first power supply terminal 401a, 402a, 403a, 404a (shown as an operating voltage terminal) of the processor element 103 is connected to each first power supply terminal of an adjacent processor element appropriately connected to this processor element 103. Has been.

  Similarly, each second power supply terminal 401b, 402b, 403b, 404b is connected to each second power supply terminal of a processor element that is locally located immediately adjacent thereto.

  In this embodiment of the invention, each second power supply terminal 401b, 402b, 403b, 404b is all connected to a meeting point or a common ring. With proper wiring, the diodes 401d, 402d, 403d, 404d ensure that the voltage is supplied to the processor 405 regardless of the ports 401, 402, 403, 404 to which the operating voltage is supplied.

  The first operating voltage terminals 401a, 402a, 403a, 404a and the second operating voltage terminals 401b, 402b, 403b, 404b corresponding to the first operating voltage terminals 401a, 402a, 403a, 404b together constitute a power source interface of the processor element 103.

  In this connection configuration, basically, a desired number of all ports can be provided in the processor element. Accordingly, a desired number of processor elements connected to and adjacent to the processor elements can be provided. That is, it should be pointed out that the present invention is not limited to the case where there are four ports, that is, the case where there are four adjacent processor elements.

  Further, the processor element 103 is provided with a microprocessor 405 and a current limiting unit 406.

  The processor element 103 further includes four diode arrays 401c, 402c, 403c, 404c that function as current valves and voltage valves, as can be seen from the figure. The diode arrays 401c, 402c, 403c, and 404c are respectively assigned to the ports 401, 402, 403, and 404 of the processor element 103, and the first terminals of the diode arrays 401c, 402c, 403c, and 404c correspond to the corresponding ones. The first power supply terminals 401a, 402a, 403a, and 404a are connected.

  In this regard, FIG. 4 shows that for simplicity of illustration of the present invention, only the lines related to the supply of power are shown, and the lines for transmitting data, similarly provided in the processor element 103, are not shown. Need to point out.

  Each diode array 401c, 402c, 403c, 404c includes diodes 401d, 402d, 403d, 404d, first switches 401e, 402e, 403e, 404e, and second switches 401f, 402f, 403f, 404f. .

  When each switch is appropriately set, the processor 405 is connected to each first power supply terminal 401a, 402a, 403a, 404a to which the first operating potential VDD is applied via each diode array 401c, 402c, 403c, 404c. The

  As an alternative to each of the diodes 401d, 402d, 403d, and 404d, a diode-connected transistor is used.

  In the processor 405, a short-circuit checking unit for checking whether or not there is an electrical short circuit for an adjacent processor element connected to each power supply terminal at each power supply terminal 401a, 402a, 403a, 404a to be tested. Is provided as a computer program.

  The computer program stored in and executed by the processor 405 is set so as to execute the following method.

  The following method is sequentially executed by an iterative method, that is, for all four first power supply terminals 401a, 402a, 403a, and 404a.

  The power supply voltages VDD and VSS are applied to the ports 401, 402, 403, and 404. That is, the above-described method is performed from a processor element coupled to an interface processor, and a check for electrical shorts is connected to each processor element step by step by all operable processor elements. It is executed repeatedly for adjacent processor elements.

  Thus, the selected port 401, 402, 403, 404 of one of the processor elements 103 is supplied with a power supply voltage while testing for electrical shorts. A power supply path is formed from the processor element.

  In another form of the invention, initially any desired processor element of the processor array is powered.

  The first processor element 103 is arranged partly immediately next to it, and is connected to the first processor element, and is connected to the first processor element 103 to supply power to three adjacent processor elements not yet supplied with power. To control.

  After power is supplied to the processor element, the processor element 103, and thus its processor 405, is powered only through the ports 401, 402, 403, 404 of the processor element to which power is supplied. The voltages VDD and VSS are supplied only to one first power supply terminal 401a, 402a, 403a, 404a to which a power supply voltage is supplied.

  In the present invention, a power supply voltage is applied to the processor 405 using the current limiting unit 406. The current limiting unit 406 is for limiting the current of the voltage supplied to the processor 405. That is, when the operating voltage VDD is applied to the second ports 401, 402, 403, 404 to which the operating voltage VDD has not yet been applied, the ports 401, 402, 403, 404 of the processor element 103 are similarly operated. A voltage VDD is applied and applied to adjacent processor elements through the port.

  If there is an electrical short in the electrical connection with the adjacent processor element in the port, the processor 405 detects this, and the processor 405 gradually disconnects from the power supply again, and this port is damaged. Mark as a damaged or defective port.

  As an alternative, the ground potential or the second operating voltage VSS may be applied to the ports 401, 402, 403, 404 of the processor element 103. In this case, the transistor included in the switch is configured as an NMOS field effect transistor. In this case, each diode 401d, 402d, 403d, 404d, each first switch 401e, 402e, 403e, 404e, and each second switch 401f, 402f, 403f, 404f is supplied with the ground potential or the second operating voltage VSS. Need to be inserted into the path.

  In the present invention, from which direction (that is, which port) each measurement node 401g, 402g, 403g, 404g between the first power supply terminal 401a, 402a, 403a, 404a and each diode array 401c, 402c, 403c, 404c In order to determine whether the operating voltage VDD is supplied (from 401, 402, 403, 404), the processor 405 can measure the voltage level. This is to close the first switches 401e, 402e, 403e, and 404e. By doing so, voltage drops that may occur in the diodes 401d, 402d, 403d, and 404d can be minimized. Or can be removed.

  After providing a power supply protected by the current limiting unit 406, the other ports 402, 403, 404 are subsequently examined for possible electrical shorts as described above.

  For this purpose, the second switches 401f, 402f, 403f, 404f are used.

  After this test phase, which can be said to be the initialization of each processor element for power supply, no electrical short circuit has occurred with each adjacent processor element (ie, each of the above adjacent processor elements). The first switches 401e, 402e, 403e, and 404e of the diode arrays 401c, 402c, 403c, and 404c determined to be closed are closed.

  In other embodiments, instead of providing a current limiting unit 406 in the center, a current limiting unit 406 is implemented in each diode array 401c, 402c, 403c, 404c. In this case, it is particularly preferable to set the second switches 401f, 402f, 403f, and 404f as current limit switches.

  It is desirable to implement these switches as switching elements (eg, relay contacts, field effect transistors, properly wired bipolar transistors, etc.).

  The above method is executed, and each processor element of the processor array performs a test on all ports 401, 402, 403, 404 connected to each adjacent processor element.

  Therefore, as described above, in the processor array, the power supply voltage network is automatically and continuously formed in a self-organized manner.

  When all ports 401, 402, 403, 404 of the processor element 103 are initialized after checking for electrical shorts, the processor element waits for another instruction. The other command is particularly a command related to transmission of an electronic message or display of information included in an electronic message by an image forming element (not shown) included in the processor element.

  After executing the configuration of the protected power supply in the processor array, the self-organization described in US Pat.

  If an electrical short on port 401, 402, 403, 404 is detected by processor 405, that port 401, 402, 403, 404 is marked as a defective port and the corresponding first switch 401e, 402e, 403e. , 404e are kept open (ie, not closed).

  As shown in FIG. 5, in the case of a defective processor element, the information to be displayed on each processor element 103 in the processor array by the image forming element and at least one image forming element (eg, , Light-emitting diode) information must be stored in the memory of the processor element 103.

  The interface processor configured as a personal computer in the present invention is stored in the processor element 103 based on the data supply point and the symbol to be displayed by the processor element 103 and the image forming element provided in the processor element 103. The pattern is calculated.

  As shown in FIG. 5, when a failure occurs in a processor element (in FIG. 5, the failed processor element is indicated by reference numeral 501), the routing paths need to be coupled by a routing branch.

  In FIG. 5, processor elements supplied with electronic messages are indicated by A and B. Further, it is shown that data to be displayed is supplied via a processor element indicated by C, D, and F. The processor elements indicated by C, D, and F also supply data to the processor element indicated by E.

  Generally, in FIG. 5 and FIG. 6, the processor elements of the processor array are indicated by circles.

  When displaying data, it should be noted that the data must be displayed by each imaging element of the processor array synchronously and simultaneously.

  In this embodiment, when an electronic message is supplied to the processor array by the interface processor, the interface processor may provide the electronic message supply point before supplying the electronic message to ensure that the information is displayed in time synchronization. The electronic message in the processor array that is sent to the routing path and each target processor element (the processor element that needs to display each piece of information contained in the message by its imaging element) based on the symbol displayed as The waiting time and the time for changing the output are calculated.

  In the present invention, the result of the calculation is given by a specific time output value specified in the time cycle. This is because the processor array is clocked to synchronize globally and electronic messages are transmitted from one processor element to the processor element located immediately next to it at one clock time. It is.

  For all displayed data, the time for which data is to be used at each processor element is calculated for each processor element in order to output the displayed information to the user at the correct time. This time data is calculated for all processor elements of the processor array and preloaded into the memory of the processor elements.

  To output the item of information, the interface processor sends a time code to the network (ie, processor array). The time code is transferred each time a new time code occurs.

  FIG. 6 shows how the time code is distributed to the processor array by the illustrated lines. Using the time codes shown in the processors A, B, C, and D, the outputs from the image forming elements in the processor elements A, B, C, and D are temporally “light-emitting diodes ON” at time T = 4. Set to synchronize.

  In the present embodiment shown in FIG. 6, the interval specified by the time cycle from the first processor element A to the interface processor is a three-hour cycle. The distance from the second processor element B to the interface processor is a two hour cycle. The distance from the processor element C to the interface processor is a 3 hour cycle, and the interval from the fourth processor element D to the interface processor is a 4 hour cycle.

  It is therefore necessary to wait for at least a four hour cycle before the information to be displayed simultaneously by the four processor elements A, B, C, D can be used in all of these processor elements.

  Only after the information is transmitted to the fourth processor element D is the information output by all four processor elements A, B, C, D.

  Thus, in order to reliably display information in time synchronization, an interrupt waiting time shorter than the required frame rate indicating the time interval from the displayed first image to the immediately following second image is assumed. There is a need.

  If the frame rate is 20 images per second, that is, if the frame repetition interval is 50 milliseconds, and if the processor array has a maximum of 256 × 256 processors, it depends on all the processors in the processor array Information supply, simultaneous control, and display can also be achieved by commercially available processors.

It is a figure which shows the fabric structure of this invention as a coarse fabric which has an electroconductive single fiber and the microelectronic element integrated. It is a figure which shows the textile structure of one Embodiment of this invention with which the carpet of the dark color is being fixed to the partial area | region. 1 is a schematic diagram illustrating a processor array of one embodiment of the present invention provided in a fabric structure. 1 is a schematic diagram illustrating a processor element of one embodiment of the present invention. Fig. 6 is a schematic diagram of a processor array showing a problem of processor element failure. 1 is a schematic diagram illustrating a processor array of one embodiment of the present invention in which processor elements of the processor array are driven synchronously in a predetermined manner.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Textile structure 101 Non-conductive single fiber 102 1st electrically conductive single fiber 103 Processor element 104 Conductive data transmission single fiber 105 Intersection 106 Protection 107 Second electrically conductive single fiber 200 Basic woven fabric 300 Processor Array 301 Interface processor 302 Evaluation system 401 1st port 402 2nd port 403 3rd port 404 4th port 401a 1st port 401b of 1st operating voltage terminal 1st port 401c of 2nd power supply terminal 1st port 401d of diode array Diode first port 401e first switch first port 401f second switch first port 401g measurement node first port 402a first operating voltage terminal second port 402b second power supply terminal second port 402c diode array Second port 4 2d diode second port 402e first switch second port 402f second switch second port 402g measurement node second port 403a first operating voltage terminal third port 403b second power supply terminal third port 403c diode array Third port 403d of diode Third port 403e of diode Third port 403f of first switch Third port 403g of second switch Measurement node Third port 404a Fourth port 404b of first operating voltage terminal Fourth of second power supply terminal Port 404c Diode Array Fourth Port 404d Diode Fourth Port 404e First Switch Fourth Port 404f Second Switch Fourth Port 404g Measurement Node Fourth Port 405 Processor 406 Current Limiting Unit 501 Damaged Processor Element A Processor Element
B Processor element
C processor element
D processor element
E Processor element
F processor element

Claims (19)

In a processor array having a plurality of processor elements,
Each processor element
At least one processor;
A plurality of power supply interfaces for transmitting power from a plurality of processor elements adjacent to the processor element; and a plurality of power supply interfaces for transmitting power to a plurality of processor elements adjacent to the processor element; ,
A plurality of power switches respectively assigned to each power interface, and can supply power to the power interface or not supply power to the power interface as desired. A power switch;
At least one short circuit test unit for sequentially checking whether an electrical short circuit has occurred at the power supply interface to the coupled adjacent processor elements;
A control unit configured to close each power switch and supply power to the power interface when a short circuit does not occur in the power interface.
At least to some extent, only processor elements located locally next to each other are connected to each other for exchanging electronic messages and for transmitting power,
Processor array. At least a portion of the processor element comprises a sensor and / or actuator coupled to the processor;
Sensor data and / or actuator data is transmitted as electronic messages between processor elements arranged adjacent to each other;
The processor array according to claim 1. The at least one short circuit inspection unit comprises a current limiting device;
The processor array according to claim 1 or 2. Each power switch is assigned a current limiting device,
The processor array according to claim 3. At least a part of the power switch is set as a power limit switch,
The processor array according to claim 4. The processor elements are arranged in a matrix consisting of rows and columns.
The processor array according to any one of claims 1 to 5. The processor array includes at least one interface processor that serves as a message interface of the processor array.
The processor array according to any one of claims 1 to 6. Sensor data and / or actuator data is transmitted as electronic messages via the interface processor.
The processor array according to claim 2 or 7. A fabric structure comprising the processor array according to any one of claims 1 to 8,
The processor and / or sensor and / or actuator are arranged in the fabric structure;
The fabric structure is
Conductive monofilaments connecting the processors together;
A conductive data transmission monofilament that couples the processors together;
A non-conductive monofilament,
have,
Woven structure. The conductive single fiber is
Configured to be used to supply power to the plurality of processors and / or sensors and / or actuators;
The woven structure according to claim 9. The conductive data transmission monofilament is conductive.
The woven structure according to claim 9 or 10. The conductive data transmission single fiber has optical conductivity.
The woven structure according to claim 9 or 10. The actuator is configured as at least one of an image forming element, a sound wave generating element, or a vibration generating element.
The textile structure according to any one of claims 9 to 12. A surface coating is fixed to the fabric structure according to any one of claims 6 to 10.
Surface covering structure. The surface coating is adhered to the fabric structure and / or laminated to the fabric structure and / or vulcanized to the fabric structure;
The surface covering structure according to claim 14. It is configured as a wall covering structure, floor covering structure, or ceiling covering structure,
The surface covering structure according to claim 14 or 15. A fabric layer in which conductive wires are uniformly woven is applied to at least a partial region of the fabric structure;
The surface covering structure according to any one of claims 14 to 16. At least one processor;
A plurality of power supply interfaces for transmitting power from a plurality of processor elements adjacent to the processor element; and a plurality of power supply interfaces for transmitting power to a plurality of processor elements adjacent to the processor element; ,
A plurality of power switches respectively assigned to each power interface, wherein the power switches can supply or not power each power interface as desired;
At least one short circuit test unit for sequentially testing whether an electrical short circuit has occurred at a power interface to adjacent coupled processor elements;
A control unit configured to close each power switch and supply power to the power supply interface when a short circuit has not occurred in the power supply interface;
A processor element comprising: A power transmission method between a plurality of processor elements disposed locally adjacent to each other,
Each processor element
At least one processor;
A plurality of power supply interfaces for transmitting power from a plurality of processor elements adjacent to the processor element; and a plurality of power supply interfaces for transmitting power to a plurality of processor elements adjacent to the processor element; ,
A plurality of power switches respectively assigned to each power interface, wherein the power switches can supply or not power each power interface as desired;
With
At least to some extent, for exchanging electronic messages and for transmitting power, only processor elements that are locally located next to each other are connected to each other, sensor data and / or actuators Data is transmitted as electronic messages between the processor elements,
A check is made on the power supply interface to determine whether an electrical short to an adjacent coupled processor element has occurred;
When there is no short circuit in the power interface, each power switch is closed so that power can be supplied to the power interface.
Power transmission method.

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