JP2007335617A - Designing method of semiconductor integrated circuit, and duty cycle improvement cell - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve a duty cycle without much change in layout in designing a semiconductor integrated circuit while an increase in area can be small. <P>SOLUTION: A duty cycle improvement cell is additionally connected with a wire which is specified to have its duty cycle deteriorated. In particular, when a standard cell is used, a gap space is used and a basic cell which is not used in a gate array is used to control a change in the whole layout to be a small partial change. The duty cycle improvement cell consists of a pull-down transistor for pulling up or down the wire which is specified to have its duty cycle deteriorated and an inverter for detecting a signal level of the wire and driving the transistor. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for designing a semiconductor integrated circuit and a duty ratio improving cell used directly for carrying out the design method.

  The signal waveform used in the digital circuit is often required to have a ratio (duty ratio) of the time width of the “H” level and the time width of the “L” level. This is particularly important for clock circuits.

  For example, a CMOS inverter is composed of a PMOS transistor 101 and an NMOS transistor 102 as shown in FIG. 5. If the balance between the transistors 101 and 102 is good, a signal with a duty ratio of 50% is input to the output side. Also, an inverted signal with a duty ratio of 50% can be obtained. However, in reality, it is difficult to completely match the driving capability of the PMOS transistor 101 and the NMOS transistor 102 constituting the CMOS inverter, and even when the data ratio of the input signal is 50%, the output The signal duty ratio often deviates from 50%. In addition, even if the deviation of the duty ratio in the single-stage inverter is slight, the duty ratio of the output signal becomes larger as the number of stages increases. Further, in a multi-input circuit such as a three-input NOR circuit including three PMOS transistors 111 to 113 and three NMOS transistors 114 to 116 shown in FIG. 6, the duty ratio is further deteriorated as compared with the inverter shown in FIG. Is strong.

  The reason why the duty ratio of the output signal waveform is deteriorated is that there is a difference between the transition time from “H” to “L” and the transition time from “L” to “H” on the output side of the cell. As shown in FIG. 7, the transition time and the difference therebetween become larger as the load becomes heavier. In FIG. 7, TpHL is a delay time of transition from “H” to “L”, and TpLH is a transition time from “L” to “H”.

Therefore, conventionally, proposals for adjusting the duty ratio have been made. For example, in Patent Document 1, as a variable buffer gate for adjusting a duty ratio, a plurality of PMOS transistors and a plurality of NMOS transistors are provided with drains commonly connected to an output side wiring, and the number of transistors operated by a switch circuit is set. What has been made possible is proposed. This generates a control signal according to the duty ratio of the output waveform, controls the switch circuit by the control signal, automatically adjusts the driving capability of the variable buffer gate, and maintains the duty ratio at 50%. It is a thing.
JP-A-4-371023

  However, this prior art variable buffer gate requires a circuit for generating a control signal, a switch circuit, and a number of transistors capable of obtaining sufficient driving capability for various loads. A large area is required. Therefore, providing such a variable buffer gate leads to an increase in the overall area of the semiconductor integrated circuit.

  Another object of the variable buffer gate of the prior art is to automatically adjust a deviation in duty ratio caused by fluctuations in power supply voltage and transistor characteristics after manufacturing. However, in an actual semiconductor integrated circuit, the deterioration of the duty ratio is not a problem only in a specific output circuit, and there is a possibility that the duty ratio is deteriorated at various places (wirings) in the circuit. Therefore, providing a variable buffer gate that requires a large area for all of the wirings that may cause the deterioration of the duty ratio leads to a significant increase in the area of the entire semiconductor integrated circuit, which is not realistic.

  Note that the duty ratio can be improved by changing the gate width ratio of the PMOS transistor and the NMOS transistor of the buffer that drives the wiring whose duty ratio has deteriorated. However, if the gate width ratio of the transistor is changed in this way, the layout may be greatly changed in the design of the semiconductor integrated circuit. If the layout is changed, the wiring needs to be changed, and the timing analysis needs to be performed again.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit design method and a duty ratio improving cell capable of improving a duty ratio without causing a layout change and minimizing an increase in area. That is.

To achieve the above object, a method for designing a semiconductor integrated circuit according to a first aspect of the present invention is to design a circuit to be configured in a semiconductor integrated circuit, and in the designed circuit, the duty ratio of a pulse signal is A wiring that deteriorates is identified, and a duty ratio improving cell is connected to the identified wiring.
According to a second aspect of the present invention, in the first aspect of the invention, the design of the wiring in which the duty ratio deteriorates is performed by designing a layout for configuring the designed circuit in the semiconductor integrated circuit. This is performed by evaluating the duty ratio of the pulse signal within the determined layout.
The invention according to claim 3 is the invention according to claim 2, wherein the duty ratio improving cell is connected to the designed circuit, and then the duty ratio improving cell is partially changed with respect to the designed layout. It arrange | positions.
The invention according to a fourth aspect is the invention according to the third aspect, wherein the layout design is performed by arranging a plurality of types of standard cells, and in the partial change, the layout is left between the standard cells arranged in the layout design. The duty ratio improving cell is disposed in the formed gap.
The invention according to claim 5 is the invention according to claim 3, wherein the layout design is performed by arranging wirings on a gate array, and the basic cell that is not used in the layout design is used in the partial change. Then, the duty ratio improving cell is formed.
According to a sixth aspect of the invention, in the invention according to any one of the first to fifth aspects, the duty ratio improving cell includes a transistor that pulls up or pulls down the specified wiring, and a signal level of the specified wiring. And an inverter for driving the transistor.
A duty ratio improving cell according to a seventh aspect of the present invention is a cell for connecting to a specific wiring in a semiconductor integrated circuit to improve a duty ratio of a signal of the wiring, and pulling up or pulling down the wiring. And a inverter for detecting the signal level of the specific wiring and driving the transistor.

  According to the present invention, since the duty ratio improving cell is connected to the wiring specified as the duty ratio is deteriorated, the area increase due to the connection of the duty ratio improving cell can be minimized. In particular, after layout design, it is possible to reliably identify a wiring whose duty ratio deteriorates. Further, if a standard cell is used, a gap space is used, and if a basic cell that is not used in the gate array is used, the entire layout need not be changed, or a slight partial change is required. At this time, the area of the entire cell does not increase or is small. Further, the duty ratio improving cell has a simple configuration in which the signal terminal is one terminal, and the layout change and the area increase can be further reduced.

  In the embodiment of the present invention, when designing a semiconductor integrated circuit, it is possible to improve the duty ratio deterioration, and after design or further layout, when a wiring whose duty ratio deteriorates can be identified. Then, a duty ratio improving cell is added and connected to the wiring. In order to make this possible, a duty ratio improving cell having a single terminal and a compact size is used so that connection does not cause a large change in the logic, layout, and timing of the circuit.

  The design of the semiconductor integrated circuit is as follows: (1) Circuit design (FE) → (2) Initial layout (BE) → (3) Timing analysis and circuit correction (FE) → (4) Layout part change (BE) → (5) The timing analysis procedure is performed, and the layout is completed when the timing analysis is OK. (3) and (4) are repeated several times as necessary. FE is a front end process, and BE is a back end process.

  Usually, in the timing analysis of (3) after the initial layout of (2), the duty ratio of each signal wiring is evaluated to identify the wiring in which the duty ratio deterioration occurs. Then, for the circuit data designed for the circuit of (1), the duty ratio improving cell is connected to the specified wiring, the circuit correction of (3) is performed, and the duty ratio improving cell is arranged (4 ) Change the layout part.

  For example, when designing with the standard cell method, a gap in which the standard cell is not laid out remains even after laying out the standard cell necessary for realizing the function of the semiconductor integrated circuit. Therefore, if a duty ratio improvement cell of a size that can be arranged in such a gap is prepared (as a kind of standard cell), the duty ratio improvement cell is additionally arranged without changing the layout already performed. It is possible to connect to the specified wiring.

  On the other hand, when designing with the gate array method, it is necessary to use a gate array in which basic cells of a certain shape are arranged and to arrange the wiring in the layout stage to realize the function of the semiconductor integrated circuit. A simple circuit. In this case, the basic cells that have not been used remain. Therefore, by forming a duty ratio improving cell using a basic cell that has not been used, the duty ratio improving cell is additionally arranged and connected to the specified wiring without changing the layout already performed. Is possible.

  However, there is a case where the wiring for which the duty ratio is desired to be improved may be specified at the circuit design stage (the layout is not performed so that the exact load is not known, but the timing analysis is performed assuming the load). In that case, the layout is performed after the duty ratio improving cell is connected in advance.

  As described above, in this embodiment, a wiring whose duty ratio is deteriorated (to be improved) is specified, and a duty ratio improving cell is connected to the wiring. Accordingly, an unnecessary duty ratio improving cell is not added, and the layout change and the area increase can be minimized. In particular, when a duty ratio improving cell having a one-terminal configuration is used, there is no change in the logic of the circuit. Therefore, it is possible to connect without changing the wiring whose duty ratio is to be improved, and the layout change can be further reduced. Further, by utilizing the gap between the standard cells and the unused basic cells of the gate array, it becomes possible to arrange the duty ratio improving cells without causing a layout change or an increase in area.

  FIG. 1 is a circuit diagram of the first duty ratio improving cell 10A. When a large delay occurs when the voltage of the wiring 30 on the output side of the circuit cell 20 changes from “L” to “H”, compared to when the voltage changes from “H” to “L”, the power supply terminal VDD The duty ratio improving cell 10 </ b> A is connected between the wiring 30. The duty ratio improving cell 10A includes an inverter 11 and a PMOS transistor 12. When the voltage of the wiring 30 changes from “L” to “H”, the PMOS transistor 12 is turned on to forcibly set the voltage of the wiring 30. The voltage is raised to the power supply terminal VDD to improve the duty ratio. Note that when the voltage of the wiring 30 changes from “H” to “L”, the PMOS transistor 12 is turned off, and the wiring 30 is not affected.

  FIG. 2 is a circuit diagram of the second duty ratio improving cell 10B. When a large delay occurs when the voltage of the wiring 30 on the output side of the circuit cell 20 changes from “H” to “L” as compared to when the voltage changes from “L” to “H”, the ground terminal GND The duty ratio improving cell 10B is connected to the wiring 30. The duty ratio improving cell 10B includes an inverter 13 and an NMOS transistor 14, and when the voltage of the wiring 30 changes from “H” to “L”, the NMOS transistor 14 is turned on to forcibly set the voltage of the wiring 30. The voltage is reduced to the voltage of the ground terminal GND to improve the duty ratio. Note that when the voltage of the wiring 30 transitions from “L” to “H”, the NMOS transistor 14 is turned off and the wiring 30 is not affected.

  The duty ratio improving cells 10A and 10B shown in FIGS. 1 and 2 are not limited to one. As these duty ratio improving cells 10A and 10B are connected in parallel to the wiring 30 whose duty ratio is to be improved, the duty ratio improving effect becomes higher. Therefore, the number of parallel connections may be determined with a duty ratio of 50% as a target.

  FIG. 3 (a) is an explanatory diagram of the basic cell 40 used when these duty ratio improving cells 10A and 10B are formed of a gate array. 41 and 42 are PMOS transistors, and 43 and 44 are NMOS transistors. The duty ratio improvement cell 10A is configured by wiring the PMOS transistors 41 and 42 and the NMOS transistor 43 as shown in FIG. 3B, and the duty ratio improvement cell 10B is configured by connecting the PMOS transistor 41 and the NMOS transistors 43 and 44 in FIG. Wire and configure as shown in c).

  FIG. 4 is an explanatory diagram of a semiconductor integrated circuit 70 composed of standard cells. This is a case where the wiring 30 is arranged from the output side of the circuit cell 20 to the input side of the circuit cell 50. As shown in the enlarged view on the right, the duty ratio improving cell 10 </ b> A (or 10 </ b> B) is arranged in the gap 60 near the wiring 30. Here, two duty ratio improving cells 10 </ b> A are connected in parallel to the wiring 30. As shown in FIG. 1 and FIG. 2, the duty ratio improving cells 10A and 10B have a one-terminal configuration (one signal terminal for connecting to the wiring 30 except for a terminal connected to VDD or GND). Have only). Therefore, the circuit logic is not affected, and the wiring 30 can be connected without change. Further, the cell is a compact cell composed of only three MOS transistors, and can be easily added to the semiconductor integrated circuit 70 and has a high degree of freedom in arrangement, so that the layout and timing are not greatly affected.

It is a circuit diagram of the 1st duty ratio improvement cell of the example of the present invention. It is a circuit diagram of the 2nd duty ratio improvement cell of the Example of this invention. It is explanatory drawing of the basic cell of a gate array. It is explanatory drawing of the layout which has arrange | positioned the duty improvement cell on the semiconductor integrated circuit comprised by the standard cell. It is a circuit diagram of the CMOS inverter for duty ratio explanation. It is a circuit diagram of a 3-input NOR circuit for explaining a duty ratio. FIG. 6 is a characteristic diagram showing the relationship between transition delay time and load.

Explanation of symbols

10A: first duty ratio improving cell 10B: second duty ratio improving cell 20: circuit cell 30: wiring 40: basic cell 50: circuit cell 60: gap 70: semiconductor integrated circuit

Claims (7)

  A circuit to be configured in a semiconductor integrated circuit is designed, a wiring in which the duty ratio of a pulse signal deteriorates is specified in the designed circuit, and a duty ratio improving cell is connected to the specified wiring. A method for designing a semiconductor integrated circuit.   Specifying the wiring whose duty ratio deteriorates, designing a layout for configuring the designed circuit in the semiconductor integrated circuit, and evaluating the duty ratio of the pulse signal in the designed layout The method of designing a semiconductor integrated circuit according to claim 1, wherein:   3. The semiconductor integrated circuit according to claim 2, wherein the duty ratio improving cell is connected to the designed circuit, and then the duty ratio improving cell is arranged in a partial change to the designed layout. Circuit design method.   The layout design is performed by arranging a plurality of types of standard cells, and in the partial change, the duty ratio improving cells are arranged in a gap left between the standard cells arranged in the layout design. A method for designing a semiconductor integrated circuit according to claim 3.   The layout design is performed by arranging wiring on a gate array, and the duty ratio improving cell is formed by using a basic cell that is not used in the layout design in the partial change. The method for designing a semiconductor integrated circuit according to claim 3.   2. The duty ratio improving cell includes a transistor that pulls up or down the specified wiring, and an inverter that drives the transistor by detecting a signal level of the specified wiring. 6. A method for designing a semiconductor integrated circuit according to any one of items 1 to 5. A cell for connecting to a specific wiring in a semiconductor integrated circuit and improving the duty ratio of a signal of the wiring,
A duty ratio improving cell comprising: a transistor that pulls up or pulls down the wiring; and an inverter that detects a signal level of the specific wiring and drives the transistor.

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