JP2007335432A - Semiconductor device and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a vertical semiconductor device having a back electrode formed on the backside of a silicon substrate in which recesses (pits) are reduced in the backside of the silicon substrate. <P>SOLUTION: A collector electrode 20 has a first conductive layer 28, a second conductive layer 26, and a third conductive layer 24 formed sequentially from the backside of a silicon substrate 30. The first conductive layer 28 contains aluminum and silicon. The second conductive layer 26 contains titanium and has a mixture layer 26b further containing silicon or nitrogen at a part including an interface which touches at least the first conductive layer 28. The third conductive layer 24 contains nickel. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a vertical semiconductor device in which a back electrode is formed on the back surface of a silicon substrate and a method for manufacturing the same. The vertical semiconductor device here refers to a device in which a pair of main electrodes are formed separately on the front surface and the back surface of a silicon substrate.

  The semiconductor device includes a silicon substrate in which a plurality of semiconductor regions are formed. For example, semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and diodes can be created by devising the shape, positional relationship, impurity concentration, etc. of each semiconductor region. The vertical semiconductor device includes a back electrode formed on the back surface of the silicon substrate. In the case of a vertical IGBT, a collector region containing p-type impurities is formed on the back surface of a silicon substrate, and a collector electrode is formed on the back surface of the silicon substrate.

  Patent Documents 1 and 2 disclose a collector electrode having a plurality of conductive layers. This type of collector electrode includes a first conductive layer, a second conductive layer, and a third conductive layer in order from the back surface of the silicon substrate. The first conductive layer contains aluminum. The second conductive layer contains titanium. The third conductive layer contains nickel. The first conductive layer is used to improve the contact property with the collector region. The second conductive layer is used to improve the adhesion between the first conductive layer and the third conductive layer and to prevent nickel in the third conductive layer from entering the first conductive layer. The third conductive layer is used to improve the adhesion with the solder.

Japanese Patent Laid-Open No. 10-163467 JP 2003-59860 A

In this type of semiconductor device, when a heat load for melting the solder is applied to the collector electrode, a part of the silicon on the back surface of the silicon substrate moves to the first conductive layer, and a recess (pit) is formed on the back surface of the silicon substrate. ) Occurs in large quantities. In order to avoid this phenomenon, a device for introducing silicon into the first conductive layer is also known. However, even if the first conductive layer contains silicon, a phenomenon in which a part of silicon on the back surface portion of the silicon substrate moves to the first conductive layer cannot be avoided, and a depression ( A lot of pits occur.
The present inventors have studied in detail about this type of back electrode, and have found that silicon is distributed in a high concentration near the interface between the first conductive layer and the second conductive layer. This local distribution is presumed to be because silicon contained in the first conductive layer is firmly bonded to titanium of the second conductive layer. That is, it is considered that silicon contained in the first conductive layer has moved to the interface with the second conductive layer. When silicon contained in the first conductive layer moves to the interface with the second conductive layer, the silicon concentration on the side in contact with the silicon substrate in the first conductive layer decreases. The phenomenon that the pits are formed on the back surface of the silicon substrate is that a part of the silicon on the back surface of the silicon substrate moves to the first conductive layer in order to compensate for the decrease in the silicon concentration of the first conductive layer. It is guessed. The present inventors have succeeded in creating the present invention based on the above-mentioned new findings.
The present invention provides a semiconductor device in which a recess (pit) is unlikely to be generated on the back surface of a silicon substrate, and a method for manufacturing the same.

In the present invention, by suppressing the silicon contained in the first conductive layer from being combined with titanium in the second conductive layer, the silicon concentration on the side of the first conductive layer in contact with the silicon substrate is reduced. To suppress the formation of a pit in the back surface of the silicon substrate. In order to suppress bonding of silicon and titanium, the second conductive layer includes a mixed layer further including silicon or nitrogen at least in a portion including an interface in contact with the first conductive layer. The titanium in the mixed layer is previously bonded to silicon or nitrogen. Therefore, even if a thermal load is applied to the back electrode, the silicon contained in the first conductive layer is suppressed from being combined with the titanium contained in the second conductive layer. Thereby, the silicon concentration on the side in contact with the silicon substrate in the first conductive layer is kept high, and it is possible to suppress the formation of depressions (pits) in the back surface of the silicon substrate.
In addition, the mixed layer should just be formed in the part including the interface with a 1st conductive layer at least among 2nd conductive layers. The mixed layer may be formed in a dispersed state in a plane orthogonal to the thickness direction of the silicon substrate. Even in this case, it is possible to suppress the formation of depressions (pits) in the back surface portion of the silicon substrate as compared with the case where there is no mixed layer. Further, the entire second conductive layer may contain silicon or nitrogen. That is, the mixed layer may be formed over the entire second conductive layer.

The present invention can be embodied in a vertical semiconductor device in which a back electrode is formed on the back surface of a silicon substrate. The back electrode of this invention is equipped with the 1st conductive layer, the 2nd conductive layer, and the 3rd conductive layer in order from the back surface of the silicon substrate. The first conductive layer contains aluminum and silicon. The second conductive layer includes titanium, and has a mixed layer further including silicon or nitrogen in a portion including at least an interface in contact with the first conductive layer. The third conductive layer contains nickel.
The mixed layer of the second conductive layer suppresses bonding of silicon contained in the first conductive layer with titanium contained in the second conductive layer. Thereby, since the silicon concentration on the side in contact with the silicon substrate in the first conductive layer can be maintained high, it is possible to suppress the formation of pits on the back surface of the silicon substrate.

When the mixed layer of the second conductive layer contains silicon and titanium, the silicon / titanium atomic ratio of the mixed layer is preferably 0.3 to 2.0.
When the atomic ratio exceeds 0.3, it is possible to effectively suppress silicon contained in the first conductive layer from being bonded to titanium contained in the second conductive layer. When the atomic ratio is 2.0, silicon is saturated with respect to titanium. If the atomic ratio is in the range of 0.3 or more, it is preferably larger. It can suppress more that the silicon contained in the 1st conductive layer couple | bonds with the titanium contained in the 2nd conductive layer.

When the mixed layer of the second conductive layer contains nitrogen and titanium, the nitrogen / titanium atomic ratio of the mixed layer is preferably 0.5 to 1.0.
When the atomic ratio exceeds 0.5, it is possible to effectively suppress the silicon contained in the first conductive layer from being bonded to titanium contained in the second conductive layer. The state where the atomic ratio is 1.0 is a state where nitrogen is saturated with respect to titanium. If the atomic ratio is in the range of 0.5 or more, it is preferably larger. It can suppress more that the silicon contained in the 1st conductive layer couple | bonds with the titanium contained in the 2nd conductive layer.

The present invention can be embodied in a vertical IGBT having a collector region containing a p-type impurity on the back surface of a silicon substrate and having a collector electrode formed on the back surface of the silicon substrate. The collector electrode of this invention is equipped with the 1st conductive layer, the 2nd conductive layer, and the 3rd conductive layer in order from the back surface of the silicon substrate. The first conductive layer contains aluminum and silicon. The second conductive layer includes titanium, and has a mixed layer further including silicon or nitrogen in a portion including at least an interface in contact with the first conductive layer. The third conductive layer contains nickel.
If a depression (pit) is formed in the collector region of the IGBT, the characteristics of the IGBT are significantly deteriorated. Therefore, when the technique of the present invention is used for an IGBT, an extremely useful effect can be exhibited.

The present invention can provide a method of manufacturing a vertical semiconductor device in which a back electrode is formed on the back surface of a silicon substrate. The manufacturing method of the present invention includes a first step of forming a first conductive layer containing aluminum and silicon on the back surface of a silicon substrate using a sputtering method. The present invention further includes a second step of forming a second conductive layer containing titanium on the first conductive layer using a sputtering method. The present invention further includes a third step of forming a third conductive layer containing nickel on the second conductive layer using a sputtering method. The second step of the present invention is characterized in that a mixed layer further containing silicon or nitrogen is formed at least in a portion including an interface in contact with the first conductive layer.
In the above manufacturing method, at least in the initial stage of the second step, the second conductive layer is formed while further supplying silicon or nitrogen in addition to titanium, whereby the mixed layer containing titanium and silicon or titanium and nitrogen is formed. Can be formed. By using the above manufacturing method, the semiconductor device of the present invention can be obtained.

  According to the present invention, it is possible to provide a semiconductor device in which depressions (pits) are hardly generated on the back surface portion of the silicon substrate. The present invention further provides a method of manufacturing such a semiconductor device.

The features of the present invention are listed.
(First Embodiment) The semiconductor device of the present invention includes an IGBT, a MOSFET, a diode, a MOS thyristor, a Schottky diode, and the like.
(2nd form) When a semiconductor device is IGBT, it is preferable that the thickness of a collector area | region is adjusted to 0.1-1.0 micrometer. A semiconductor device having this type of collector region can reduce loss during switching. Further, in a semiconductor device having such a thin collector region, a very useful effect is exhibited by providing the second conductive layer having a mixed layer.

  FIG. 1 schematically shows a cross-sectional view of the main part of the semiconductor device 10. The semiconductor device 10 is a punch-through (PT) IGBT. As will be described later in the manufacturing method, the semiconductor device 10 has a thin plate structure formed using a Raw wafer. In FIG. 1, the reference numerals of the repeated structures are omitted for clarity of illustration.

  The semiconductor device 10 includes a collector electrode 20 on the back surface of the silicon substrate 30. The collector electrode 20 includes a first conductive layer 28, a second conductive layer 26, and a third conductive layer 24 in order from the back surface of the silicon substrate 30. The second conductive layer 26 separates the first conductive layer 28 and the third conductive layer 24. The third conductive layer 24 is covered with a covering layer 22 containing gold (Au).

The first conductive layer 28 contains aluminum and silicon. The second conductive layer 26 includes a mixed layer 26b formed on the first conductive layer 28 side and an unmixed layer 26a formed on the third conductive layer 24 side. The mixed layer 26b contains titanium and silicon. The unmixed layer 26a contains titanium. The second conductive layer 26 mainly contains titanium. The mixed layer 26b is distinguished from the non-mixed layer 26a in that it contains silicon in addition to titanium. The mixed layer 26 b is formed in a portion of the second conductive layer 26 including at least an interface in contact with the first conductive layer 28. The third conductive layer 24 contains nickel.
The first conductive layer 28 is used to improve the contact property with the collector region 32. The second conductive layer 26 is used to improve the adhesion between the first conductive layer 28 and the third conductive layer 24 and to prevent nickel in the third conductive layer 24 from entering the first conductive layer 28. . The third conductive layer 24 is used to improve the adhesiveness with the solder. The coating layer 22 is used to improve the wettability with the solder.

The semiconductor device 10 is constituted by a plurality of semiconductor regions formed on the silicon substrate 30. A collector region 32 containing a p-type impurity (typically boron) at a high concentration is formed on the back surface of the silicon substrate 30. The impurity concentration of the collector region 32 is generally adjusted to 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ⁻³ . The thickness 32a of the collector region 32 is generally adjusted to 0.1 to 0.8 μm. The impurity concentration and thickness 32a of the collector region 32 are preferably adjusted so that the amount of holes supplied in the ON state is reduced. If the amount of holes supplied is small, loss during switching can be reduced. If it is said numerical range, the amount of holes supplied can be decreased.

A buffer region 34 containing an n-type impurity (typically phosphorus) at a high concentration is formed on the collector region 32. The impurity concentration of the buffer region 34 is generally adjusted to 1 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ⁻³ . The thickness of the buffer region 34 is generally adjusted to 0.2 to 0.6 μm. The buffer region 34 stops the depletion layer extending from the pn interface between the body region 38 and the drift region 36 from extending when the semiconductor device 10 is turned off, and prevents the depletion layer from reaching the collector region 32. .

A drift region 36 containing an n-type impurity (typically phosphorus) at a low concentration is formed on the buffer region 34. The impurity concentration of the drift region 36 is generally adjusted to 1 × 10 ¹³ to 1 × 10 ¹⁵ cm ⁻³ . The thickness of the drift region 36 is generally adjusted to 70 to 160 μm. The thickness of the drift region 36 is adjusted according to the breakdown voltage required for the semiconductor device 10.

A body region 38 containing a p-type impurity (typically boron) is formed on the drift region 38. The impurity concentration of the body region 38 is generally adjusted to 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ . The thickness of the body region 38 is generally adjusted to 1.5 to 4.0 μm.

On the surface portion of the body region 38, an emitter region 42 containing an n-type impurity (typically phosphorus) at a high concentration is selectively formed. Emitter region 42 is separated from drift region 36 by body region 38. The impurity concentration of the emitter region 42 is generally adjusted to 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ .

  The semiconductor device 10 includes a trench gate electrode 46. The trench gate electrode 46 reaches the drift region 36 from the surface of the body region 38. The trench gate electrode 46 is opposed to the body region 38 that separates the emitter region 42 and the drift region 36 through the gate insulating film 44. Polysilicon is used for the trench gate electrode 46. Silicon oxide is used for the gate insulating film 44.

  On the body region 38, an emitter electrode 52 containing aluminum is formed. The emitter electrode 52 is electrically connected to the body region 38 and the emitter region 42. The emitter electrode 52 and the trench gate electrode 46 are separated by an interlayer insulating film 48.

Here, for the sake of comparison, FIG. 5 schematically shows a cross-sectional view of a main part of a conventional semiconductor device 100. The same components as those of the semiconductor device 10 in FIG. The second conductive layer 126 of the conventional semiconductor device 100 is composed of only one layer. The second conductive layer 126 of the conventional semiconductor device 100 contains only titanium. Therefore, silicon is distributed at a high concentration in the vicinity of the interface 126 c between the first conductive layer 28 and the second conductive layer 126. This local distribution indicates that when a heat load for melting the solder is applied to the collector electrode 120, the silicon contained in the first conductive layer 28 moves to the interface 126 c, and the titanium of the second conductive layer 126 is firmly attached. This is presumed to be due to bonding (silicide reaction). For this reason, the silicon concentration on the side in contact with the silicon substrate 30 in the first conductive layer 28 decreases. In order to compensate for the decrease in the silicon concentration, a part of the silicon on the back surface of the silicon substrate 30 moves to the first conductive layer 28. As a result, in the conventional semiconductor device 100, a large amount of depressions (pits) are generated on the back surface of the silicon substrate 30. The height of the depression (pit) may reach 0.2 to 0.8 μm.
In particular, in the case of the semiconductor device 100 having a thin plate structure, the generation of a depression (pit) becomes a big problem. In order to reduce the loss at the time of switching, it is desirable to adjust the thickness 32a of the collector region 32 to be thinner than 1 μm. However, in the case of such a thin collector region 32, a recess (pit) passes through the collector region 32 and reaches the buffer region 34, and the back electrode 120 and the buffer region 34 are short-circuited. When the back electrode 120 and the buffer region 34 are short-circuited, the breakdown voltage of the semiconductor device 100 is rapidly deteriorated. For this reason, in the case of the semiconductor device 100 having a thin plate structure, it is extremely useful to take measures against the occurrence of pits.

  In the semiconductor device 10 of FIG. 1, the second conductive layer 26 has a mixed layer 26b. The mixed layer 26b contains titanium and silicon. For this reason, in the mixed layer 26b, titanium and silicon are bonded in advance. Therefore, even if a thermal load when melting the solder is applied to the collector electrode 20, the silicide reaction in which silicon contained in the first conductive layer 28 is bonded to titanium in the second conductive layer 26 is not promoted. Therefore, the phenomenon that the silicon of the first conductive layer 28 moves is suppressed, and the silicon concentration on the silicon substrate 30 side of the first conductive layer 28 is kept high. As a result, the phenomenon that the silicon of the silicon substrate 30 moves to the first conductive layer 28 is also suppressed, so that it is possible to suppress the formation of depressions (pits) on the back surface of the silicon substrate 30.

Other features of the semiconductor device 10 will be described.
(1) The silicon / titanium atomic ratio of the mixed layer 26b is preferably 0.3 to 2.0. When the atomic ratio exceeds 0.3, it is possible to effectively suppress the silicon contained in the first conductive layer 28 from being bonded to titanium contained in the second conductive layer 26. That is, the silicide reaction can be effectively suppressed. When the atomic ratio is 2.0, silicon is saturated with respect to titanium. If the atomic ratio is in the range of 0.3 or more, the larger one is desirable. The silicon contained in the first conductive layer 28 can be further suppressed from bonding with titanium contained in the second conductive layer 26.
(2) The mixed layer 26b may contain nitrogen instead of silicon. In this case, the nitrogen / titanium atomic ratio of the mixed layer 26b is preferably 0.5 to 1.0. When the atomic ratio exceeds 0.5, it is possible to effectively suppress the silicon contained in the first conductive layer 28 from being bonded to the titanium contained in the second conductive layer 26. That is, the silicide reaction can be effectively suppressed. The state where the atomic ratio is 1.0 is a state where nitrogen is saturated with respect to titanium. If the atomic ratio is in the range of 0.5 or more, the larger one is desirable. The silicon contained in the first conductive layer 28 can be further suppressed from bonding with titanium contained in the second conductive layer 26.

(Manufacturing method of the semiconductor device 10)
Next, a method for manufacturing the semiconductor device 10 will be described with reference to FIGS.
First, as shown in FIG. 2, a silicon substrate 30 containing n-type impurities at a low concentration is prepared, and various structures are formed on the surface portion of the silicon substrate 30. A raw wafer is used for the silicon substrate 30.
Specifically, the following steps are provided. First, using ion implantation technology, boron is introduced into the surface portion of the silicon substrate 30 to form the body region 38. A region other than the body region 38 in the silicon substrate 30 becomes a drift region 36. Next, using the ion implantation technique, phosphorus is selectively introduced into the surface portion of the body region 38 to form the emitter region 42. Next, a trench reaching the drift region 36 through the body region 38 is formed by using a lithography technique and an etching technique. Next, a silicon oxide film is coated on the surface of the silicon substrate 30 and the inner wall of the trench using a CVD (Chemical Vapor Deposition) method. Further, using the CVD method, polysilicon is formed on the silicon oxide film, and the trench is filled with polysilicon. Next, using the lithography technique and the etching technique, the silicon oxide film and the polysilicon formed on the surface of the silicon substrate 30 are removed so that the silicon oxide film and the polysilicon formed in the trench are left. . As a result, a gate oxide film 44 and a trench gate electrode 46 are formed in the trench. Next, an interlayer insulating film 48 and an emitter electrode 52 are formed on the silicon substrate 30. Through these steps, various structures can be formed on the surface portion of the silicon substrate 30.

  Next, as shown in FIG. 3, the thickness of the silicon substrate 30 is adjusted by polishing from the back surface of the silicon substrate 30. For example, when the breakdown voltage of the semiconductor device 10 is required to be 1200 V, the thickness of the silicon substrate 30 is adjusted to about 150 μm.

Next, as shown in FIG. 4, a buffer region 34 and a collector region 32 are formed on the back surface of the silicon substrate 30 by using an ion implantation technique. Specifically, phosphorus is implanted toward the back surface of the silicon substrate 30 using a double charge with an acceleration voltage of 160 keV and a dose of 5 × 10 ¹³ cm ⁻² . Further, boron is implanted toward the back surface of the silicon substrate 30 under the conditions of an acceleration voltage of 25 keV and a dose of 3 × 10 ¹⁴ cm ⁻² . Thereafter, the introduced phosphorus and boron are activated using a laser heat treatment method to form the buffer region 34 and the collector region 32. The buffer region 34 is formed with a thickness of approximately 0.2 μm. The collector region 32 is formed with a thickness of approximately 0.2 μm.

Next, the first conductive layer 28, the second conductive layer 26, the third conductive layer 24, and the coating film 22 are sequentially formed on the back surface of the silicon substrate 30 using a sputtering method. Thereby, the collector electrode 20 is formed on the back surface of the silicon substrate 30, and the semiconductor device 10 shown in FIG. 1 is obtained.
Specifically, first, a substance having an atomic ratio of silicon to aluminum of 1: 1 is selected as a target, and the first conductive layer 28 is formed on the back surface of the silicon substrate 30 while keeping the temperature of the silicon substrate 30 at 400 ° C. or lower. It is formed with a thickness of approximately 400 nm. Next, a material having an atomic ratio of silicon to titanium of 2: 1 is selected as a target, and while maintaining the temperature of the silicon substrate 30 at 400 ° C. or lower, the mixed layer 26b is formed on the first conductive layer 28 to approximately 20 to 100 nm. Form with thickness. Next, titanium is selected as a target, and the non-mixed layer 26a is formed with a thickness of approximately 200 nm on the mixed layer 26b while keeping the temperature of the silicon substrate 30 at 400 ° C. or lower. Next, nickel is selected as a target, and the third conductive layer 24 is formed with a thickness of approximately 700 nm on the second conductive layer 26 while keeping the temperature of the silicon substrate 30 at room temperature. Next, gold (Au) is selected as a target, and the covering layer 22 is formed with a thickness of approximately 100 nm on the third conductive layer 24 while keeping the temperature of the silicon substrate 30 at 400 ° C. or lower. Thereafter, heat treatment at 350 to 450 ° C. is performed as necessary. Thereby, the contact resistance between the first conductive layer 28 and the collector region 32 is reduced, and the contact characteristics are improved.
Through these steps, the semiconductor device 10 shown in FIG. 1 can be obtained.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

The principal part sectional drawing of the semiconductor device of an Example is shown typically. A manufacturing process of a semiconductor device of an example is shown (1). The manufacturing process of the semiconductor device of an Example is shown (2). The manufacturing process of the semiconductor device of an Example is shown (3). The principal part sectional drawing of the conventional semiconductor device is shown typically.

Explanation of symbols

20: collector electrode 22: coating layer 24: third conductive layer 26: second conductive layer 26a: unmixed layer 26b: mixed layer 28: first conductive layer 30: silicon substrate 32: collector region 34: buffer region 36: drift Region 38: Body region 42: Emitter region 44: Gate insulating film 46: Trench gate electrode 48: Interlayer insulating film 52: Emitter electrode

Claims (7)

It is a vertical semiconductor device in which a back electrode is formed on the back surface of a silicon substrate,
The back electrode, in order from the back surface of the silicon substrate, includes a first conductive layer, a second conductive layer, and a third conductive layer,
The first conductive layer contains aluminum and silicon,
The second conductive layer includes titanium, and has a mixed layer further including silicon or nitrogen in a portion including at least an interface in contact with the first conductive layer.
The third conductive layer is a semiconductor device containing nickel.   2. The semiconductor device according to claim 1, wherein the mixed layer of the second conductive layer contains silicon and titanium, and the atomic ratio of silicon / titanium in the mixed layer is 0.3 to 2.0.   2. The semiconductor device according to claim 1, wherein the mixed layer of the second conductive layer contains nitrogen and titanium, and the nitrogen / titanium atomic ratio of the mixed layer is 0.5 to 1.0. A vertical IGBT having a collector region containing a p-type impurity on the back surface of the silicon substrate, and a collector electrode formed on the back surface of the silicon substrate;
The collector electrode includes, in order from the back surface of the silicon substrate, a first conductive layer, a second conductive layer, and a third conductive layer.
The first conductive layer contains aluminum and silicon,
The second conductive layer includes titanium, and has a mixed layer further including silicon or nitrogen in a portion including at least an interface in contact with the first conductive layer.
The third conductive layer is an IGBT containing nickel.   5. The IGBT according to claim 4, wherein the mixed layer of the second conductive layer contains silicon and titanium, and the atomic ratio of silicon / titanium in the mixed layer is 0.3 to 2.0.   The IGBT according to claim 4, wherein the mixed layer of the second conductive layer contains nitrogen and titanium, and the atomic ratio of nitrogen / titanium in the mixed layer is 0.5 to 1.0. A method of manufacturing a vertical semiconductor device in which a back electrode is formed on the back surface of a silicon substrate,
A first step of forming a first conductive layer containing aluminum and silicon on the back surface of the silicon substrate using a sputtering method;
A second step of forming a second conductive layer containing titanium on the first conductive layer using a sputtering method;
A third step of forming a third conductive layer containing nickel on the second conductive layer using a sputtering method;
In the second step, a mixed layer further including silicon or nitrogen is formed in a portion including at least an interface in contact with the first conductive layer.

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