JP2007334416A - Image processor and image processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive and simple countermeasure against an unwanted noise emission (EMI countermeasure). <P>SOLUTION: An image processor includes an image processing circuit and an image data output circuit, etc., for each color or each beam when outputting image data to a printer engine in a printer controller transferring the image data to the engine to print images after forming the image data. The processor has a means for generating operation clocks in which each phase of the operation clocks to operate the processing circuit and the output circuit is shifted and uses the operation clocks. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an image processing apparatus, an image processing method, and a program, and more particularly to a technique suitable for use in efficiently processing image data.

  In recent years, in image forming apparatuses such as printers and copiers, particularly in image forming apparatuses such as electrophotographic color printers and color copiers, high speed and high resolution are remarkable. In order to efficiently process a large amount of image data with high speed and high resolution, very high-speed operation clocks tend to be used.

  Along with this, the difficulty of countermeasures against unnecessary radiation noise (EMI countermeasures) has increased. For example, in Patent Document 1, paying attention to a method of transferring image data from a drawing circuit to a laser unit of a laser printer, the image data is once converted into a substantially sinusoidal signal and transmitted through a balanced transmission line, and then again a square wave. A method of converting to is proposed.

JP 2001-339444 A

  However, in the above-described method, the image data signal to the laser unit circuit is once converted into a substantially sine wave, and then converted again into a square wave to restore the layer data signal. Therefore, it is difficult to store PWM modulation information of 1 dot or less to be used for transferring an image data signal whose gradation has been increased by PWM modulation (pulse width modulation) performed for high image quality in recent years. was there.

  The present invention has been made in view of the above-described problems, and an object thereof is to provide a cheaper and simpler countermeasure (EMI countermeasure) against unnecessary radiation noise.

  An image processing apparatus according to the present invention is an image processing apparatus for processing image data and generating an image signal for causing a printer engine to draw the image data, and a plurality of image processing means for processing the image data in parallel. A plurality of output means for outputting image data processed by the image processing means, a plurality of output synchronization means for synchronously outputting the image data in synchronization with a synchronization signal generated by the printer engine, and a clock generation means. Phase distribution means for generating a plurality of clocks having different phases when distributing the clock, and operating the plurality of image processing means with the plurality of clocks having different phases generated by the phase adjustment means. It is characterized by.

  An image processing method of the present invention is an image processing method for generating image signals for processing image data and rendering a printer engine, wherein the image processing step performs data processing in parallel with the image data, and the image An output step of outputting image data output in the processing step, an output synchronization step of synchronously outputting the image data in synchronization with a synchronization signal generated by the printer engine, and a plurality of phases having different phases when distributing clocks A phase adjustment step for generating a clock, and the image processing step is operated with a plurality of clocks having different phases generated in the phase adjustment step.

  The program of the present invention is characterized in that each step of the above method is executed by a computer.

  According to the present invention, it is possible to intentionally disperse the phase relationship of each operation clock of the image processing circuit which is the main circuit portion. In addition, it is possible to disperse the phase of the current waveform consumed during the circuit operation, and to disperse and reduce the peak power of noise generated by the current change synchronized with each operation clock. As a result, it is possible to provide a measure (EMI countermeasure) against unnecessary radiation noise that is cheaper and simpler.

(First embodiment)
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
First, the entire image processing apparatus according to the present embodiment will be described with reference to FIG.
FIG. 1 is a block diagram illustrating a schematic configuration example of a printer controller as an example of an image processing apparatus according to the present exemplary embodiment.
When the printer controller 101 receives data to be printed from a host computer (PC) or the like (not shown) via the I / O interface 105, the CPU 102 writes the data to the RAM 104 by I / O transfer.

  The CPU 102 performs image processing according to a printer engine method described later, and the processed data is written in the RAM 104. When a series of image processing is completed and printing is possible, the image is sent to the image processing circuit unit 106 by the DMA controller built in the CPU 102.

  The image processing circuit unit 106 converts the image-processed data into an image signal that can be drawn by the printer engine, and sends the image signal to a printer engine (not shown) via the printer engine interface 107. Then, the printer engine performs drawing according to the image signal and prints an image on a print sheet.

  FIG. 3 is a flowchart illustrating an example of a series of processing procedures of the printer controller 101 in the present embodiment. The data to be printed sent from the host computer is data compressed in advance to reduce the data amount and the data transfer time.

  First, in step S311, the printer controller 101 receives data by I / O transfer. Next, in step S312, the received data is decompressed. In step S313, color conversion corresponding to the printer engine method is performed. In step S314, a series of image processing such as halftone processing is performed.

  In step S315, the data after the series of image processing is transferred to the image processing circuit unit 106 using a DMA controller built in the CPU. The image processing circuit unit 106 decompresses the image data received from the CPU 102 and then converts the image data according to each color table and halftone table.

  In step S316, the image signal is converted into an image signal that can be drawn by the printer engine through the PWM modulation process, sent to the printer engine (not shown) via the printer engine interface 107, and the process ends. The printer engine performs drawing according to the image signal and prints an image on a print sheet.

FIG. 2 is a block diagram illustrating an internal configuration example of the image processing circuit unit 106 according to the present embodiment.
In FIG. 2, a clock A generated by the clock generation circuit 201 is input to the first PLL circuit 211 and converted into a first operation clock. The first operation clock is output to the first color image processing circuit 231 and the first color image data output circuit 241.

  When the image processing circuit 231 for the first color receives image data input from the CPU 102 via the CPU bus, the first color image processing circuit 231 performs predetermined image processing at the operation clock A. The processed image data is output to the first color image data output circuit 241. The first output synchronization circuit 251 synchronizes the data to be output in the first color image data output circuit 241 with the BD signal 1 which is a horizontal synchronization signal output from the printer engine via the printer engine interface 107. And output as an image signal 1.

  On the other hand, the clock generated by the clock generation circuit 201 is input to the delay circuit 202 set to a predetermined delay amount. The delay circuit 202 generates a clock B having a phase delayed by 90 degrees. The clock B is input to the second PLL circuit 212, converted to a second operation clock, and output to the second color image processing circuit 232 and the second color image data output circuit 242.

  When the image data input from the CPU 102 via the CPU bus is received, the second color image processing circuit 232 performs predetermined image processing at the operation clock B. The processed image data is output to the second color image data output circuit 242. The second output synchronization circuit 252 synchronizes the data to be output in the second color image data output circuit 242 with the BD signal 2 which is a horizontal synchronization signal output from the printer engine via the printer engine interface 107. And output as an image signal 2.

  Further, the clock B is input to the delay circuit 203, and the delay circuit 203 generates a clock C whose phase is delayed by 180 degrees from the clock A. The clock C is input to the third PLL circuit 213 and converted into a third operation clock. The third operation clock is output to the third color image processing circuit 233 and the third color image data output circuit 243.

  When receiving image data input from the CPU 102 via the CPU bus, the third color image processing circuit 233 performs predetermined image processing at the operation clock C. The processed image data is output to the third color image data output circuit 243. The third output synchronization circuit 253 synchronizes the data to be output in the third color image data output circuit 243 with the BD signal 3 which is a horizontal synchronization signal output from the printer engine via the printer engine interface 107. And output as an image signal 3.

  Further, the clock C is input to the delay circuit 204, and the delay circuit 204 generates a clock D whose phase is delayed by 270 degrees from the clock A. The clock D is input to the fourth PLL circuit 214 and converted into a fourth operation clock. The fourth operation clock is output to the fourth color image processing circuit 234 and the fourth color image data output circuit 244.

  When the image data input from the CPU 102 via the CPU bus is received, the fourth color image processing circuit 234 performs predetermined image processing at the operation clock D. The processed image data is output to the fourth color image data output circuit 244. The fourth output synchronization circuit 254 synchronizes the data to be output in the fourth color image data output circuit 244 with the BD signal 4 which is a horizontal synchronization signal output from the printer engine via the printer engine interface 107. And output as an image signal 4.

  The first to fourth output synchronization circuits 251 to 254 described above have a PWM modulation function corresponding to high image quality. Further, when the printer engine (not shown) receives the image signal 1, the image signal 2, the image signal 3, and the image signal 4, the laser corresponding to each of the printer engine is driven and electrostatically is applied to a photosensitive drum or the like in the engine process. An image is formed. Thereafter, toner of a predetermined color is adsorbed to the electrostatic image, and finally a visible image is formed and output for printing.

  The circuit scale of the image processing circuits 231 to 234 in the image processing circuit unit 106 described above is increasing in proportion due to recent high image quality and resolution, and the current consumed in this portion is also large. In accordance with the current consumed in proportion to the circuit scale, there is a large amount of noise that causes a change in current synchronized with each operation clock.

FIG. 4 is a diagram showing the phase relationship of each clock in the present embodiment.
As shown in FIG. 4, the phase relationship of the operation clocks of the image processing circuits 231 to 234, which are the main circuit portions, is intentionally distributed by the delay circuits 202 to 204, thereby being consumed during the circuit operation. The phase of the current waveform can also be dispersed. As a result, the peak power of noise generated by a change in current synchronized with each operation clock can be dispersed and reduced.

(Second Embodiment)
Hereinafter, this embodiment will be described with reference to FIGS. 5 and 6. In the first embodiment, the operation when the laser unit of the printer engine has one system for each color has been described. However, with the recent increase in resolution and speed of printers, the laser units of printer engines have been converted into multi-beams of two or more systems for each color. Hereinafter, the operation in the case of two laser units for each color will be described with reference to FIG.

FIG. 5 is a block diagram illustrating an example of an internal configuration of the image processing circuit unit 105 according to the present embodiment.
In FIG. 5, a clock A1 generated by the clock generation circuit 501 is input to an eleventh PLL circuit 511 and converted into an eleventh operation clock. The eleventh operation clock is output to the first color first image processing circuit 531 and the first color first image data output circuit 541.

  When the first color first image processing circuit 531 receives image data 11 input from the CPU 102 via the CPU bus, the first color first image processing circuit 531 performs predetermined image processing at the operation clock A1. The processed image data is output to the first color first image data output circuit 541. The eleventh output synchronization circuit 551 converts the data to be output from the first color first image data output circuit 541 into the BD signal 11 which is a horizontal synchronization signal output from the printer engine via the printer engine interface 107. The image signal 11 is output in synchronization.

  On the other hand, the clock generated by the clock generation circuit 501 is input to the delay circuit 502 set to a predetermined delay amount. The delay circuit 502 generates a clock A2 having a phase delayed by 45 degrees. The clock A2 is input to the twelfth PLL circuit 512 and converted into a twelfth operation clock. The twelfth operation clock is input to the second color second image processing circuit 532 and the second color second image data output circuit 542.

  When the image data 12 input from the CPU 102 via the CPU bus is received, the first color second image processing circuit 532 performs predetermined image processing at the operation clock A2. The processed image data is output to the second color second image data output circuit 542. The twelfth output synchronization circuit 552 converts the data to be output in the second color second image data output circuit 542 into the BD signal 12 which is a horizontal synchronization signal output from the printer engine via the printer engine interface 107. The image signal 12 is output in synchronization.

  Similarly, clocks having different phases are input to the 21st to 42nd PLL circuits 513 to 518, and converted to the 21st to 42nd operation clocks. The image processing circuits 533 to 538 process the image data 21, 22, 31, 32, 41, and 42, and output them to the output circuits 543 to 548. And it outputs as image signal 21, 22, 31, 32, 41, 42 in each output synchronous circuit 553-558.

FIG. 6 is a diagram showing the phase relationship of each clock in the present embodiment.
As shown in FIG. 6, the phase relationship of the operation clocks of the image processing circuits 531 to 538, which are the main circuit portions, is intentionally distributed by the delay circuits 202 to 208, thereby being consumed during the circuit operation. The phase of the current waveform can also be dispersed. As a result, it is possible to disperse and reduce the noise peak power generated by the change in current synchronized with each operation clock.

  Further, since the image processing circuit unit 106 has a large circuit scale, an ASIC may be considered. However, the delay amount of the delay circuits 202 to 208 can be set by the CPU 102, so that even when the clock frequency is changed, each operation clock is set to an optimum phase relationship by appropriately selecting the delay setting. be able to.

(Other embodiments according to the present invention)
Each means constituting the image processing apparatus and each step of the image processing method in the embodiment of the present invention described above can be realized by operating a program stored in a RAM or ROM of a computer. This program and a computer-readable recording medium recording the program are included in the present invention.

  Further, the present invention can be implemented as, for example, a system, apparatus, method, program, or recording medium. Specifically, the present invention may be applied to a system including a plurality of devices. The present invention may be applied to an apparatus composed of a single device.

  In the present invention, a software program (in the embodiment, a program corresponding to the flowchart shown in FIG. 3) that realizes the functions of the above-described embodiments is directly or remotely supplied to the system or apparatus. This includes the case where the system or the computer of the apparatus is also achieved by reading and executing the supplied program code.

  Therefore, the program code itself installed in the computer in order to realize the functional processing of the present invention by the computer also realizes the present invention. In other words, the present invention includes a computer program itself for realizing the functional processing of the present invention.

  In that case, as long as it has the function of a program, it may be in the form of object code, a program executed by an interpreter, script data supplied to the OS, and the like.

  Examples of the recording medium for supplying the program include a floppy (registered trademark) disk, a hard disk, an optical disk, and a magneto-optical disk. Further, there are MO, CD-ROM, CD-R, CD-RW, magnetic tape, nonvolatile memory card, ROM, DVD (DVD-ROM, DVD-R) and the like.

  As another program supply method, there is a method of connecting to a homepage on the Internet using a browser of a client computer. The computer program itself of the present invention or a compressed file including an automatic installation function can be downloaded from the homepage by downloading it to a recording medium such as a hard disk.

  It can also be realized by dividing the program code constituting the program of the present invention into a plurality of files and downloading each file from a different homepage. That is, a WWW server that allows a plurality of users to download a program file for realizing the functional processing of the present invention on a computer is also included in the present invention.

  As another method, the program of the present invention is encrypted, stored in a recording medium such as a CD-ROM, distributed to users, and encrypted from a homepage via the Internet to users who have cleared predetermined conditions. Download the key information to be solved. It is also possible to execute the encrypted program by using the key information and install the program on a computer.

  Further, the functions of the above-described embodiments are realized by the computer executing the read program. Furthermore, based on the instructions of the program, an OS or the like running on the computer performs part or all of the actual processing, and the functions of the above-described embodiments can be realized by the processing.

  As another method, the program read from the recording medium is first written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer. Then, based on the instructions of the program, the CPU or the like provided in the function expansion board or function expansion unit performs part or all of the actual processing, and the functions of the above-described embodiments are also realized by the processing.

1 is a block diagram illustrating a schematic configuration example of an entire image processing apparatus according to a first embodiment of the present invention. It is a block diagram which shows the internal structural example of the image processing circuit part in the 1st Embodiment of this invention. It is a flowchart which shows the process sequence of the whole image process in the 1st Embodiment of this invention. It is a figure which shows the phase shift | offset | difference of each clock in the 1st Embodiment of this invention. It is a block diagram which shows the internal structural example of the image processing circuit part in the 2nd Embodiment of this invention. It is a figure which shows the phase shift | offset | difference of each clock in the 2nd Embodiment of this invention.

Explanation of symbols

101 Printer controller 102 CPU
104 RAM
105 I / O interface 106 Image processing circuit unit 107 Printer engine interface 201 Clock generation circuit 202 Delay circuit 203 Delay circuit 204 Delay circuit 211 First PLL circuit 212 Second PLL circuit 213 Third PLL circuit 214 Fourth PLL Circuit 231 First color image processing circuit 232 Second color image processing circuit 233 Third color image processing circuit 234 Fourth color image processing circuit 241 First color image data output circuit 242 Second color image data output Circuit 243 Third color image data output circuit 244 Fourth color image data output circuit 251 First output synchronization circuit 252 Second output synchronization circuit 253 Third output synchronization circuit 254 Fourth output synchronization circuit

Claims (5)

An image processing apparatus that generates image signals for processing image data and causing a printer engine to draw the image data,
A plurality of image processing means for processing the image data in parallel;
A plurality of output means for outputting the image data processed by the image processing means;
A plurality of output synchronization means for synchronously outputting the image data in synchronization with a synchronization signal generated by the printer engine;
Phase distribution means for generating a plurality of clocks having different phases when distributing clocks generated by the clock generation means,
An image processing apparatus, wherein the plurality of image processing means are operated by a plurality of clocks having different phases generated by the phase adjusting means.   The image processing apparatus according to claim 1, wherein the image processing unit performs data processing on the image data in parallel with each color in order to generate an image signal to be drawn by a color printer engine.   The image processing apparatus according to claim 1, wherein the image processing means processes image data in parallel with each color in order to generate an image signal to be drawn by the multi-beam printer engine. An image processing method for processing image data and generating an image signal for causing a printer engine to draw the image data,
An image processing step for processing the image data in parallel;
An output step of outputting image data output in the image processing step;
An output synchronization step of synchronously outputting the image data in synchronization with a synchronization signal generated by the printer engine;
A phase adjusting step for generating a plurality of clocks having different phases when distributing the clocks;
An image processing method comprising operating the image processing step with a plurality of clocks having different phases generated in the phase adjustment step.   A program causing a computer to carry out each step of the method according to claim 4.

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