JP2007329837A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To highly accurately perform desired signal processing without increasing a circuit scale in equalizing processing by a digital filter. <P>SOLUTION: When digital input data are inputted, a right shifter 17 shifts fixed decimal point data to the right on the basis of an adjustment value stored in a register 24 and performs filter calculation. Then, left shifters 20-22 shifts them to the left on the basis of the adjustment value stored in the register 24 and returns an extended integer part to the original. An adjustment value change circuit 23 compares the code bit of the fixed decimal point data stored in a buffer 14 and the most significant bit of the integer part. When they do not match, the adjustment value change circuit 23 outputs shift control signals to the right shifters 18 and 19 and shifts the fixed decimal point data stored in the buffers 14 and 15 to the right by 1 bit. Then, the adjustment value stored in the register 24 is increased and the adjustment value in the register 24 is overwritten. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an equalizing processing technique for audio signals, and more particularly to a technique effective for preventing overflow in filter operation processing of digital audio data.

  As an equalizer device for correcting frequency characteristics in a digital audio device, a digital filter constituted by a DSP (Digital Signal Processor) or a digital circuit is known.

In this type of digital filter, as a technique for performing the filtering process without reducing the calculation accuracy, for example, a technique for dividing the configuration of the digital filter into upper bits and lower bits (see Patent Document 1), a downsampling unit, etc. There is a technique for increasing the center frequency at the time of calculation (see Patent Document 2).
Japanese Patent Laid-Open No. 05-7120 Japanese Patent Laid-Open No. 10-84239

  However, the present inventors have found that the equalizer device as described above has the following problems.

  FIG. 12 is a circuit configuration example of the equalizer device 200 examined by the present inventors. The equalizer device 200 includes adders 201 and 202, multipliers 203 to 207 and 210, buffers 208 and 209, and the like.

  In general, in signal processing using a digital filter of an equalizer device, when correcting characteristics of an input audio signal, a large bit length is required during calculation depending on the center frequency and gain of the frequency to be corrected.

  Therefore, in the equalizer device 200 of FIG. 12, the overflow of the filter operation is prevented according to the scale value 214 calculated in advance with the constants S and b0 to b2 of the adder 201 and the multipliers 205, 206, and 207.

  However, in this method, since the scale value is not calculated depending on the input data, the scale value has to be determined in the worst case of the input data, so that there is a problem that the bit accuracy is greatly reduced.

  Further, the techniques of Patent Documents 1 and 2 have a problem that the operation length of the multiplier and the adder can be kept constant, but other circuit scales increase or the processing in the DSP increases.

  An object of the present invention is to provide a technique capable of performing desired signal processing with high accuracy without increasing the circuit scale in equalizing processing using a digital filter.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention is a semiconductor integrated circuit device including an equalizer unit that performs a filter operation on digital data and performs an equalizing process, and the equalizer unit adjusts a shift amount of the digital data according to the input digital data. An adjustment value change setting unit for preventing overflow during filter calculation is provided.

  Moreover, the outline | summary of the other invention of this application is shown briefly.

  The present invention provides an adjustment value storage unit in which the adjustment value change setting unit increments and stores an input adjustment value, and an integer of digital data input according to the adjustment value stored in the adjustment value storage unit An expansion unit that expands the unit, a first storage unit that stores digital data one hour before used for the filter operation, a second storage unit that stores the digital data stored in the first storage unit, An adjustment value for determining whether adjustment of digital data is necessary from the digital data stored in the first storage unit, and outputting an adjustment value to the adjustment value storage unit when adjustment is necessary, and outputting an adjustment control signal A change circuit, a first 1-bit right shifter that shifts the digital data stored in the first storage unit to the right by 1 bit based on the adjustment control signal output from the adjustment value change circuit, and an adjustment value Output from change circuit A second 1-bit right shifter that shifts the digital data stored in the second storage unit to the right by one bit based on the adjustment control signal, and an adjustment value stored in the adjustment value storage unit A reduction unit that restores the integer part of the digital data extended by the extension unit.

  Further, according to the present invention, the expansion unit includes a right shifter that shifts the input digital data to the right according to the adjustment value stored in the adjustment value storage unit, and the reduction unit stores the adjustment value. A first left shifter for shifting the latest digital data to the left according to the adjustment value stored in the output unit; and storing in the first storage unit according to the adjustment value stored in the adjustment value storage unit. A second left shifter that shifts and outputs the digital data of the previous time to the left, and the digital data of the previous time stored in the second storage unit in accordance with the adjustment value stored in the adjustment value storage unit And a third left shifter for shifting the data to the left and outputting it.

  Further, according to the present invention, the adjustment value changing circuit compares the sign bit in the fixed-point format with the most significant bit of the integer part, and determines that the adjustment value does not need to be changed when the bits are the same. It is judged that adjustment is necessary.

  In the present invention, the equalizer unit is provided in a digital signal processor.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) It is possible to prevent overflow when performing digital data filtering.

  (2) Further, since it can be realized with a simple circuit configuration, an increase in the size of the semiconductor integrated circuit device can be prevented.

  (3) With the above (1) and (2), it is possible to perform high-precision equalization with low noise and low noise, thereby realizing high performance and high reliability of the semiconductor integrated circuit device. it can.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing a configuration of an equalizer unit provided in the DSP of the semiconductor integrated circuit device of FIG. 1, and FIG. 2 is an explanatory diagram showing an example of a fixed-point format in audio data processed by the equalizer unit of FIG. 2, FIG. 4 is a flowchart of an example of filter calculation processing by the equalizer unit of FIG. 3, and FIG. 5 is provided in the equalizer unit of FIG. 6 is an explanatory diagram showing an example of scaling by the right shifter, FIG. 6 is an explanatory diagram showing another example of scaling by the right shifter provided in the equalizer unit of FIG. 2, and FIG. 7 is provided in the equalizer unit of FIG. FIG. 8 is an explanatory diagram showing another example of scaling by the left shifter provided in the equalizer section of FIG. 2, 9 is an explanatory view showing a state example of the fixed-point data requiring adjustment value changed according to this embodiment, FIG. 10, the adjustment value changes is an explanatory view showing a state example of unnecessary fixed-point data.

  In the present embodiment, the semiconductor integrated circuit device 1 is used in, for example, a digital audio playback device. As shown in FIG. 1, the semiconductor integrated circuit device 1 includes a CPU (Central Processing Unit) 2, a DSP 3, a DMA (Direct Memory Access) controller 4, a memory 4a, an audio interface 5, and the like.

  The CPU 2, DSP 3, DMA controller 4, and audio interface 5 are connected to each other by a bus 6. The CPU 2 governs overall control in the semiconductor integrated circuit device 1. The DSP 3 is a processor that performs digital signal processing on audio data.

  The DMA controller 4 directly accesses the designated memory address space without going through the CPU 2 to the externally connected memory or the internally provided memory 4a in accordance with an instruction from the DSP 3 or the audio interface 5, and writes data or Control reading. The audio interface 5 is an interface for inputting and outputting audio signals.

  As shown in FIG. 2, the DSP 3 is provided with an equalizer unit 3 a that performs an equalizer process. As illustrated, the equalizer unit 3 a includes adders 7 and 8, multipliers 9 to 13, buffers 14 and 15, and an adjustment value change setting unit 16.

  The adjustment value change setting unit 16 prevents overflow when the equalizer unit 3a performs a filter operation. The adjustment change setting unit 16 includes a right shifter 17 to 19, a left shifter 20 to 22, an adjustment value change circuit 23, and a register. (Adjustment value storage unit) 24.

  Digital input data such as audio data is input to the input unit of the right shifter (extension unit) 17. Digital input data has a fixed-point format (FIG. 3) configuration. The right shifter 17 shifts the digital input data input in the fixed-point format to the right according to the adjustment value stored in the register 24. The adjustment value stored in the register 24 is data indicating a data shift amount (how many bits are shifted).

  An adder 7 is connected to the output section of the right shifter 17. The adder 7 is connected to a multiplier 11, an input unit of a buffer (first storage unit) 14, and output units of the multipliers 9 and 10. A right shifter (first 1-bit right shifter) 18, an input unit of a multiplier 9, and a buffer (second storage unit) 15 are connected to the buffer 14.

  The buffer 14 is connected to the adjustment value changing circuit 23 and the multiplier 12. The buffer 15 is connected to the right shifter (second 1-bit right shifter) 19 and the input units of the multipliers 10 and 13.

  The adder 7 adds the multiplication results of the multipliers 9 and 10 to the input data output from the right shifter 17 and outputs the result. The multiplier 11 multiplies the data output from the adder 7 by the constant b0.

  The buffer 14 temporarily stores the data output from the adder 7 or the data shifted to the right shifter 18. The buffer 15 temporarily stores the data in the buffer 14 or the data shifted to the right shifter 19 to the right.

  The right shifters 18 and 19 are connected so that a shift control signal output from the adjustment value changing circuit 23 is input. The right shifter 18 shifts the data stored in the buffer 14 to the right by 1 bit when the shift control signal is input. The buffer 14 overwrites and stores the data shifted by the right shifter 18.

  The right shifter 19 shifts the data stored in the buffer 15 to the right by 1 bit when the shift control signal is input. The buffer 15 overwrites and stores the data shifted by the right shifter 19.

  The multiplier 9 multiplies the data stored in the buffer 14 by the constant a1 and outputs the result to the adder 7. The multiplier 10 multiplies the data stored in the buffer 15 by the constant a2, and outputs the result to the adder 7. The adjustment value changing circuit 23 calculates an adjustment value (shift amount) from the contents of the data stored in the buffer 14.

  A left shifter (reduction unit, first left shifter) 20 is connected to the output unit of the multiplier 11. Input units of multipliers 12 and 13 are connected to the buffers 14 and 15, respectively, and left shifters 21 and 22 are connected to output units of the multipliers 12 and 13, respectively.

  Further, the left shifters 20 to 22 are connected so that the adjustment values stored in the register 24 are respectively input. The input units of the adder 8 are connected to the output units of the left shifters 20 to 22, and the output unit of the adder 8 serves as the output unit of the equalizer unit 3a.

  The multiplier 11 multiplies the data output from the adder 7 by the constant b0 and outputs the result to the left shifter 20. The multiplier 12 multiplies the data stored in the buffer 14 by the constant b1, and outputs the result to the left shifter (reduction unit, second left shifter) 21. The multiplier 13 multiplies the data stored in the buffer 14 by the constant b 2 and outputs the result to the left shifter (reduction unit, third left shifter) 22.

  The left shifters 20 to 22 shift the data to the left based on the adjustment value stored in the register 24 and output the data to the adder 8. The adder 8 adds the data output from the left shifters 20 to 22 and outputs the result.

  Here, FIG. 3 shows an example of a fixed-point format used when performing fixed-point arithmetic in audio data filtering.

  As shown in the figure, in this example, a sign bit indicating polarity is positioned first, and the most significant bit of the integer part is adjacent to the sign bit. The integer part is 8 bits including the sign bit, and the integer part is followed by a 7-bit decimal part.

  In this case, an integer part may be insufficient depending on a filter that obtains a desired frequency characteristic. Therefore, the adjustment value for performing the right shift is calculated by the adjustment value changing circuit 23, and the right shifter 17 performs the right shift based on the adjustment value to expand the integer part IB, and the right shift is performed by the left shifters 20-22. By performing left shift by the amount, overflow can be prevented by restoring the expanded integer part.

  This adjustment value can be determined offline beforehand in the worst case of the input data. However, if it is determined in the worst case, the number of bits in the decimal part is smaller than the actual input data and the calculation accuracy is deteriorated.

  Next, the operation of the adjustment value change setting unit 16 provided in the equalizer unit 3a according to the present embodiment will be described.

  FIG. 4 is a flowchart of an example of filter calculation processing by the equalizer unit 3a.

  First, when digital input data is input, the right shifter 17 performs scaling for shifting the fixed-point data to the right based on the value of the adjustment value stored in the register 24 (step S101).

  FIG. 5 is an explanatory diagram showing an example of scaling (right shift) by the right shifter 17 when “1” is stored in the register 24 as the adjustment value.

  In FIG. 5, the right shift 17 is shifted to the right by 1 bit because the adjustment value is “1”. In this case, data b15 to b0 other than the sign bit are shifted right by 1 bit. As a result, the least significant bit data b0 disappears, and the most significant bit of the integer part is insufficient, so that the sign bit data S is input to the most significant bit.

  FIG. 6 is an explanatory diagram showing an example of scaling (right shift) by the right shifter 17 when “2” is stored in the register 24 as an adjustment value.

  In this case, the data b15 to b0 other than the sign bit are shifted to the right by 2 bits. As a result, the data b0 and b1 of the least significant bit and the adjacent bits disappear, and the most significant bit of the integer part and the adjacent bit (the most significant bit minus 1 bit) are insufficient. The sign bit data S is input to the upper bits and the adjacent bits.

  Subsequently, in FIG. 4, filter calculation is performed (step S102). This filter calculation is performed by the adders 7 and 8, the buffers 14 and 15, and the multipliers 9 to 13. Then, scaling is performed (step S103). In this scaling, the left shifters 20 to 22 shift left based on the adjustment value stored in the register 24, and restore the expanded integer part.

  FIG. 7 is an explanatory diagram showing an example of scaling by the left shifter 20 (˜22) when “1” is stored in the register 24 as an adjustment value.

  In FIG. 7, the data b15 to b0 other than the sign bits are shifted to the left by 1 bit by the left shifter 20 (to 22). As a result, the most significant bit of the integer part changes from data b15 to data b14, and the least significant bit data b0 disappears. '0' is input to the shortest least significant bit.

  FIG. 6 is an explanatory diagram showing an example of scaling by the left shifter 20 (˜22) when “2” is stored in the register 24 as an adjustment value.

  In this case, the data b15 to b0 other than the sign bit are shifted to the right by 2 bits. As a result, the data b0 and b1 of the least significant bit and the adjacent bits disappear, and '0' is input to each of the missing bits.

  Data b13 to data b0 are input to each bit below the most significant bit of the integer part.

  Thereafter, the adjustment value changing circuit 23 checks the state of the addition result of the adder 7 stored in the buffer 14 (step S104), and determines whether or not to change the adjustment value (step S105).

  FIG. 9 is an explanatory diagram showing an example of the state of fixed-point data that requires an adjustment value change, and FIG. 10 is an explanatory diagram showing an example of the state of fixed-point data that does not require an adjustment value change.

  The state where the adjustment value needs to be changed is a case where the sign bit of the fixed-point data stored in the buffer 14 and the most significant bit of the integer part do not match as shown in FIG. Further, the state in which the adjustment value change is unnecessary is a case where the sign bit of the fixed-point data stored in the buffer 14 and the most significant bit of the integer part match as shown in FIG.

  As shown in FIG. 9, when the sign bit is different from the most significant bit of the integer part and the adjustment value needs to be changed, the adjustment value change circuit 23 outputs the shift control signal to the right shifters 18 and 19 respectively (step S106). ).

  In the process of step S106, the right shifter 18 (, 19) receives the shift control signal and shifts the fixed-point data stored in the buffer 14 (, 15) to the right by 1 bit.

  This right shift is performed in the same way as the right shift in the case where “1” is stored in the register 24 by the right shifter 17 shown in FIG.

  Subsequently, the adjustment value stored in the register 24 is incremented, and the adjustment value in the register 24 is overwritten (step S107).

  Thereby, according to this Embodiment, the overflow at the time of the equalizer part 3a performing a filter calculation can be prevented.

  Further, the adjustment value change setting unit 16 includes a shift computing unit (right shifters 17 to 19 and left shifters 20 to 22), a 1-bit comparator (adjustment value change circuit 23), and a register 24. Can be prevented from increasing significantly.

  Furthermore, since the optimum adjustment value is calculated in real time according to the digital input data, highly accurate equalizing adjustment can be performed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above-described embodiment, the DSP is provided with the equalizer unit, but the equalizer unit of the present invention may be provided as a peripheral circuit in the semiconductor integrated circuit device without being provided in the DSP.

  FIG. 11 is a block diagram of the semiconductor integrated circuit device 1 showing an example thereof.

  In this case, the semiconductor integrated circuit device 1 includes a CPU 2, an equalizer unit 3 a, a DMA controller 4, a memory 4 a, an audio interface 5, and the like, which are connected to each other by a bus 6.

  The present invention is suitable for high-precision equalizing processing technology for digital audio data and the like.

1 is a block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is an explanatory diagram illustrating a configuration of an equalizer unit provided in the DSP of the semiconductor integrated circuit device of FIG. 1. It is explanatory drawing which shows an example of the fixed point format in the audio data processed by the equalizer part of FIG. It is a flowchart of the example of filter calculation processing by the equalizer part of FIG. It is explanatory drawing which shows an example of the scaling by the right shifter provided in the equalizer part of FIG. It is explanatory drawing which shows the other example of the scaling by the right shifter provided in the equalizer part of FIG. It is explanatory drawing which shows an example of the scaling by the left shifter provided in the equalizer part of FIG. It is explanatory drawing which shows the other example of the scaling by the left shifter provided in the equalizer part of FIG. It is explanatory drawing which showed the example of the state of the fixed point data which needs adjustment value change by this Embodiment. It is explanatory drawing which showed the example of the state of the fixed point data which does not require adjustment value change. It is a block diagram of the semiconductor integrated circuit device by other embodiment of this invention. It is explanatory drawing which shows the structure of the equalizer part which this inventor examined.

Explanation of symbols

1 Semiconductor Integrated Circuit Device 2 CPU
3 DSP
3a Equalizer section 4 DMA controller 4a Memory 5 Audio interface 6 Buses 7 and 8 Adders 9 to 13 Multiplier 14 Buffer (first storage section)
15 buffer (second storage)
16 Adjustment value change setting part 17 Right shifter (expansion part)
18 Right shifter (first 1-bit right shifter)
19 Right shifter (second 1-bit right shifter)
20 Left shifter (reduced part, first left shifter)
21 Left shifter (reduced part, second left shifter)
22 Left shifter (reduced part, third left shifter)
23 Adjustment Value Change Circuit 24 Register (Adjustment Value Storage Unit)
200 Equalizers 201 and 202 Adders 203 to 207 Multipliers 208 and 209 Buffers

Claims (5)

A semiconductor integrated circuit device including an equalizer unit that performs digital filter processing and equalization processing,
The equalizer section is
A semiconductor integrated circuit device comprising: an adjustment value change setting unit that adjusts a shift amount of the digital data according to input digital data and prevents an overflow during filter calculation. The semiconductor integrated circuit device according to claim 1.
The adjustment value change setting unit
An adjustment value storage for incrementing and storing the input adjustment value;
An extension unit for extending the integer part of the digital data input according to the adjustment value stored in the adjustment value storage unit;
A first storage unit for storing digital data one hour before used for the filter operation;
A second storage unit for storing digital data stored in the first storage unit;
From the digital data stored in the first storage unit, it is determined whether adjustment of the digital data is necessary, and when adjustment is necessary, an adjustment value is output to the adjustment value storage unit and an adjustment control signal is output An adjustment value changing circuit to be
A first 1-bit right shifter that shifts digital data stored in the first storage unit to the right by 1 bit based on an adjustment control signal output from the adjustment value changing circuit;
A second 1-bit right shifter that shifts the digital data stored in the second storage unit to the right by 1 bit based on the adjustment control signal output from the adjustment value changing circuit;
A semiconductor integrated circuit device comprising: a reduction unit that restores an integer part of digital data expanded by the expansion unit according to an adjustment value stored in the adjustment value storage unit. The semiconductor integrated circuit device according to claim 2.
The extension is
According to the adjustment value stored in the adjustment value storage unit, the input digital data is right-shifted and output by shifting the digital data,
The reduction unit is
According to the adjustment value stored in the adjustment value storage unit, the first left shifter for shifting and outputting the latest digital data to the left,
In accordance with the adjustment value stored in the adjustment value storage unit, a second left shifter that shifts and outputs the digital data of the previous time stored in the first storage unit to the left;
According to the adjustment value stored in the adjustment value storage unit, a third left shifter that shifts and outputs the digital data two times before stored in the second storage unit to the left is provided. Semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 2 or 3,
The adjustment value changing circuit includes:
The sign bit in the fixed-point format is compared with the most significant bit of the integer part, and it is determined that the adjustment value change is not necessary when the bits are the same, and the adjustment is determined to be necessary when the bits are different. Semiconductor integrated circuit device. The semiconductor integrated circuit device according to any one of claims 1 to 4,
The equalizer section is
A semiconductor integrated circuit device provided in a digital signal processor.

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