JP2007329507A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device consuming less power and operating high speed. <P>SOLUTION: This semiconductor integrated circuit device is formed on an SOI substrate, each of which includes a p-channel MOS transistor 14 and an n-channel MOS transistor 15. The device has a plurality of inverters 11-13 connected in series, and switches 21-26 which fix the bodies of transistors 14, 15 to boosted potential Vpp and negative potential Vbb, respectively, during a standby mode period, and make the bodies of transistors 14, 15 to floating states during an active mode period. Sub-threshold leakage current I<SB>L</SB>is thereby reduced during the standby mode period, and the switching speed is increased during the active mode period. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device formed on an SOI (Silicon On Insulator) substrate and having a standby mode and an active mode.

  FIG. 13 is a circuit diagram showing a configuration of a CMOS inverter 70 of a conventional semiconductor integrated circuit device (DRAM, SRAM, etc.) formed on an SOI substrate. Referring to FIG. 13, CMOS inverter 70 includes an input node N71, an output node N72, a p-channel MOS transistor 71 and an n-channel MOS transistor 72. Input signal Vin is input to input node N71, and output signal Vout is output from output node N72. P channel MOS transistor 71 has its gate connected to input node N71, its source receiving power supply potential Vcc, and its drain connected to output node N72. N channel MOS transistor 72 has its gate connected to input node N71, its drain connected to output node N72, and its source grounded. The bodies of the MOS transistors 71 and 72 are both floating.

14A is a partially broken plan view showing the device structure of the n-channel MOS transistor 72 shown in FIG. 13, and FIG. 14B is a cross-sectional view taken along the line XX ′ of FIG. 14A. 14A and 14B, the n-channel MOS transistor 72 is formed on an SOI substrate 73. The SOI substrate 73 includes a silicon substrate 74 and a SiO buried oxide layer 75 and a p ⁻ type silicon layer 76 laminated on the surface thereof. The element region of n channel MOS transistor 72 is separated from other element regions by SiO insulating layer 77 in which p ⁻ type silicon layer 76 is oxidized.

A gate electrode 81 is formed above the center of the element region via a gate oxide film (not shown). A portion of the p ⁻ -type silicon layer 76 covered with the gate electrode 81 becomes the body region 82. An n ⁺ type drain region 83 is formed on one side of the gate electrode 81, and an n ⁺ type source region 84 is formed on the other side of the gate electrode 81. Gate electrode 81 is connected to input node N71, n ⁺ -type drain region 83 is connected to output node N72 through contact hole CH, and n ⁺ -type source region 84 is grounded through contact hole CH. The device structure of the p-channel MOS transistor 71 is the same as that of the n-channel MOS transistor 72 except that the p-type and n-type are reversed.

  Next, the operation of the CMOS inverter 70 shown in FIGS. 13 and 14A and 14B will be described. In the standby mode period in which the input signal Vin is at the “L” level (ground level Vss), the p-channel MOS transistor 71 is turned on, the n-channel MOS transistor 72 is turned off, and the output signal Vout is at the “H” level. (Power supply level Vcc). When the input signal Vin rises to “H” level during the active mode period, the p-channel MOS transistor 71 becomes non-conductive, the n-channel MOS transistor 72 becomes conductive, and the output signal Vout becomes “L” level. .

  By the way, in such a semiconductor integrated circuit device, in recent years, the power supply voltage has been lowered together with the higher integration. Therefore, it is necessary to reduce the threshold voltage of the MOS transistors constituting the semiconductor integrated circuit device and increase the driving capability so that the semiconductor integrated circuit device can operate at high speed even under a low power supply voltage.

However, when reduced as with the power supply voltage threshold voltage of the MOS transistor, the sub-threshold MOS transistors de leakage current I _L is increased. Therefore, the threshold voltage of the MOS transistor cannot be reduced in the same way as the power supply voltage, and it is expected that it will be difficult to improve the performance of the semiconductor integrated circuit device, particularly to realize its high speed. Such problems are pointed out in, for example, 1993 Symposium on VLSI Circuit Dig. Of Tech Papers pp. 47-48 and pp. 83-84.

For example, in the n-channel MOS transistor 72 of the CMOS inverter 70 shown in FIGS. 13 and 14A and 14B, as shown in FIG. 15, when the threshold voltage is reduced, the n ⁺ type drain region in the standby mode period. The junction leakage current flowing from 83 to the p ⁻ type body region 82 increases. As a result, the potential of p ⁻ type body region 82 rises and subthreshold leakage current I _{L of} n channel MOS transistor 72 increases. Such a phenomenon is pointed out, for example, in 1995 Symposium on VLSI Technology Dig. Of Tech Papers 12-3.

As a method of reducing the subthreshold leakage current I _L , there is a method of fixing the potential of the p ⁻ type body region 82 of the n-channel MOS transistor 72. In this method, as shown in FIG. 16, a T-shaped gate electrode 81 ′ is provided, and a p ⁺ -type contact region 85 is formed so as to be in contact with a p ⁻ -type body region 82 ′ covered with the gate electrode 81. Newly provided. By applying a constant substrate potential to the p ⁺ -type contact region 85 via the contact hole CH, the potential rise of the p ⁻ -type body region 82 ′ can be prevented, and the subthreshold leakage current I _L can be reduced. Can be planned.

However, this method has a problem that the layout area increases because it is necessary to provide the p ⁺ -type contact region 85. Further, there is a problem that the capacitance value between the p ⁻ type body region 82 and the n ⁺ type drain region 83 and the n ⁺ type source region 84 increases, and the operation speed is delayed.

  Therefore, a main object of the present invention is to provide a semiconductor device with low current consumption and high operating speed.

  A semiconductor device according to the present invention is a semiconductor device formed on an SOI substrate and having a standby mode and an active mode, and includes a source region, a drain region, and a body region located between the two regions. The transistor and the standby mode period are provided with body potential switching means for fixing the body region of the MOS transistor at a predetermined potential during a predetermined period and floating the body region during other periods.

  Preferably, the body potential switching means pulse-fixes the body region at a predetermined potential at a predetermined cycle in the standby mode period.

  Another semiconductor device according to the present invention is a semiconductor device formed on an SOI substrate and having a standby mode and an active mode, each connected in series between first and second power supply potential lines. A plurality of inverter circuits connected in series, and a predetermined period of the standby mode period is non-conductive during the standby mode period of the plurality of inverter circuits First body potential switching means for fixing the body region between the source region and the drain region of the MOS transistor to a boosted potential equal to or higher than the first power supply potential, and floating the body region during other periods, and a standby mode period The predetermined period of time is the standby mode period of the plurality of inverting circuits. The body region between the source region and the drain region of the n-channel MOS transistor that becomes non-conductive is fixed to a step-down potential equal to or lower than the second power supply potential, and the body region is floated during other periods. A potential switching means is provided.

  Still another semiconductor device according to the present invention is a semiconductor device formed on an SOI substrate and having a standby mode and an active mode, wherein a first main power supply line to which a first power supply potential is applied from the outside, The first sub power line provided corresponding to the first main power line, the second main power line provided with the second power potential from the outside, and the second main power line provided A plurality of inversion circuits connected in series, each including a p-channel MOS transistor and an n-channel MOS transistor connected in series between the first and second sub-power supply lines, A first connection means connected between the main power supply line and the first sub power supply line and conducting in the active mode period to apply a first power supply potential to the first sub power supply line; A second connection means connected between the source line and the second sub power supply line and conducting during the active mode period to apply the second power supply potential to the second sub power supply line; A p channel MOS transistor that is rendered non-conductive during the standby mode period is provided corresponding to a first region of the body region between the source region and the drain region of the corresponding p channel MOS transistor during a predetermined period of the standby mode period. First body potential switching means for fixing the boosted potential to a power supply potential equal to or higher than the power supply potential, and floating the body region during other periods, and an n-channel MOS transistor that is non-conductive in the standby mode period of the plurality of inversion circuits The predetermined period of the standby mode period is provided for the corresponding n-channel MOS transistor. The body region between the source region and drain region of the transistor is fixed to a step-down potential equal to or lower than the second power supply potential, and is provided with second body potential switching means for floating the body region during other periods. is there.

  Still another semiconductor device according to the present invention is a semiconductor device formed on an SOI substrate and having a standby mode and an active mode, each of which includes a p-channel MOS transistor and an n-channel MOS transistor whose drains are connected to each other. A plurality of inverter circuits connected in series, a first power supply potential is applied from the outside, and a first channel connected to the source of a p-channel MOS transistor that is conductive during a standby mode period of the plurality of inverter circuits A main power supply line, a second main power supply line externally supplied with a second power supply potential and connected to a source of an n-channel MOS transistor which is turned on during a standby mode period of the plurality of inversion circuits; A first power supply potential is applied from the line, and during a standby mode period of the plurality of inverting circuits A second power supply potential is applied from the first sub power supply line and the second main power supply line connected to the source of the p-channel MOS transistor which is turned on, and is turned off during the standby mode period of the plurality of inversion circuits. A second sub-power supply line connected to the source of the n-channel MOS transistor, and a p-channel MOS transistor that is non-conductive during the standby mode period of the plurality of inversion circuits. The body region between the source region and the drain region of the corresponding p-channel MOS transistor is fixed to a boosted potential equal to or higher than the first power supply potential during a predetermined period, and the body region is floated during the other periods. Body potential switching means and n-char which becomes non-conductive during standby mode among a plurality of inverting circuits A body region provided between the source region and the drain region of the corresponding n-channel MOS transistor is fixed to a potential lower than the second power supply potential during a predetermined period of the standby mode period. In other periods, second body potential switching means for floating the body region is provided.

  Preferably, the first body potential switching means pulse-fixes the body region of the p-channel MOS transistor at the boosted potential in a predetermined cycle in the standby mode period, and the second body potential switching means is in the standby mode period. The body region of the n-channel MOS transistor is fixed to the step-down potential in a predetermined cycle.

  In the semiconductor device according to the present invention, the body potential of the MOS transistor is fixed during a predetermined period of the standby mode period, and the body region of the MOS transistor is floated during other periods. Therefore, the subthreshold leakage current during the standby mode period can be reduced, and the operation speed during the active mode period can be improved.

  Preferably, the body potential of the MOS transistor is fixed in a pulse manner at a predetermined cycle in the standby mode period. In this case, the current consumption caused by fixing the body potential is minimized.

  In another semiconductor device according to the present invention, a plurality of inverting circuits including a p-channel MOS transistor and an n-channel MOS transistor, each connected in series between the first and second power supply potential lines, are provided. The body of the p-channel MOS transistor and the n-channel MOS transistor is fixed to the boosted potential and the step-down potential during the predetermined period of the standby mode period, and the body of the p-channel MOS transistor and the n-channel MOS transistor is floating during the other periods. Is done. Therefore, the subthreshold leakage current during the standby mode period can be reduced, and the operation speed during the active mode period can be improved.

  In still another semiconductor device according to the present invention, a plurality of series-connected inverting circuits each including a p-channel MOS transistor and an n-channel MOS transistor each connected in series between the first and second sub-power supply lines. In the active mode period, a first power supply potential is applied from the first main power supply line to the first subpower supply line, and a second power supply is supplied from the second main power supply line to the second subpower supply line. A potential is applied. During a predetermined period of the standby mode period, the bodies of the p-channel MOS transistor and the n-channel MOS transistor that are non-conductive during the standby mode period are fixed to the boosted potential and the step-down potential, respectively, and during other periods, the p-channel MOS transistor And the body of the n-channel MOS transistor is floated. Therefore, the subthreshold leakage current during the standby mode period can be reduced, and the operation speed during the active mode period can be improved. Further, since the potential drop of the first sub power supply line and the potential rise of the second sub power supply line during the standby mode period are prevented, the transition from the standby mode period to the active mode can be made quickly.

  In still another semiconductor device according to the present invention, the sources of the p-channel MOS transistor and the n-channel MOS transistor that are non-conductive during the standby mode period among the plurality of inversion circuits are the first and second sub power supply lines, respectively. And the sources of the p-channel MOS transistor and the n-channel MOS transistor that are conductive during the standby mode period are connected to the first and second main power supply lines, respectively. During a predetermined period of the standby mode period, the bodies of the p-channel MOS transistor and the n-channel MOS transistor that are non-conductive during the standby mode period are fixed to the boosted potential and the step-down potential, respectively, and during other periods, the p-channel MOS transistor And the body of the n-channel MOS transistor is floated. Therefore, the subthreshold leakage current during the standby mode period can be reduced, and the operation speed during the active mode period can be improved. Further, the subthreshold leakage current of the p-channel MOS transistor and the n-channel MOS transistor can be further reduced by lowering the potential of the first sub power supply line and increasing the potential of the second sub power supply line in the standby mode period.

  Preferably, the bodies of the p-channel MOS transistor and the n-channel MOS transistor are fixed in a pulsed manner to the boosted potential and the step-down potential, respectively. In this case, the current consumption caused by fixing the body potential is minimized.

  [Embodiment 1]

FIG. 1 is a diagram for explaining the principle of Embodiment 1 of the present invention. In particular, FIG. 1 (a) is a diagram contrasted with FIG. 15, and FIG. 1 (b) is FIG. 1 (a). FIG. 7 is a diagram showing the potentials of p ⁻ type body region 82 and n ⁺ type source region 84 of n channel MOS transistor 72 shown in FIG.

In FIG. 15, when the threshold voltage of n channel MOS transistor 72 is lowered, the junction leakage current flowing from drain region 83 to body region 82 of n channel MOS transistor 72 in the non-conducting state during the standby mode period increases. potential rises of the body region 82, subthreshold leakage current I _L has been described to increase.

Therefore, in this embodiment, as shown in FIG. 1, a changeover switch 7 is provided, and in the standby mode period, a negative potential Vbb (Vbb <Vss) is applied to the n ⁺ -type source region 84 of the n-channel MOS transistor 72 and active In the mode period, the ground potential Vss is applied as usual. When negative potential Vbb is applied to n ⁺ type source region 84 of n channel MOS transistor 72 in the standby mode period, a forward bias is applied between p ⁻ type body region 82 and n ⁺ type source region 84. Therefore, p ^- accumulated positive charges on the type body region 82 flows out to the n ⁺ -type source region 84, p ^- potential type body region 82 is relatively reduced subthreshold leakage current I _L to decrease To do. In a p-channel MOS transistor that is in a non-conductive state in the standby mode period, a similar effect can be obtained by applying boosted potential Vpp (Vpp> Vcc) to its source region.

  FIG. 2 is a circuit diagram showing a main part of a semiconductor integrated circuit device to which the principle explained in FIG. 1 is applied.

  Referring to FIG. 2, this semiconductor integrated circuit device is formed on an SOI substrate, and a plurality of (three in the figure) CMOS inverters 1 to 3 and two change-over switches 6 and 7 connected in series. Is provided. Each of inverters 1 to 3 includes a p-channel MOS transistor 4 and an n-channel MOS transistor 5 connected in series between nodes N1 and N2. The input signal Vin is input to the first-stage inverter 1, and the output signal Vout is output from the final-stage inverter 3.

  The common terminal 6c of the changeover switch 6 is connected to the node N1, its one changeover terminal 6a receives the power supply potential Vcc, and the other changeover terminal 6b receives the boosted potential Vpp. The common terminal 7c of the changeover switch 7 is connected to the node N2, one of the changeover terminals 7a receives the ground potential Vss, and the other changeover terminal 7b receives the negative potential Vbb.

  3 and 4 are time charts for explaining the operation of the circuit shown in FIG. In the standby mode period, the terminals 6a and 6c of the changeover switch 6 are basically conducted, the terminals 7a and 7c of the changeover switch 7 are conducted, and the power supply potential Vcc and the ground potential Vss are respectively applied to the nodes N1 and N2. Given. The input signal Vin is fixed to the “L” level (ground potential Vss).

  Therefore, p channel MOS transistor 4 of inverters 1 and 3 and n channel MOS transistor 5 of inverter 2 are turned on, and n channel MOS transistor 5 of inverters 1 and 3 and p channel MOS transistor 4 of inverter 2 are turned off. Become.

At this time, as shown in FIG. 3, n-channel MOS body potential of the transistor 5 gradually increases subthreshold leakage current I _L of the inverter 1 and 3 is increased. Therefore, the changeover switch 7 is switched at a predetermined cycle for a predetermined period to apply a negative potential Vbb to the node N2, that is, the source of the n-channel MOS transistor 5 in a pulsed manner. Thus, the accumulated positive charge in the body region of the n-channel MOS transistor 5 is withdrawn through the source, body potential of n-channel MOS transistor 5 is subthreshold leakage current I _L decreases decreases.

Similarly, the body potential of the p-channel MOS transistor 4 of the inverter 2 is gradually lowered subthreshold leakage current I _L is increased. Therefore, selector switch 6 is switched in the same manner as selector switch 7 to apply boosted potential Vpp in a pulse manner to node N1, that is, the source of p-channel MOS transistor 4. Thus, the negative charges accumulated in the body region of the p-channel MOS transistor 4 is withdrawn through the source, body potential of the p-channel MOS transistor 4 is subthreshold leakage current I _L decreases and increases.

  In the active period, the terminals 6a and 6c of the changeover switch 6 are turned on, the terminals 7a and 7c of the changeover switch 7 are always turned on, and the nodes N1 and N2 are fixed at the power supply potential Vcc and the ground potential Vss, respectively.

  In the active period, as shown in FIG. 4, the input signal Vin, that is, the gate potential of the MOS transistors 4 and 5 of the inverter 1 rises from the “L” level to the “H” level. At this time, the body potential of the MOS transistors 4 and 5 rises rapidly to the “H” level by coupling with the gate, the p-channel MOS transistor 4 becomes non-conductive, the n-channel MOS transistor 5 becomes conductive, and the inverter 1 outputs “L” level. In response, inverter 2 outputs “H” level, inverter 3 outputs “L” level, and output signal Vout becomes “L” level.

In this embodiment, to reduce the subthreshold leakage current I _L by pulling out the electric charges accumulated in the body region of the MOS transistors 4 and 5 via its source in the standby mode. Therefore, compared to the conventional used to secure the body potential by the provided contact area 85 to reduce the subthreshold leakage current I _L, it is possible to achieve a reduction of the layout area.

  In this embodiment, the changeover switches 6 and 7 are changed in pulses in a predetermined cycle in the standby mode period. However, the present invention is not limited to this, and between the terminals 6b and 6c of the changeover switch 6 and in the standby mode period. The terminals 7b and 7c of the changeover switch 7 may be always connected. However, in this case, when the transition from the standby mode period to the active mode period is made, the operation time is delayed by the time when the node N1 is switched from the boosted potential Vpp to the power supply potential Vcc and the node N2 is switched from the negative potential Vbb to the ground potential Vss. In addition, the current consumption during the standby mode period increases.

  In this embodiment, the source potentials of the MOS transistors 4 and 5 are switched in the standby mode. However, the same effect can be obtained by switching in the power down mode, the battery backup mode, and the sleep mode.

  [Embodiment 2]

  FIG. 5 is a circuit diagram showing a configuration of a main part of the semiconductor integrated circuit device according to the second embodiment of the present invention.

  Referring to FIG. 5, this semiconductor integrated circuit device is formed on an SOI substrate and includes a plurality (three in the figure) of CMOS inverters 11-13 and switches 21-26 connected in series. Inverters 11-13 each include a p-channel MOS transistor 14 and an n-channel MOS transistor 15 connected in series between nodes N11 and N12. The input signal Vin is input to the first-stage inverter 11, and the output signal Vout is output from the final-stage inverter 13.

  One terminal of each of switches 21-23 is connected to the body of p channel MOS transistor 14 of inverters 11-13, respectively, and the other terminal thereof receives boosted potential Vpp. One terminal of each of switches 24-26 is connected to the body of n-channel MOS transistor 15 of inverters 11-13, respectively, and each of the other terminals receives negative potential Vbb.

  Next, the operation of the circuit shown in FIG. 5 will be described. In the standby mode period, all the switches 21 to 26 are turned on, the body of the p channel MOS transistor 14 of the inverters 11 to 13 is fixed to the boosted potential Vpp, and the body of the n channel MOS transistor 15 is fixed to the negative potential Vbb. The In the active mode period, all the switches 21 to 26 are turned off, and the bodies of the MOS transistors 14 and 15 of the inverters 11 to 13 are in a floating state. The operation of the inverter trains 11 to 13 is the same as that of the inverter trains 1 to 3 shown in FIG.

In this embodiment, the body potential is fixed subthreshold leakage current I _L of the MOS transistors 14 and 15 is reduced in the standby mode, and the body of the MOS transistors 14 and 15 are floating in an active mode period Body As a result, the capacitance value between the source / drain is reduced and the switching speed is increased. Therefore, both reduction in current consumption and increase in operating speed are realized.

  In this embodiment, boosted potential Vpp is applied to the body of p channel MOS transistor 14 and negative potential Vbb is applied to the body of n channel MOS transistor 15 in the standby mode period. The potential Vcc may be applied and the ground potential Vss may be applied to the body of the n-channel MOS transistor 15.

  Further, in this embodiment, the switches 21 to 26 are turned on during the entire standby mode period. However, similarly to the first embodiment, the switches 21 to 26 may be turned on in pulses at predetermined intervals. .

  [Embodiment 3]

  FIG. 6 is a circuit diagram showing a structure of a main part of a semiconductor integrated circuit device according to the third embodiment of the present invention.

  Referring to FIG. 6, this semiconductor integrated circuit device is formed on an SOI substrate, and a plurality of (three in the figure) CMOS inverters 31-33, p-channel MOS transistor 36, n, Channel MOS transistor 37. Each of inverters 31 to 33 includes a p-channel MOS transistor 34 and an n-channel MOS transistor 35 connected in series between local power supply lines LL31 and LL32. The input signal Vin is input to the first-stage inverter 31, and the output signal Vout is output from the final-stage inverter 33.

  P channel MOS transistor 36 is connected between main power supply line ML31 and local power supply line LL31, and has its gate receiving activation signal / φa. N channel MOS transistor 37 is connected between main power supply line ML32 and local power supply line LL32, and its gate receives activation signal φa. Main power supply lines ML31 and ML32 are supplied with power supply potential Vcc and ground potential Vss, respectively.

  In the active period, when activation signals / φa and φa attain “L” level and “H” level of activation levels, MOS transistors 36 and 37 are rendered conductive, and inverters 31 to 33 are activated.

In this circuit, inverters 31-33 are disconnected from power supply potential Vcc and ground potential Vss during the standby mode period. Therefore, even if the sub-threshold leakage current I _L to the MOS transistors 34 and 35 constituting the inverter 31 to 33 flows, as long as the previously set high threshold voltage of the MOS transistors 36 and 37, current flows to the power supply There is nothing. Therefore, current consumption in the standby mode period can be reduced.

The circuit itself (excluding the points formed on the SOI substrate) is “1V High-Speed Digital Circuit Technology with 0.5 μm Multi-Theshold CMOS,” Proc. IEEE
As described in ASIC Conf., 1993, pp 186-189, if the present invention is applied to this circuit, higher performance can be achieved.

That is, as described in the above-mentioned document, simply setting the activation signals / φa and φa to the inactive level during the standby period and simply setting the activation signals / φa and φa to the activation level during the active mode period. As shown in FIG. 8, due to the subthreshold leakage current I _L , the potential Vcc ′ of the local power supply line LL31 gradually decreases and the potential Vss ′ of the local power supply line LL32 gradually increases in the standby mode period. For this reason, when the active mode is entered next, it takes time to restore the potentials of the local power supply lines LL31 and LL32 to the power supply potential Vcc and the ground potential Vss, respectively.

  Therefore, in this embodiment, as shown in FIG. 7, even in the standby mode period, activation signals / φa and φa are pulsed to an activation level in a predetermined cycle, and MOS transistors 36 and 37 are pulsed. Thus, the potentials of the local power supply lines LL31 and LL32 are kept constant at the power supply potential Vcc and the ground potential Vss, respectively.

This can reduce the body potential of the n-channel MOS transistor 35 raises the body potential of the p-channel MOS transistor 34 achieve a reduction of subthreshold leakage current I _L of the MOS transistors 34 and 35, and the standby You can quickly transition from mode to active mode.

  [Embodiment 4]

  FIG. 9 is a circuit diagram showing a structure of a main part of a semiconductor integrated circuit device according to the fourth embodiment of the present invention.

  Referring to FIG. 9, the semiconductor integrated circuit device is different from the semiconductor integrated circuit device shown in FIG. 6 in that n channel MOS transistors 35 and inverters 32 of inverters 31 and 33 which are in a non-conductive state during the standby mode period. Corresponding to the p-channel MOS transistor 34, switches 38 to 40 are newly provided. One terminal of switch 38 is connected to the body of n-channel MOS transistor 35 of inverter 31, and the other terminal receives negative potential Vbb. One terminal of switch 39 is connected to the body of p channel MOS transistor 34 of inverter 32, and the other terminal receives boosted potential Vpp. One terminal of switch 40 is connected to the body of n-channel MOS transistor 35 of inverter 33, and the other terminal receives negative potential Vbb.

  Next, the operation of the circuit shown in FIG. 9 will be described. In the standby mode period, switches 38 to 40 are turned on, the body potential of n channel MOS transistor 35 of inverters 31 and 33 is fixed to negative potential Vbb, and the body potential of p channel MOS transistor 34 of inverter 32 is set to boosted potential Vpp. Fixed. In the active mode period, the switches 38 to 40 are in a non-conductive state, and the bodies of the MOS transistors 34 and 35 of the inverters 31 to 33 are in a floating state. Other operations are the same as those of the circuits shown in FIGS.

  Also in this embodiment, the same effect as in the second embodiment can be obtained.

  [Embodiment 5]

  FIG. 10 is a circuit diagram showing a structure of a main part of a semiconductor integrated circuit device according to the fifth embodiment of the present invention.

  Referring to FIG. 10, this semiconductor integrated circuit device includes a plurality (four in the figure) of CMOS inverters 41 to 44 formed on an SOI substrate and connected in series. Each of inverters 41 and 43 includes p channel MOS transistor 45 and n channel MOS transistor 46 connected in series between main power supply line ML41 and local power supply line LL41. Each of inverters 42 and 44 includes a p-channel MOS transistor 45 and an n-channel MOS transistor 46 connected in series between local power supply line LL41 and main power supply line ML42. Local power supply wiring LL41 is supplied with power supply potential Vcc via main power supply wiring ML41. The ground potential Vss is applied to the local power supply line LL42 via the main power supply line ML42.

  The input signal Vin is input to the first-stage inverter 41, and the output signal Vout is output from the final-stage inverter 44. The input signal Vin is fixed at the “L” level during the standby mode period, and is at the “H” level during the active mode period.

In this circuit, for example, the gate of n channel MOS transistor 46 of inverter 43 receives ground potential Vss from main power supply line ML42 and its source receives ground potential Vss from local power supply line LL42 in the standby mode period. When the subthreshold leakage current I _L of the n-channel MOS transistor 46 and the potential Vss' of the local power supply line LL42 rises, the gate potential of the n-channel MOS transistor 46 becomes lower than its source potential, subthreshold leakage current I _L Is reduced. p-channel MOS transistor 45 even subthreshold leakage current I _L for the same reason can be reduced.

This circuit itself (excluding the point formed on the SOI substrate) is described in 1993 Symposium on VLSI Circuit Dig. Of Tech Papers pp. 47-48. If the present invention is applied to this circuit, , it is possible to further reduce the subthreshold leakage current I _L.

  That is, this semiconductor integrated circuit device is further provided with changeover switches 47 and 48. The common terminal 47c of the changeover switch 47 is connected to the local power supply line LL41, one of the changeover terminals 47a is connected to the main power supply line ML41, and the other changeover terminal 47b receives the boosted potential Vpp. The common terminal 48c of the changeover switch 48 is connected to the local power supply line LL42, one of the changeover terminals 48a is connected to the main power supply line ML42, and the other changeover terminal 48b receives the negative potential Vbb.

As illustrated in FIG. 11, the potential Vss' of the local power supply line LL42 is increased by the subthreshold leakage current I _L in the standby mode period, the sub-threshold body potential of n-channel MOS transistor 46 of the inverter 41, 43 is increased when Doriku current I _L has increased, giving in pulses of negative potential Vbb to local power supply line LL42 by switching only the switch 48 predetermined interval of time. This makes it possible to reduce the body potential of the p-channel MOS transistor 46 of the inverter 41 and 43 is reduced the subthreshold leakage current I _L.

Similarly, decreases the potential Vcc 'of local power supply line LL41 by subthreshold leakage current I _L in the standby mode period, subthreshold leakage current body potential of the p-channel MOS transistor 45 of the inverter 42 is lowered is When the voltage increases, the switch 47 is switched for a predetermined time to apply the boosted potential Vpp to the local power supply line LL41 in a pulsed manner. This makes it possible to reduce the body potential of the p-channel MOS transistor 45 of the inverter 42, 44 is reduced the subthreshold leakage current I _L.

  Also in this embodiment, the same effect as in the first embodiment can be obtained.

  If potential Vss 'of local power supply line LL42 becomes too lower than ground potential Vss, n channel MOS transistor 46 that should be in a non-conductive state is turned on, and potential Vcc' of local power supply line LL41 is higher than power supply potential Vcc. If it becomes too large, p channel MOS transistor 45 that should be in a non-conductive state will be conductive, so negative potential Vbb and boosted potential Vpp are set to appropriate values so that MOS transistors 45 and 46 that should be in a non-conductive state are not conductive. There is a need.

  [Embodiment 6]

  FIG. 12 is a circuit diagram showing a structure of a main part of a semiconductor integrated circuit device according to the sixth embodiment of the present invention.

  Referring to FIG. 12, this semiconductor integrated circuit device is different from the semiconductor integrated circuit device of FIG. 10 in that switches 47 and 48 are removed and local power supply lines LL41 and LL42 are directly connected to main power supply lines ML41 and ML42, respectively. And switches 51 to 54 are newly provided. One terminal of each of switches 51 and 53 is connected to the body of n-channel MOS transistor 46 of inverters 41 and 43, respectively, and the other terminal thereof receives negative potential Vbb. One terminal of each of switches 52 and 54 is connected to the body of p channel MOS transistor 45 of inverters 42 and 44, respectively, and the other terminal thereof receives boosted potential Vpp.

  Next, the operation of the circuit shown in FIG. 12 will be described. In the standby mode period, switches 51-54 are turned on, the body of n channel MOS transistor 46 of inverters 41 and 43 is fixed at negative potential Vbb, and the body of p channel MOS transistor 45 of inverters 42 and 44 is boosted potential Vpp. Fixed to. In the active mode period, the switches 51 to 54 are in a non-conductive state, and the bodies of the MOS transistors 45 and 46 of the inverters 41 to 43 are in a floating state.

  Also in this embodiment, the same effect as in the second embodiment can be obtained.

It is a figure for demonstrating the principle of Embodiment 1 of this invention. FIG. 2 is a circuit diagram showing a configuration of a main part of a semiconductor integrated circuit device to which the principle shown in FIG. 1 is applied. 3 is a time chart for explaining the operation of the circuit shown in FIG. 2. 6 is another time chart for explaining the operation of the circuit shown in FIG. 2. It is a circuit diagram which shows the structure of the principal part of the semiconductor integrated circuit device by Embodiment 2 of this invention. It is a circuit diagram which shows the structure of the principal part of the semiconductor integrated circuit device by Embodiment 3 of this invention. 7 is a time chart for explaining the operation of the circuit shown in FIG. 6. It is a figure for demonstrating the effect of the circuit shown in FIG. It is a circuit diagram which shows the structure of the principal part of the semiconductor integrated circuit device by Embodiment 4 of this invention. It is a circuit diagram which shows the structure of the principal part of the semiconductor integrated circuit device by Embodiment 5 of this invention. It is a time chart for demonstrating operation | movement of the circuit shown in FIG. It is a circuit diagram which shows the structure of the principal part of the semiconductor integrated circuit device by Embodiment 6 of this invention. It is a circuit diagram which shows the structure of the CMOS inverter of the conventional semiconductor integrated circuit device. It is a figure which shows the device structure of the n channel MOS transistor shown in FIG. It is a figure for demonstrating the problem of the circuit shown in FIG. FIG. 14 is a diagram showing another device structure of the n-channel MOS transistor shown in FIG. 13.

Explanation of symbols

1-3, 11-13, 31-33, 41-44, 70 CMOS inverter, 4, 14, 34, 36, 45, 71 p-channel MOS transistor, 5, 15, 35, 37, 46, 72 n-channel MOS Transistor, 6, 7, 21-26, 38-40, 47, 48, 51-54 switch, 73 SOI substrate, 74 silicon substrate, 75 SiO buried oxide layer, 76 p ^- type silicon layer, 77 SiO insulating layer, 81 gate electrode, 82 p ⁻ type body region, 83 n ⁺ type drain region, 84 n ⁺ type source region, 85 p ⁺ type contact region.

Claims (6)

A semiconductor device formed on an SOI substrate and having a standby mode and an active mode,
A MOS transistor including a source region, a drain region, and a body region located between the two regions; and a predetermined period of the standby mode period fixes the body region of the MOS transistor at a predetermined potential; A semiconductor device comprising body potential switching means for floating the body region during other periods.   2. The semiconductor device according to claim 1, wherein the body potential switching unit pulse-fixes the body region at the predetermined potential in a predetermined cycle during the standby mode period. A semiconductor device formed on an SOI substrate and having a standby mode and an active mode,
A plurality of inverter circuits connected in series, each including a p-channel MOS transistor and an n-channel MOS transistor connected in series between the first and second power supply potential lines;
A predetermined period of the standby mode period includes a body region between a source region and a drain region of a p-channel MOS transistor that is non-conductive during the standby mode period of the plurality of inversion circuits. A first body potential switching means that fixes the boosted potential to a potential equal to or higher than the potential and floats the body region during other periods; and a predetermined period of the standby mode period includes the standby circuit of the plurality of inversion circuits. The body region between the source region and the drain region of the n-channel MOS transistor that becomes non-conductive during the mode period is fixed to a step-down potential equal to or lower than the second power supply potential, and the body region is floated during other periods. A semiconductor device comprising two body potential switching means. A semiconductor device formed on an SOI substrate and having a standby mode and an active mode,
A first main power supply line to which a first power supply potential is applied from the outside;
A first sub power supply line provided corresponding to the first main power supply line;
A second main power supply line to which a second power supply potential is applied from the outside;
A second sub power supply line provided corresponding to the second main power supply line;
A plurality of inverter circuits connected in series, each including a p-channel MOS transistor and an n-channel MOS transistor connected in series between the first and second sub-power supply lines;
A first connection that is connected between the first main power supply line and the first sub power supply line and that conducts during the active mode period and applies the first power supply potential to the first sub power supply line. means,
A second connection connected between the second main power supply line and the second sub power supply line and conducting during the active mode period to apply the second power supply potential to the second sub power supply line. means,
Of the plurality of inversion circuits, provided corresponding to a p-channel MOS transistor that is non-conductive during the standby mode period, the predetermined period of the standby mode period is the source region and drain of the corresponding p-channel MOS transistor A body region between the regions is fixed to a boosted potential equal to or higher than the first power supply potential, and during other periods, the first body potential switching means for floating the body region; and Provided corresponding to the n-channel MOS transistor that is rendered non-conductive during the standby mode period, a predetermined period of the standby mode period includes a body region between the source region and the drain region of the corresponding n-channel MOS transistor. The step-down potential is fixed to the second power supply potential or lower, and during other periods A semiconductor device comprising second body potential switching means for floating the body region. A semiconductor device formed on an SOI substrate and having a standby mode and an active mode,
A plurality of inverting circuits connected in series, each including a p-channel MOS transistor and an n-channel MOS transistor with their drains connected;
A first main power supply line externally supplied with a first power supply potential and connected to a source of a p-channel MOS transistor that is conductive during the standby mode period of the plurality of inversion circuits;
A second main power supply line externally supplied with a second power supply potential and connected to a source of an n-channel MOS transistor that is conductive during the standby mode period of the plurality of inversion circuits;
A first sub-power supply that is supplied with the first power supply potential from the first main power supply line and is connected to the source of a p-channel MOS transistor that becomes non-conductive during the standby mode period of the plurality of inversion circuits. line,
A second sub-power supply that is supplied with the second power supply potential from the second main power supply line and is connected to the source of an n-channel MOS transistor that becomes non-conductive during the standby mode period of the plurality of inversion circuits. line,
Of the plurality of inverting circuits, provided corresponding to a p-channel MOS transistor that is non-conductive during the standby mode period, the predetermined period of the standby mode period is the source region and drain of the corresponding p-channel MOS transistor A body region between the regions is fixed to a boosted potential equal to or higher than the first power supply potential, and during other periods, the first body potential switching means for floating the body region; and Provided corresponding to the n-channel MOS transistor that becomes non-conductive during the standby mode period, the predetermined period of the standby mode period is a body region between the source region and the drain region of the corresponding n-channel MOS transistor. The drop potential is fixed to the second power supply potential or lower, and during other periods A semiconductor device comprising second body potential switching means for floating the body region. The first body potential switching means pulse-fixes the body region of the p-channel MOS transistor to the boosted potential at a predetermined cycle in the standby mode period,
The second body potential switching means pulse-fixes the body region of the n-channel MOS transistor at the step-down potential in a predetermined cycle in the standby mode period. The semiconductor device described.

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