JP2007329257A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify a process through which a polysilicon electrode and a contact for a silicon substrate are formed as located at different depths in a silicon oxide film in a semiconductor device. <P>SOLUTION: A silicide film 102 is formed on the surface of a third-layered polysilicon electrode 100. A silicon oxide film 92 laminated thereon is etched to form contact openings for the polysilicon electrode 100, and the diffusion layer (FD 52) of a silicon substrate 80 at the same time. In the etching process, etching of a contact groove 96 is stopped at the silicide film 102 until a contact groove 110 reaches the FD 52 after the contact groove 96 reaches to the silicide film 102. The contact openings different in depth from each other are filled up with tungsten so as to connect the polysilicon electrode 100 and the FD 52 to Al electrodes 98 and 114 respectively. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device, and more particularly to formation of contacts to silicon portions located at different depths.

  In a semiconductor element formed using a silicon substrate, electrodes and wirings are formed using a plurality of polysilicon layers on the substrate. For example, in a CCD (Charge Coupled Device) image sensor, a transfer electrode of a CCD shift register is formed using a first layer polysilicon (1 poly-Si) film and a second layer polysilicon (2 poly-Si) film. The Further, the transfer electrode of the vertical CCD shift register is composed of 1poly-Si and 2poly-Si, and a backing wiring structure using a third-layer polysilicon (3poly-Si) film is also formed. After forming each of these polysilicon layers, an insulating layer made of a silicon oxide film or the like is laminated, and a metal wiring is formed thereon. The transfer electrode formed using each polysilicon layer and the diffusion layer formed on the surface of the silicon substrate are connected to the metal wiring through an opening such as a contact hole provided in the insulating layer laminated thereon. Is done.

  Incidentally, with the improvement of the degree of integration of semiconductor elements, it is necessary to reduce the dimensions of wiring and contacts. As a structure effective for miniaturization, a tungsten plug in which tungsten (W) is buried in a contact hole as a contact material is known. Also in the CCD image sensor, as the resolution is increased and the chip size is reduced, a contact with a silicon substrate or a polysilicon electrode is formed with tungsten.

  For example, a 3poly-Si wiring having a backing wiring structure is extended on a channel isolation region between adjacent vertical shift registers. A contact groove extending along the 3poly-Si wiring is formed in the insulating layer on the 3poly-Si wiring, and tungsten is buried in the contact groove. The 3poly-Si wiring is connected to a metal wiring for supplying a clock signal through a tungsten wiring.

FIG. 6 is a schematic cross-sectional view showing the structure of a conventional contact. This figure shows the structure of the contact to the silicon substrate 200 and the contact to the 3poly-Si wiring 202. A diffusion layer 204 is formed on the surface of the silicon substrate 200, and a vertical transfer electrode 208 made of 1poly-Si or 2poly-Si is formed thereon via a silicon oxide film (SiO ₂ film) 206. Further, a SiO ₂ film 210 is laminated thereon, and then a 3poly-Si wiring 202 is formed. A SiO ₂ film 212 is laminated on the 3poly-Si wiring 202, and tungsten is buried in an opening provided in the SiO ₂ film 212. This tungsten is electrically connected to a metal wiring (not shown) using aluminum (Al) or the like. Specifically, a contact groove 218 is formed on the 3poly-Si wiring 202, and tungsten 220 is embedded in the contact groove 218. A contact hole 222 is formed on the diffusion layer 204, and a tungsten plug 224 is embedded in the contact hole 222. The tungsten plug 224 is connected to a metal wiring 216 using aluminum or the like.

These contact grooves 218 and contact holes 222 are formed by performing an etching process after forming an etching mask on the SiO ₂ film 212.

  The silicon oxide film laminated on the silicon substrate 200 and the silicon oxide film laminated on each polysilicon layer have different thicknesses. That is, it is necessary to form contact holes or contact grooves having different depths. For example, the contact groove 218 for the 3poly-Si wiring 202 shown in FIG. 6 is shallower than the contact hole 222 for the diffusion layer 204. As described above, the openings having different depths can be formed by, for example, etching processes in separate steps. However, in this method, it is necessary to perform an etching process including a series of processes such as formation of an etching mask, etching process, and removal of the etching mask a plurality of times, and there is a problem in that device manufacturing throughput may be reduced and cost may be increased. there were.

  On the other hand, it is conceivable that openings having different depths are formed in a single etching process by utilizing the difference in etching selectivity. However, in the silicon oxide film etching process, it is relatively difficult to ensure a selection ratio with respect to polysilicon. In particular, as the depth difference is larger, such as the contact groove 218 for the 3poly-Si wiring and the contact hole 222 for the diffusion layer 204, a higher selection ratio is required, which makes it difficult to set the etching conditions. there were.

  The present invention has been made to solve the above-described problems. In a semiconductor device in which silicon portions such as polysilicon wirings or silicon substrates are formed at different depths under an insulating layer, formation of contacts to these silicon portions is performed. The present invention relates to a manufacturing method that facilitates

  According to the method of manufacturing a semiconductor device of the present invention, the insulating layer stacked on the semiconductor substrate is etched to reach the first silicon portion to the first thickness of the insulating layer existing on the first silicon portion. An opening forming step of forming one opening and forming a second opening reaching the second silicon portion in the insulating layer having a second thickness smaller than the first thickness existing on the second silicon portion; A metal film forming step of laminating a metal film covering the second silicon portion; and reacting the second silicon portion and the metal film to selectively form a surface of the second silicon portion. A step of forming an opening; and a step of forming a silicide film, and a step of laminating an insulating layer of the second thickness on the second silicon portion on which the silicide film is formed. Is the second opening While the Oite the silicide film as an etching stopper, a method of forming the second opening.

  The second opening is shallower than the first opening, and when the insulating layer is etched to form these openings, the second opening reaches the target depth before the first opening. According to the present invention, the silicide film is formed in advance on the surface of the second silicon portion that appears at the bottom of the second opening. The formation of the silicide film can be self-aligned by using a salicide process. In the etching process for silicon oxide, it is easier to ensure a selectivity relative to silicide than to polysilicon or a silicon substrate. That is, even when the difference in depth between the first opening and the second opening is relatively large, etching at the bottom of the second opening is performed with the silicide film until the first opening reaches the target depth. Easy to fasten.

  The manufacturing method further includes depositing a metal film after the opening forming step, and connecting the metal wiring electrically connected to the first silicon portion and the second silicon portion to the first opening and the second. It may include a metal wiring forming process formed in the opening.

  The manufacturing method of the present invention can be suitably applied to a semiconductor device in which the second silicon portion is a polysilicon wiring and the insulating layer is a silicon oxide film.

  The manufacturing method of the present invention includes a charge coupled device in which a charge transfer region is formed on a silicon substrate, wherein the first silicon part is a diffusion layer in the silicon substrate, and the second silicon part is a transfer electrode. The present invention can be suitably applied to a semiconductor device that is a polysilicon wiring for supplying a clock signal and the insulating layer is a silicon oxide film.

  According to the present invention, the first opening and the second opening can be formed by a single etching process, and the contact formation process becomes simple and easy.

  Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

  FIG. 1 is a schematic plan view showing a schematic configuration of a CCD image sensor according to an embodiment. FIG. 2 is a schematic plan view showing a schematic arrangement of polysilicon electrodes and contacts in the CCD image sensor.

  The CCD image sensor 20 is a frame transfer method, and includes an imaging unit 20i, a storage unit 20s, a horizontal transfer unit 20h, and an output unit 20d formed on the surface of a semiconductor substrate.

  The imaging unit 20i includes a plurality of vertical shift registers (vertical CCD shift registers) 22i arranged in the row direction (horizontal direction). The storage unit 20s includes a plurality of vertical shift registers 22s that correspond one-to-one with the plurality of vertical shift registers 22i of the imaging unit 20i. The plurality of vertical shift registers 22s are arranged in the row direction, and each has a charge transfer channel continuous with the corresponding vertical shift register 22i.

  Each bit of the vertical shift register 22i of the imaging unit 20i constitutes a light receiving pixel, and generates and accumulates signal charges according to incident light. The signal charges accumulated in the exposure period in the imaging unit 20i are vertically transferred to the accumulation unit 20s at high speed by the frame transfer operation. The accumulating unit 20s is covered with a light shielding film and prevents charge generation due to the incidence of light, so that the signal charges from the image capturing unit 20i transferred by the frame can be basically held as they are.

Each of the vertical shift registers 22i and 22s includes vertical transfer electrodes 24i and 24s that are transferred in the row direction on the substrate and arranged in parallel in the column direction as transfer electrodes. The vertical transfer electrodes 24i and 24s are polysilicon electrodes, and are formed using, for example, 1poly-Si and 2poly-Si. The vertical transfer electrodes 24i and 24s are connected to the clock signal line through contacts 26 provided at both ends. The vertical transfer electrodes 24i and 24s control the potential of the charge transfer channel formed on the semiconductor substrate in accordance with the transfer clocks φ _I and φ _S of a plurality of phases applied from the drive circuit via the clock signal line. For example, in the CCD image sensor 20, nine transfer electrodes for every three consecutive bits of the vertical CCD shift registers 22 i and 22 s are driven independently of each other in order to enable shooting with moving picture and pixel compression in preview. Configured to be possible. Correspondingly, nine clock signal lines are arranged for each of the imaging unit 20i and the storage unit 20s, and the vertical transfer electrodes 22i and 22s arranged in the column direction are respectively connected to the same clock signal line in a cycle of nine. The

The drive circuit controls the transfer clocks φ _{I1 to} φ _I9 supplied to the clock signal line of the imaging unit 20 i and the transfer clocks φ _{S1 to} φ _S9 supplied to the clock signal line of the storage unit 20 s to capture the still image and the moving image Switch between shooting and preview. For example, in still image shooting, standard driving, which is three-phase driving with three transfer electrodes for each bit as separate phases, is performed. On the other hand, in moving image shooting and preview, pixel compression driving is performed in which frame transfer is performed after signal charge addition and synthesis processing is performed on three consecutive pixels in the column direction of the imaging unit 20i.

  In general, the vertical transfer electrode is relatively long in the horizontal direction, and the width (vertical dimension) becomes finer as the pixel density increases. Therefore, the waveform of the transfer clock applied from both ends of the horizontal transfer electrode is broken toward the center, which may cause problems such as deterioration in transfer efficiency. In order to avoid this, a separate clock signal line is formed on the channel separation region between the vertical shift registers adjacent in the row direction. The clock wiring forms a backing wiring configuration and is provided in a row in the row direction. Each backing wiring is connected to a corresponding one of the vertical transfer electrodes crossing the wiring via a contact. Each vertical transfer electrode is connected to the backing wiring at a position in the middle of the row direction, and can receive the transfer clock from the drive circuit via the backing wiring, so the waveform of the transfer clock according to the position in the row direction It is possible to suppress the difference.

  The CCD image sensor 20 has a backing wiring in each of the imaging unit 20i and the storage unit 20s. The backing wiring has a structure in which an underlying wiring 28 formed by patterning a polysilicon layer and a tungsten wiring 30 are laminated. The underlying wiring 28i is arranged across the column direction on the imaging unit 20i in which the vertical transfer electrode 24i is formed. For example, the underlying wiring 28i is formed using 3poly-Si. Its formation will be described later. The tungsten wiring 30i has a structure embedded in a contact trench formed in a silicon oxide film on 3poly-Si. The contact groove extends in the column direction on the underlying wiring 28i and penetrates to the surface of the underlying wiring 28i. In the storage unit 20s, a backing wiring in which the underlying wiring 28s and the tungsten wiring 30s are stacked is formed in the same manner as the backing wiring of the imaging unit 20i.

The horizontal transfer unit 20h is composed of a CCD shift register, and each bit thereof is connected to the output end of the charge transfer channel of the vertical shift register 22s. For example, a pair of horizontal transfer electrodes 40 and 42 is arranged for each bit. For example, the horizontal transfer electrode 40 is made of 1 poly-Si, and the horizontal transfer electrode 42 is made of 2 poly-Si. A barrier region having a channel potential shallower than that under the horizontal transfer electrode 40 is formed under the horizontal transfer electrode 42, thereby forming a channel potential gradient toward the output unit 20 d under each horizontal transfer electrode pair. The paired horizontal transfer electrodes 40 and 42 are connected to a common clock signal line via a contact 44. Each electrode pair controls the potential of the charge transfer channel formed in the semiconductor substrate in accordance with a plurality of phase transfer clocks φ _H applied from the drive circuit. For example, the horizontal transfer clock phi _H1 of the horizontal transfer section 20h is 2-phase driven by phi _H2.

The output unit 20d includes an output gate electrode (OG) 50, a floating diffusion layer (FD) 52, a reset gate electrode (RG) 54, a reset drain (RD) 56, and an output amplifier 58. The OG 50 is connected via a contact 60 to a signal line that supplies a predetermined voltage V _OG . The FD 52 constitutes an electrically independent capacitor. The FD 52 is transferred with a signal charge from the horizontal transfer unit 20h via the charge transfer channel under the OG 50, and has a potential corresponding to the amount of signal charge. The potential of the FD 52 is taken out to the signal line through the contact 62 and input to the output amplifier 58 as a voltage signal. The output amplifier 58 amplifies the input voltage signal and outputs the output signal _VOUT of the CCD image sensor 20. RG54 via the contact 64 is connected to a signal line for supplying a clock signal phi _RG. The RD 56 is connected to a signal line through a contact 66, and the signal line is connected to a predetermined positive voltage power supply _VRD . FD 52, RG54 and RD56 constitute a MOS transistor, when turned on by phi _RG, the signal charge accumulated in the FD 52 is discharged to the positive voltage source _{V RD} via the RD56.

  Here, the contact structure of the backing wiring composed of the contact groove and the tungsten wiring 30i is formed by a process common to the contact 62 for the FD 52. Hereinafter, this process will be described. FIG. 3 is a schematic cross-sectional view showing the cross-section 70 of the contact structure for the underlay wiring 28 and the cross-section 72 of the contact 62 for the FD 52 side by side. Here, the cross section 70 represents, for example, a vertical cross section along the row direction in the imaging unit 20i.

As the silicon substrate 80, for example, a silicon semiconductor substrate (N-sub) containing n-type impurities is used. Various diffusion layers are formed on the surface of the silicon substrate 80 by ion implantation or thermal diffusion of n-type or p-type impurities. For example, a p-well (PW) 82 in which p-type impurities are diffused is formed in almost the entire CCD image sensor 20. In the cross section 70, an n-well (NW) is formed as a channel region 84 of the vertical shift register 22i, and ap ⁺ region is formed as a channel isolation region 86 between adjacent channel regions. The FD 52 is an n ⁺ region and is formed by injecting an n-type impurity into the surface of the silicon substrate 80. A silicon oxide film 90 is deposited on the silicon substrate 80 as an insulating film serving as a base of 3poly-Si, and a silicon oxide film 92 is deposited on the 3poly-Si as an insulating film serving as a base of the Al wiring. .

  In the imaging unit 20i, a vertical transfer electrode 24i disposed across a plurality of vertical shift registers 22i is formed using 1poly-Si and 2poly-Si. On the channel isolation region 86, a backing wiring structure 94 is formed extending in the column direction (the normal direction in FIG. 3). The backing wiring structure 94 includes a contact groove 96 provided in the silicon oxide film 92, an underlying wiring 28 i located on the bottom surface of the contact groove 96, and a tungsten wiring 30 i embedded in the contact groove 96. The tungsten wiring 30i is connected to an Al wiring (not shown) outside the imaging unit 20i. The underlying wiring 28i is formed using 3poly-Si as described above, and a silicide film is formed on the surface by a process described later. That is, the underlying wiring 28i includes the polysilicon wiring 100 and the silicide film 102 covering the surface thereof.

  Since the silicide film is light-shielding and low-reflectivity, color mixing between adjacent channels can be prevented by forming a silicide film on the surface of the underlying wiring 28i formed on the channel isolation region 86. That is, according to this configuration, the silicide film 102 is formed wider than the tungsten wiring 30i at a lower position nearer to the channel isolation region than the tungsten wiring 30i. The tungsten wiring 30i in the contact groove 96 forms a wall with respect to the oblique incident light, and prevents the oblique incident light from entering the adjacent channel. In addition to this, in this configuration, the silicide film 102 more effectively blocks the incidence of the obliquely incident light on the adjacent channel based on its light shielding property and low reflectivity, position and shape. As a result, in this configuration, color mixing between adjacent channels can be suitably prevented as described above.

  On the other hand, the contact 62 with respect to the FD 52 includes a contact hole 110 that reaches the FD 52 through the silicon oxide films 90 and 92, and a tungsten plug 112 embedded in the contact hole 110, and is disposed on the tungsten plug 112. The Al wiring 114 and the FD 52 are electrically connected.

  Next, a manufacturing method of the CCD image sensor 20 will be described with reference to FIGS. 4 and 5 are diagrams for explaining main processes according to the present invention in the manufacturing method of the CCD image sensor 20, and show schematic cross-sectional views in each process of forming the backing wiring structure 94 and the contact 62. FIG. ing. 4 and 5, some of the configuration shown in FIG. 3 is omitted for simplification.

  In FIG. 4A, a 1poly-Si electrode and a 2poly-Si electrode (not shown) constituting the vertical transfer electrode 24i are sequentially formed on a silicon substrate 80 on which the FD 52 is formed, and a silicon oxide film 90 is laminated. Thereafter, a state in which the 3poly-Si film 120 is deposited by, for example, CVD (Chemical Vapor Deposition) is shown.

  By patterning the 3poly-Si film 120 using a photoresist method, a polysilicon wiring 100 made of the 3poly-Si film is formed at a position corresponding to the underlying wiring 28 (FIG. 4B).

  Titanium (Ti) is deposited on the silicon oxide film 90 on which the polysilicon wiring 100 is formed by sputtering to form a Ti film 122. By this step, the Ti film 122 is deposited on the surface of the polysilicon wiring 100 (FIG. 4C).

Silicide is formed on the surface of the polysilicon wiring 100 in a self-aligned manner by a salicide process using the Ti film 122. This silicide formation is realized by heat treatment in an N ₂ atmosphere. The heat treatment can be performed by, for example, RTA (Rapid Thermal Annealing). If RTA is used, the heat treatment can be completed in a short time, and the diffusion layer already formed in the silicon substrate 80 can be prevented from unnecessarily spreading. By the heat treatment, a silicidation reaction occurs on the surface of the polysilicon wiring 100, and a Ti silicide film 102 is selectively formed on the surface of the polysilicon wiring 100. On the other hand, the Ti film 122 in contact with the surface of the silicon oxide film 90 remains without being silicided. The remaining Ti film 122 is removed by, for example, a cleaning process using ammonia overwater, and the silicon oxide film 90 is exposed. As a result, the underlying wiring 28 composed of the polysilicon wiring 100 and the Ti silicide film 102 covering the surface is formed on the surface of the silicon oxide film 90 (FIG. 4D).

  A silicon oxide film 92 is further deposited as an insulating film on the silicon oxide film 90 on which the underlying wiring 28 is formed. Photoresist is applied to the surface of the silicon oxide film 92 and patterned to form an etching mask 124 for forming contact holes and the like (FIG. 5A).

  The etching mask 124 has openings at positions where the contact holes 110 and the contact grooves 96 are to be formed. The silicon oxide films 92 and 90 are etched using this etching mask. For example, the silicon oxide film etching is performed by RIE (Reactive Ion Etching) or the like. First, etching of the upper silicon oxide film 92 proceeds from the opening of the etching mask 124, and a contact groove 96 reaching the underlying wiring 28 is formed (FIG. 5B).

  At this stage, the contact hole 110 ′ for the FD 52 has not yet reached the FD 52, and the etching of the silicon oxide film is further continued. As a result, the contact hole 110 ′ becomes deeper and reaches the FD 52 to complete the contact hole 110 (FIG. 5C). During this time, in the contact trench 96, the Ti silicide film 102 appearing on the bottom surface functions as an etching stopper, and the growth in the depth direction of the trench is basically stopped.

Tungsten (W) is deposited by CVD in the contact grooves 96 and the contact holes 110 formed in this manner and having different depths. For example, W is generated and deposited by the reaction of WF ₆ gas and silane (SiH ₄ ) gas to form the W layer 130. The contact groove 96 and the contact hole 110 are filled with the W layer 130 (FIG. 5D).

  Thereafter, the deposited layer on the upper surface of the silicon oxide film 92 is removed by a CMP (Chemical Mechanical Polishing) process or an etch back process. As a result, a tungsten wiring 30i embedded in the contact groove 96 and a tungsten plug 112 embedded in the contact hole 110 are formed (FIG. 5E).

  A first Al layer is deposited on the surface of the silicon oxide film 92 and patterned to form Al wirings (not shown) connected to the Al wirings 98 and 114 and the tungsten wiring 30i. The structure shown in FIG. Is completed. After the first Al layer, an interlayer insulating film and other Al layers are further stacked.

  Of the silicon oxide film openings of the various contacts of the CCD image sensor 20, the contact groove 96 and the contact hole 110 described above have the largest difference in depth. According to the present invention, these can be formed simultaneously. The present invention can also be applied to a plurality of openings having a smaller depth difference, and a contact structure using these openings can be formed simultaneously. For example, it is possible to simultaneously form a contact for a 1 poly-Si layer or a 2 poly-Si layer and a contact for a silicon substrate 80, or a contact for a 1 poly-Si layer and a contact for a 2 poly-Si layer at the same time.

  Furthermore, the depth of the contact structure that can be formed simultaneously is not limited to two types, and three or more types of contact structures having different depths can be formed simultaneously. For example, in FIG. 2, the contact structure for each layer of 1 to 3 poly-Si can be formed simultaneously with the formation of the contact 62 for the FD 52. That is, in the above-described CCD image sensor 20, not only the backing wiring structure and the contacts 62 but also other contacts 26, 44, 60, 64 and 66 can be formed simultaneously. In this case, a silicide film is formed on the surface of the 3poly-Si layer and, if necessary, a silicide film is formed on the surface of the 2poly-Si layer, or on both surfaces of the 1poly-Si layer and the 2poly-Si layer. The depth to which the polysilicon film is formed is determined according to the selectivity of the etching process for forming the opening in the silicon oxide film with respect to the polysilicon. In the above-described embodiment, the silicide film is formed on the entire surface of the polysilicon wiring 100 by the salicide process. However, the silicide can be selectively formed in the vicinity region where the contact hole is provided.

  As described above, according to the present invention, contact structures having different depths can be formed by a single etching process, and the contact formation process becomes simple and easy. Further, the contact resistance can be reduced by connecting the silicon portion such as the poly-Si layer and the metal electrode such as tungsten via the silicide.

  In the above embodiment, the Ti film 122 is formed on the polysilicon wiring 100, and silicide is formed using the Ti film 122. However, other metals can be used for forming the silicide. This metal is selected from the viewpoints of, for example, good adhesion to silicon, low electrical resistance, and resistance to silicon oxide film etching. For example, nickel (Ni) or cobalt (Co) can be selected instead of Ti.

  Although the present embodiment relates to the CCD image sensor 20, it can also be applied to other semiconductor elements.

1 is a schematic plan view showing a schematic configuration of a CCD image sensor according to an embodiment of the present invention. FIG. 2 is a schematic plan view showing a schematic arrangement of polysilicon electrodes and contacts in a CCD image sensor according to an embodiment of the present invention. It is typical sectional drawing which shows the contact structure used for the backing wiring of the CCD image sensor which is embodiment of this invention, and the structure of the contact with respect to a floating diffusion layer. It is typical sectional drawing which shows the formation process of the structure of the contact structure used for the backing wiring of the CCD image sensor which is embodiment of this invention, and a floating diffusion layer. It is typical sectional drawing which shows the formation process of the structure of the contact structure used for the backing wiring of the CCD image sensor which is embodiment of this invention, and a floating diffusion layer. It is typical sectional drawing which shows the structure of the conventional contact.

Explanation of symbols

  20 CCD image sensor, 20i imaging unit, 20s storage unit, 20h horizontal transfer unit, 20d output unit, 22 vertical shift register, 24 vertical transfer electrode, 26, 44, 60, 62, 64, 66 contact, 28 underlay electrode, 30 Tungsten electrode, 40, 42 Horizontal transfer electrode, 50 Output gate electrode (OG), 52 Floating diffusion layer (FD), 54 Reset gate electrode (RG), 56 Reset drain (RD), 58 Output amplifier, 80 Silicon substrate, 82 p well (PW), 84 charge transfer region, 86 channel isolation region, 90, 92 silicon oxide film, 94 backing wiring structure, 96 contact groove, 98, 114 Al wiring, 100 polysilicon wiring, 102 silicide film, 110 contact hole , 112 Tungsten plug, 12 3poly-Si film, 122 Ti film, 124 an etch mask, 130 W layer.

Claims (4)

The insulating layer containing silicon oxide stacked on the semiconductor substrate is etched to form a first opening reaching the first silicon portion in the insulating layer having a first thickness existing on the first silicon portion. And a method of manufacturing a semiconductor device, comprising: an opening forming step of forming a second opening reaching the second silicon portion in the insulating layer having a second thickness smaller than the first thickness existing on the second silicon portion. Because
A metal film forming step of laminating a metal film covering the second silicon portion;
A silicide forming step of selectively forming a silicide film on a surface of the second silicon portion by reacting the second silicon portion with the metal film;
An insulating layer stacking step of stacking the second thickness insulating layer on the second silicon portion on which the silicide film is formed;
Have
The opening forming step includes forming the second opening while using the silicide film as an etching stopper in the second opening;
A method of manufacturing a semiconductor device. The manufacturing method according to claim 1,
Metal wiring for depositing a metal film after the opening forming step and forming metal wiring electrically connected to the first silicon portion and the second silicon portion in the first opening and the second opening A method for manufacturing a semiconductor device, comprising a forming step. In the manufacturing method of Claim 1 or Claim 2,
The second silicon portion is a polysilicon wiring;
The insulating layer is a silicon oxide film;
A method of manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1 or 2,
The semiconductor device includes a charge coupled device in which a charge transfer region is formed on a silicon substrate,
The first silicon part is a diffusion layer in a silicon substrate;
The second silicon part is a polysilicon wiring for supplying a clock signal to the transfer electrode,
The insulating layer is a silicon oxide film;
A method of manufacturing a semiconductor device.

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