JP2007328622A - Method for verifying circuit operation - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for verifying circuit operation that is capable of increasing the speed of verifying operation by further reducing the number of times of communication of split circuits to be verified when the operation of a circuit to be verified is verified. <P>SOLUTION: The method for verifying circuit operation includes an investigation step for investigating a method of synchronizing synchronization elements in the circuit to be verified; a splitting step for splitting the circuit to be verified into a plurality of split circuits to be verified 103.1, 103.2 in such a manner as to minimize the number of times that the synchronization element addressed by a path between the split circuits 103.1, 103.2 latches the signal values of the path; and a verification step for verifying the operation of the circuit to be verified, by causing the plurality of split circuits 103.1, 103.2 to communicate with each other via a bus 10. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a circuit operation verification method for performing operation verification of a circuit to be verified which is divided into a plurality of divided circuits to be verified and operates by performing mutual communication between the plurality of divided circuits to be verified. The present invention relates to a circuit operation verification method for performing operation verification of a circuit to be verified on a scale.

  As the circuit scale that can be mounted on a digital LSI (Large Scale Integration) has increased year by year, it has become an important issue to speed up the operation verification of the digital LSI.

  In recent years, a large-scale circuit such as a digital LSI is used as a circuit to be verified, and as a circuit operation verification method for speeding up the operation verification, an FPGA (Field Programmable Gate Array), CPLD (Complex Programmable Logic Device) capable of mounting the circuit is used. A configuration using a verification device such as) has been studied.

  For example, in Patent Document 1, a plurality of verification devices each mounted with a plurality of verified divided circuits obtained by dividing a circuit to be verified, and a functional operation of each of the verified divided circuits are realized by simulation. A plurality of simulation means, a bus connecting the plurality of simulation means to enable mutual communication between the plurality of simulation means, a bus control means for controlling the bus, and a plurality of simulations by controlling the bus control means There has been proposed a circuit operation verification method using a circuit operation verification device having higher-level control means for performing verification of functional operation of a circuit to be verified by performing mutual communication between the means.

  According to this circuit operation verification method, each of a plurality of divided circuit to be verified obtained by dividing a circuit to be verified is mounted on a plurality of verification devices. It is possible to execute. Further, according to this circuit operation verification method, in the verification, the communication is performed between the divided circuits to be verified through the bus, and the operation is performed by inputting a control signal such as a clock signal from the upper control means. Perform verification.

Patent Document 1 proposes the following circuit division method for speeding up the operation verification of the circuit to be verified.
-Tested so that the number of through paths (paths where there is no synchronization element such as a memory synchronized with the clock between the input signal and output signal of the circuit to be verified) between the circuit to be verified is minimized. A circuit dividing method for dividing a circuit. If the number of through paths is small, the number of times of communication decreases.
A circuit division method that divides a circuit to be verified so that the number of communication occurrences is minimized based on a signal change rate of a path across the circuit to be verified.

Both of the above two circuit division methods are methods for speeding up the operation verification of the circuit to be verified by dividing the circuit to be verified so that the required number of communications between the verification devices is reduced.
JP 2005-84957 A

  By the way, the timing at which communication via a path crossing between the divided circuits to be verified is required is when the following two conditions are satisfied.

Condition 1) After the signal value of the path that crosses between the divided circuits to be verified changes. Condition 2) Before the synchronization element of the communication destination of the path that crosses between the divided circuits to be verified latches the signal value of the path. If is not changing, there is no need to communicate. If the signal value of the path has changed and the synchronization element at the communication destination does not latch the signal value, communication is not necessary.

  Condition 1 is a condition based on a synchronization element at a communication source, and condition 2 is a condition based on a synchronization element at a communication destination.

  Of the circuit division methods proposed in Patent Document 1, the circuit division method that minimizes the number of communication occurrences based on the signal change rate of the path that crosses between the divided circuits to be verified is focused on condition 1. It is a technique.

  However, since Patent Document 1 does not pay attention to Condition 2, circuit division that can sufficiently reduce the number of communications has not been achieved. Also, unnecessary communication is performed when a schedule for clock input and communication between devices is determined.

  An object of the present invention is to provide a circuit operation verification method capable of further reducing the number of times of communication of a verification target divided circuit at the time of verifying the operation of the circuit to be verified and increasing the speed of the operation verification.

In order to achieve the above object, the present invention provides:
A circuit operation verification method for performing operation verification of a circuit to be verified that is divided into a plurality of divided circuits to be verified and performs mutual communication via a bus between the plurality of divided circuits to be verified.
An investigation step for investigating a synchronization method of a synchronization element synchronized with a clock in the circuit to be verified;
Based on the result of the investigation in the investigation step, the circuit to be verified is divided into a plurality of circuits to be verified so that the number of times that the synchronization element of the communication destination of the path across the circuit to be verified latches the signal value of the path is minimized. A dividing step of dividing into verification dividing circuits;
A verification step of performing operation verification of the circuit to be verified by performing mutual communication between the plurality of circuit to be verified via a bus.

  According to this configuration, attention is paid to a synchronization element at a communication destination of a path that is not focused on in Patent Document 1, and circuit division is performed so that the number of times that the synchronization element at the communication destination latches a signal value of the path is minimized. Compared to the invention disclosed in Patent Document 1, it is possible to effectively reduce the number of communications of the circuit to be verified at the time of verifying the operation of the circuit to be verified, thereby speeding up the operation verification.

Specifically, according to the first embodiment of the present invention, in the investigating step, as the synchronization method of the synchronization element, when the circuit to be verified uses a plurality of clocks having different frequencies, the frequency of the synchronization element Investigate whether to synchronize with other clocks,
In the division step, based on the investigation result in the investigation step, all the synchronization elements of the communication destination of the path crossing between the division circuits to be verified have a lower frequency than all of the synchronization elements of the communication source of the path. The circuit to be verified is divided into a plurality of divided circuits to be verified so as to be synchronized with a clock.

  According to this configuration, since the synchronization element of the communication destination of the path crossing between the divided circuits to be verified is synchronized with the clock having a low frequency, communication can be performed only at the timing of the clock with the low frequency to which the synchronization element of the communication destination is synchronized. Therefore, it is possible to reduce the number of times of communication of the divided circuit to be verified at the time of operation verification.

Further, in the second embodiment of the present invention, in the investigating step, as the synchronizing method of the synchronizing element, investigating whether the synchronizing element synchronizes at the rising edge or falling edge of the clock,
In the division step, based on the investigation result in the investigation step, all the synchronization elements of the communication sources of the paths crossing the division circuits to be verified are synchronized only at the rising edge or falling edge of the clock, or The circuit to be verified is divided into a plurality of divided circuits to be verified so that all the synchronization elements at the communication destination are synchronized only at the rise or fall of the clock.

  According to this configuration, it is possible to avoid performing communication both at the rising edge and the falling edge of the clock, so that the number of times of communication of the division circuit to be verified at the time of operation verification can be reduced.

In the third embodiment of the present invention, in the investigating step, as the synchronizing method of the synchronizing element, investigating whether the synchronizing element is synchronized at the rising edge or falling edge of the clock,
In the division step, based on the investigation result in the investigation step, all the synchronization elements of the communication source of the path crossing between the divided circuits to be verified are synchronized only at the falling edge of the clock, or the communication destination of the path The to-be-verified circuit is divided into a plurality of to-be-verified divided circuits so that all of the synchronization elements are synchronized only at the rise of the clock.

  In the verification step, the clock is automatically lowered by the divided circuit to be verified after the clock rises.

  According to this configuration, it is possible to avoid performing communication both at the rising edge and the falling edge of the clock, so that the number of times of communication of the division circuit to be verified at the time of operation verification can be reduced. Furthermore, after the clock rise, since the communication of the path across the divided circuit to be verified is not performed, the clock can be automatically lowered by the divided circuit to be verified. Therefore, since the number of clock inputs from the host computer to the verified divided circuit can be reduced, the number of communications of the verified divided circuit during operation verification can be further reduced.

  According to the present invention configured as described above, attention is paid to the synchronization element of the communication destination of the path not paid attention in Patent Document 1, and the number of times the synchronization element of the communication destination latches the signal value of the path is minimized. Since the circuit division is performed as described above, it is possible to further reduce the number of times of communication of the circuit to be verified at the time of verifying the operation of the circuit to be verified and to speed up the operation verification than the invention disclosed in Patent Document 1. Is obtained.

The best mode for carrying out the present invention will be described below with reference to the drawings. Among these, in the first to third embodiments, the basic system configuration is the same as the configuration of Patent Document 1, but the circuit division process, which will be described later, the path communication between the verified divided circuits and the order of clock input are determined. There is a difference from Patent Document 1 in the scheduling process and the address arrangement process.
(First embodiment)
1.1) System Configuration FIG. 1 is a block diagram showing a schematic configuration of a circuit operation verification apparatus used in the circuit operation verification method according to the first embodiment of the present invention.

  Referring to FIG. 1, in this embodiment, a circuit to be verified including a plurality of circuit elements or a plurality of circuit modules is divided into a plurality of divided circuits 103.1 and 103.2 to be verified, Verification division circuits 103.1 and 103.2 are mounted on a plurality of verification devices (hereinafter referred to as devices) 1 and 2, respectively.

  The devices 1 and 2 are connected to the bus 10, and the bus 10 is further connected to the bus controller 11. The bus controller 11 always operates as a bus master, and the devices 1 and 2 always operate as slave devices of the bus.

  The host computer system 12 is connected to the bus controller 11, user interface 13 and display device 14. The user can control the operation of the bus controller 11 using the user interface 13. Information obtained through the bus controller 11 is presented to the user by the display device 14. The bus controller 11 is regulated in operation by a command from the host computer system 12 and inputs and outputs signals to the devices 1 and 2.

  The bus controller 11 is connected to a memory 15 for sequentially storing designated signal values inside the circuit to be verified. The user specifies in advance to the bus controller 11 through the user interface 13 which signal in the circuit to be verified is to be specified. For example, a signal for which a break condition is set is specified.

  Each of the devices 1 and 2 is connected to the bus 10 through a bus interface 101 that enables input / output of signals, a divided circuit 103 to be verified obtained by dividing the circuit to be verified, and a divided circuit 103 to be verified. The communication circuit 102 is connected to the interface 101 to enable mutual communication with the divided circuit 103 to be verified of another device.

  Hereinafter, the configuration of the devices 1 and 2 will be described in more detail.

  FIG. 2 is a block diagram showing a detailed configuration of the devices 1 and 2 shown in FIG.

  As described above, the basic configuration of each of the devices 1 and 2 includes the bus interface 101, the communication circuit 102, and the divided circuit 103 to be verified.

  The communication circuit 102 supplies the write data WDATA from the bus interface 101 as an input signal input to the verified divided circuit 103, and selects the output signal output from the verified divided circuit 103 according to the address signal AD from the bus interface 101. The data is transferred to the bus interface 101.

  More specifically, the communication circuit 102 includes a clock control circuit 201, a register 202, an address decoder 203, and a selector 204.

  The clock control circuit 201 writes the write data WDATA, receives the write enable signal WE and the selector signal SEL, generates a clock signal, and supplies the clock signal to the divided circuit 103 to be verified and the selector 204. In the example of FIG. 2, two clock signals CLK and 2f_CLK are generated. In FIG. 2, the clock signal supplied to the selector 204 is not shown for the sake of simplicity.

  The register 202 receives the write data WDATA, the write enable signal WE, and the selector signal SEL, generates an input signal input, an input / output signal IN / OUT, and a reset signal RST and outputs them to the divided circuit 103 to be verified.

  The address decoder 203 decodes the address signal AD input from the bus interface 101 to generate selector signals SEL and SELTx, supplies the selector signal SEL to the clock control circuit 201 and the register 202, and supplies the selector signal SELTx to the selector 204. To do.

  The selector 204 selects one of the output signal output and the input / output signal IN / OUT of the verified divided circuit 103 as the transmission data TxD according to the selector signal SELTx, and outputs it to the bus interface 101.

  Note that one address is assigned to each of the input signal input and input / output signal IN / OUT input signal, the output signal output and the input / output signal IN / OUT output signal of the divided circuit 103 to be verified. The maximum number of bits of data specified by one address is equal to the bit width of write data WDATA and transmission data TxD. The address by the address signal AD may be a part of the address space of the bus 10 or an address in another space. This address only needs to be able to uniquely determine the data position of the verification target divided circuit 103 from the bus 10. When this address is not part of the address space of the bus 10, the bus interface 101 performs necessary address conversion. However, in the allocation of each data address, data of devices with different connection destinations cannot be allocated to one address.

  FIG. 3 is a block diagram showing a detailed configuration of the clock control circuit 201 shown in FIG.

  Referring to FIG. 3, the clock control circuit 201 includes synchronization elements 301 and 302 and AND circuits 303 and 304. In FIG. 3, [X] in writing WDATA [0] to WDATA [1] and selector signals SEL [0] to SEL [1] represents the bit number of the signal.

  When both the selector signal SEL [0] and the write enable signal WE become active, the synchronization element 301 latches the value of the write data WDATA [0], and uses the value as the clock signal CLK to the verified divided circuit 103. input.

  Similarly, when both the selector signal SEL [1] and the write enable signal WE become active, the synchronization element 302 latches the value of the write data WDATA [1] and uses the value as the clock signal 2f_CLK to be verified. Input to the circuit 103.

  When the host computer system 12 raises the clock signal CLK, it inputs the address value assigned to the clock signal CLK from the bus controller 11 as the address signal AD, and inputs 1 to WDATA [0]. When falling, the address value assigned to the clock signal CLK is input as the address signal AD, and 0 is input to WDATA [0]. In FIG. 3, WDATA [0] and WDATA [1] are assigned to inputs of CLK and 2f_CLK, respectively, but this assignment can be freely changed within the bit width of WDAT. Although the synchronization elements 301 and 302 operate with the clock signal from the bus interface 101, the clock signal is not shown for simplicity.

  4 is a block diagram showing a detailed configuration of the register 202 shown in FIG.

  Referring to FIG. 4, the register 202 has the same number of synchronization elements 401 to 407 as the sum of the sum of the input signals input and input / output signals IN / OUT of the circuit to be verified 103. FIG. 4 shows an example where the write data WDATA has a bit width of 3 and the total number of input signals input and input / output signals IN / OUT of the divided circuit 103 to be verified is 7. Further, A, B, C, D, E, F, and G in FIG. 4 respectively indicate seven input signals input and input signals of the input / output signal IN / OUT.

  The synchronization element 401 latches the value of the write data WDATA [0] when both the selector signal SEL [0] and the write enable signal WE become active. The other synchronization elements 402 to 407 perform substantially the same operation as the synchronization element 401.

  By configuring the register 202 as shown in FIG. 4, each of the synchronization elements 401 to 407 can be uniquely specified from the bus 10, and the input signal input and the input / output signal IN / OUT input signals of the divided circuit 103 to be verified. All values of A, B, C, D, E, F, and G can be changed from all devices connected to the bus 10.

  For example, if write data WDATA [0] to WDATA [2] = (1, 0, 0) and selector signals SEL [0] to SEL [2] obtained by decoding the address signal AD are set to (1, 0, 0). When the write enable signal WE becomes active and a clock (not shown) rises, data “1”, “0”, and “0” are held in the synchronization elements 401 to 403, respectively.

  FIG. 5 is a block diagram showing a detailed configuration of the selector 204 shown in FIG. FIG. 5 shows an example in which the transmission data TxD has a bit width of 3, and the total number of output signals output and output signals of the divided circuit 103 to be verified is eight. In addition, OA, OB, OC, OD, OE, OF, OG, and OH in FIG. 5 represent output signals output of the divided circuit 103 to be verified.

  The selector 204 has three selector circuits 501 to 503. The selector circuits 501 to 503 operate with the clock signal from the clock control circuit 201, but the clock signal is not shown for the sake of simplicity.

  The selector circuit 501 receives the output signals OA, OD, OG from the divided circuit 103 to be verified, selects one of the output signals OA, OD, OG by the selector signal SELTx, and outputs it as transmission data TxD [0].

  The selector circuit 502 receives the output signals OB, OE, and OH from the divided circuit 103 to be verified, selects one of the output signals OB, OE, and OH by the selector signal SELTx and outputs it as transmission data TxD [1].

  The selector circuit 503 receives the output signals OC, OF, “0” from the divided circuit 103 to be verified, selects one of the output signals OC, OF, “0” by the selector signal SELTx, and transmits the transmission data TxD [2]. Output as.

  FIG. 6 is a flowchart for explaining a schematic flow from dividing the circuit to be verified into two divided circuits 103.1 and 103.2 to be verified and mounting them on the two devices 1 and 2, respectively.

  Referring to FIG. 6, in order to mount the circuit to be verified on the two devices 1 and 2, first, circuit division is performed to divide the circuit to be verified into two circuit to be verified 103.1 and 103.2. First, for each of the division candidate solutions, the communication source / communication destination synchronization element of the path crossing the circuit division plane is investigated (step S101). Based on this investigation result, the circuit to be verified is divided into the circuit to be verified 103.1 so that the number of times that the synchronization element of the communication destination of the path across the circuit to be verified latches the signal value of the path is minimized. Divide into 103.2 (step S102).

  Subsequently, scheduling is performed to determine the order of communication and the timing for providing the clock for each path crossing between the divided circuits to be verified 103.1 and 103.2 (step S103). Based on this scheduling, the address arrangement in the bus address space of the input signal input, the input / output signal IN / OUT, and the output signal output of the divided circuit to be verified 103.1, 103.2 mounted on the devices 1 and 2 is determined ( Step S104). Details of steps S101 to S104 will be described later. The communication circuit 102 is generated from the determined address arrangement (step S105).

  At this time, in steps S101 and S102, the verification divided circuit 103 is generated for each of the devices 1 and 2, and in step S105, the communication circuit 102 is generated for each of the devices 1 and 2. Thereafter, the divided circuit 103 to be verified and the communication circuit 102 are mounted on the devices 1 and 2 (step S106). The mounting method varies depending on the configuration of the devices 1 and 2. For example, when one of the devices 1 and 2 is composed of programmable elements, in addition to preparing the bus interface 101 and the communication circuit 102 in advance, the highest circuit in which the divided circuit 103 to be verified, the communication circuit 102 and the bus interface 101 are instantiated May be synthesized using a synthesis tool, and the result may be placed and routed to configure a programmable element.

  In addition, the process of step S101-S104 can be performed by the simulation means which is not illustrated in FIG.

1.2) Circuit Division Next, the circuit division process of the circuit to be verified in steps S101 and S102 shown in FIG. 6 will be described in more detail.

  In circuit division of the circuit to be verified, as described above, circuit division is performed so that the number of times that the synchronization element of the communication destination of the path across the divided circuit to be verified latches the signal value of the path is minimized. Here, it is assumed that the circuit to be verified is composed of a plurality of circuit units, and each circuit unit is composed of one or a plurality of circuit elements. The basic procedure of the circuit division method is as follows.

  A1) Read a hardware description language of a circuit to be verified including a plurality of circuit units, and analyze which circuit unit each input and output of each circuit unit is connected to.

  A2) The number of devices, the circuit scale of each device, and the circuit scale of each circuit unit are calculated. The number of devices and the circuit scale of each device are manually given by the user, and the circuit scale of each circuit unit is estimated by reading the hardware description language for the circuit unit.

A3) The hardware description language of the entire circuit to be verified is read, and information on the synchronization element of the communication source / destination of the path crossing between the circuit units is stored. Specifically, the information of the synchronization element is the following two.
(1) Information on which frequency clock the communication source / destination synchronization element synchronizes with when the circuit to be verified uses a plurality of clocks having different frequencies.
(2) Information on whether the communication source / destination synchronization elements are synchronized at the rising edge of the clock or at the falling edge.

A4) Based on the information obtained in steps A1 to A3, the number of times that the synchronization element of the communication destination synchronizes with the signal value of the path across the divided circuit to be verified is minimized. Perform circuit division. As a result, the necessary number of communications during operation verification is reduced. Further, circuit division is performed so as to reduce the number of clock inputs. Specifically, circuit division is performed as follows.
(A) Circuit division is performed so that the number of paths crossing between the divided circuits to be verified is reduced.
(B) When the circuit to be verified uses a plurality of clocks having different frequencies, all the synchronization elements in the communication destination of the path crossing between the divided circuits to be verified have a frequency higher than that of all the synchronization elements of the communication source. Circuit division is performed so as to synchronize with a small clock.
(C) For all paths straddling between the divided circuit to be verified, the synchronization element of the divided circuit to be verified of the communication source of the path and the synchronous element of the divided circuit to be verified of the communication destination satisfy the following condition i or condition ii: Perform circuit division. Hereinafter, a synchronization element that synchronizes with the rising edge of the clock is referred to as PM, and a synchronization element that synchronizes with the falling edge of the clock is referred to as NM.
(Condition i) The set of synchronization elements of the communication source is either PM or NM. Alternatively, the set of communication synchronous elements is either PM or NM.
(Condition ii) The set of synchronization elements of the communication source is only NM. Alternatively, the PM is the only set of communication-destination synchronization elements.

  Condition ii is more severe than condition i.

  Among these circuit dividing methods, the circuit dividing methods (b) and (c) are unique to the present invention which is not disclosed in Patent Document 1.

  In order to help understanding of this circuit dividing method, a simple example will be described.

  The verification of the circuit to be verified will be described in detail later. Roughly speaking, the device-to-device communication for performing communication between the circuit to be verified 103.1 and 103.2 mounted on each device 1 and 2 and the host computer system This is executed by alternately repeating the clock signal input from 12 to each of the divided circuit to be verified 103.1 and 103.2.

  The inter-device communication is performed for all paths in which a certain synchronization element in the circuit to be verified is a communication source and a synchronization element in another circuit to be verified is a communication destination across the circuit division plane.

  For example, in the case of FIG. 7, a path P in which the synchronization element X in the divided circuit to be verified 103.1 is a communication source and the synchronization element Z in the divided circuit to be verified 103.2 is a communication destination, and the division to be verified Between the devices of the path Q such that the synchronous element X in the circuit 103.1 is a communication source and the synchronous element Y in the verified divided circuit 103.1 is the communication destination through the verified divided circuit 103.2. Communicate. Note that the synchronization elements in the divided circuits 103.1 and 103.2 to be verified are realized by FFs (flip-flops), registers, memories, and the like.

  In the case of FIG. 7, when circuit division is performed using the circuit division method of (a), it is obvious that the number of communication between devices decreases.

  In addition, even if circuit division is performed using the circuit division method (b), the number of communication between devices is reduced. The reason will be described with reference to the circuit division examples of FIGS.

  8 and 9, (A) is a diagram showing an example of circuit division in which three synchronization elements X, Y, and Z are divided into two to-be-verified divided circuits, and (B) is a clock input to the device and the device The flowchart explaining the timing of intercommunication, (C) is a figure which shows the waveform of a clock, the signal value of a path | pass, and the signal value of the synchronous element of a communication destination.

  Here, in (A), the synchronization element Z is synchronized with the clock signal f_Clock, and the synchronization elements X and Y are synchronized with 2f_Clock having a frequency twice that of f_Clock. Note that the waveforms of the clock signals f_Clock and 2f_Clock are the same in FIGS. In (B), the clock input is to input both rising and falling of the clock signal. Further, in (C), a vertical thick dotted line in the figure indicates the timing of communication between devices. Further, the signal value of the synchronous element of the communication destination corresponding to the signal value [X] of the path is ([X]).

  For example, in the circuit division example shown in FIG. 8A, the circuit division is performed so that the synchronization element Z is arranged at a communication destination of a path that crosses between the divided circuits to be verified. In this case, as shown in FIGS. 8B and 8C, if the inter-device communication is performed just before the clock signal f_Clock is input, the circuit operates normally. This is because the signal of the path between the divided circuits to be verified changes in synchronization with the clock signal 2f_Clock, but the signal of this path is latched only in synchronization with the clock signal f_Clock.

  On the other hand, in the circuit division example shown in FIG. 9A, circuit division is performed so that the synchronization element Y is arranged at a communication destination of a path that crosses between the divided circuits to be verified. That is, the circuit dividing method (b) is used. In this case, as illustrated in FIG. 9B, it is necessary to perform inter-device communication for each input of the clock signal 2f_Clock. This is because, as shown in FIG. 9C, the signal of the path between the division circuits to be verified changes in synchronization with the clock signal 2f_Clock, and the change is latched in synchronization with the clock signal 2f_Clock.

  Therefore, the circuit division example shown in FIG. 9 requires twice as many communication operations as the circuit division example shown in FIG.

  In this way, when circuit division is performed using the circuit division method of (b), the number of communications of the verification target divided circuit during operation verification is reduced with respect to the verification target circuit using a plurality of clocks having different frequencies. This has the effect of improving the operation verification speed.

  Further, even when circuit division is performed using the circuit division method of (c), the number of communication between devices is reduced. The reason will be described with reference to the circuit division examples of FIGS. In the circuit division method (c), circuit division is performed so as to satisfy the condition i or the condition ii.

  10 to 13, (A) is a diagram showing an example of circuit division in which four synchronization elements are divided into two to-be-verified divided circuits, and (B) shows the timing of clock input to the device and communication between devices. The flowchart to be described, (C) is a diagram showing waveforms of the clock, the signal value of the path, and the signal value of the synchronization element of the communication destination.

  Here, in (A), the four synchronization elements are synchronized with the same clock signal. In the figure, the synchronizing element marked P is PM, and the synchronizing element marked N is NM. The waveform of the clock signal is the same in FIGS. Further, in (C), a vertical thick dotted line in the figure indicates the timing of communication between devices. Further, the signal value of the synchronous element of the communication destination corresponding to the signal value [X] of the path is ([X]).

  In the circuit division example shown in FIG. 10A, there are both PM and NM synchronization elements at the communication source of the path crossing between the divided circuits to be verified, and both PM and NM synchronization elements at the communication destination. Therefore, the condition i is not satisfied. In this case, as shown in FIG. 10B, inter-device communication is performed both after the rising and falling of the clock signal. As shown in FIG. 10C, since there are both PM and NM synchronization elements at the path communication source, the signal value of the path is synchronized with both rising and falling of the clock signal. This is because the signal value of the path is latched in synchronism with both rising and falling of the clock signal because there are both PM and NM synchronizing elements at the communication destination.

  In the circuit division example shown in FIG. 11A, there are both PM and NM synchronization elements in the communication destination of the path that crosses between the divided circuits to be verified, but only the communication source is PM. For this reason, the condition i is satisfied. In this case, as shown in FIG. 11B, it is necessary to perform inter-device communication only after the rising of the clock signal. This is because, as shown in FIG. 11 (C), since the PM is the only communication source of the path that crosses between the divided circuits to be verified, the signal value of the path changes only at the rising edge of the clock.

  Similarly, in the circuit division example shown in FIG. 12A, there is only NM as a communication source of a path that crosses between the divided circuits to be verified. For this reason, the condition i is satisfied. In this case, as shown in FIGS. 12B and 12C, it is only necessary to perform inter-device communication after the clock signal falls.

  Further, in the circuit division example shown in FIG. 13A, there are both PM and NM synchronization elements at the communication source of the path crossing between the divided circuits to be verified, but only the communication destination is PM. For this reason, the condition i is satisfied. In this case, as shown in FIG. 13B, device communication is necessary only after the clock signal falls. This is because, as shown in FIG. 13C, since the communication destination has only PM, the signal value of the path is latched in synchronism only with the rise of the clock signal. For this reason, if device communication is performed only before the rise of the clock signal, the circuit operates normally.

  The circuit division examples shown in FIGS. 12 and 13 also satisfy the condition ii. In these cases, since no inter-device communication is performed after the rising of the clock signal, a method of automatically falling the clock signal in the circuit can be used. The automatic falling is a method of reducing the number of inputs from the host computer system 12 by causing the clock signal to fall automatically in the circuit to be verified after the rising signal of the clock signal is input from the host computer system 12. is there. Details of this will be described later.

1.3) Scheduling of communication between devices Next, the scheduling process in step S103 shown in FIG. 6 will be described in detail.

  In the scheduling step, the order of performing the communication and the clock input of the path across the divided circuit to be verified is determined for one cycle of the clock having the lowest frequency. In the scheduling step, a search is made for a through path in the divided circuit to be verified. The through path refers to a path having no synchronization element between the input signal and the output signal of the divided circuit to be verified.

  FIG. 14 is a schematic diagram illustrating an example of a through path between devices.

  In the example shown in FIG. 14, there is a through path that does not include a synchronizing element between the input signal S2 and the output signal S3 of the divided circuit to be verified 103.1, and the input signal S4 and the output of the divided circuit to be verified 103.2 are output. There is a through path that does not include a synchronization element between the signal S5 and the signal S5. Between the synchronization element 601 and the synchronization element 602, there is a path including a path and a through path that cross between the divided circuits to be verified. In such a case, in the communication between devices in one clock cycle, the priority order of the paths connected to the through path among the paths crossing between the divided circuits to be verified 103.1 and 103.2 is inevitably determined. In this example, path P must communicate before path Q, and path Q must communicate before path R.

  The scheduling process for inter-device communication needs to be performed so as to maintain the priority order of the through paths. In order to help understanding of the scheduling process, description will be made using the circuit division example of FIG.

  In the circuit division example shown in FIG. 15, the clock signal CLK and the clock signal 2f_CLK having twice the frequency are given to the synchronizing elements in the divided circuit to be verified. There are five paths A, B, C, D, and E that cross between the divided circuits to be verified. Further, in the dividing circuit 103.2, there are a through path between the path A and the path B and a through path between the path D and the path E. For this reason, the path A needs to communicate before the path B, and the path D needs to communicate before the path E. Table 1 shows a set of communication source synchronization elements and communication destination synchronization elements of each path that crosses the divided circuit to be verified.

  For example, in the case of path A, PM in the dividing circuit 103.1 is a synchronization element of the communication source, and NM in 103.2 in the dividing circuit and NM in the dividing circuit 103.1 that has passed the path B Becomes the synchronous element of the communication destination. In the case of path B, the PM in the dividing circuit 103.1 that is the communication source of the path A and the NM in the dividing circuit 103.2 are the synchronization elements of the communication source, and the NM in the dividing circuit 103.1. Becomes the synchronous element of the communication destination.

  At this time, since the signal value of the path A changes in synchronization with the rise of CLK, communication is performed only after the rise of CLK.

  Since the path B latches the signal value of the path B in synchronization with the fall of CLK, the communication is performed only before the fall of CLK.

  Since the path C latches the signal value of the path only in synchronization with the rise of CLK, communication is performed only before the rise of CLK.

  Since the path D has a communication destination synchronization element that latches the signal value of the path D in synchronization with the clock signal 2f_CLK, communication is performed after the rising of the clock signal 2f_CLK. However, the path E is synchronized with the clock CLK. Since there is only a synchronizing element that latches the signal value of E, communication is performed only after the rise of CLK.

  FIG. 16 shows a schedule result of inter-device communication and clock input within the CLK1 period based on these results and the priority order of the through paths.

1.4) Address Placement Next, the address placement step in step S104 in FIG. 6 will be described in detail.

  In the address arrangement process, based on the scheduling result of step S103, the input signal input, input / output signal IN / OUT, and output signal output of the divided circuit to be verified 103.1, 103.2 mounted on each device 1, 2 are output. Determine the address arrangement.

  When determining the address arrangement, paths that can be communicated at the same timing are determined based on the scheduling result in step S103, and inputs, IN / OUTs, and outputs constituting these paths are arranged at the same address. By arranging the same address in this way, the number of communications can be reduced and the communication speed can be increased.

  For example, when the address arrangement of the dividing circuit 103.1 in FIG. 17 is performed according to the schedule shown in FIG. 16, if the output signals outputA and outputD or the input signals inputB and inputE are arranged at the same address, communication can be performed simultaneously. By doing so, the number of communications can be reduced.

1.5) Automatic falling of clock As described above, for all paths crossing between the divided circuits to be verified, the communication source synchronization element is only NM, or the communication destination synchronization element is only PM. In some cases, an automatic clock fall technique can be used.

  In the automatic falling of the clock, after the clock is raised from the bus controller 11, the clock is automatically lowered in the clock control circuit 201 to thereby input a signal from the bus controller 11 for the clock falling. It is a technique to avoid. With this method, the number of signal inputs is reduced, so that the speed of operation verification can be increased.

  The clock can be automatically lowered by configuring the clock control circuit 201 as shown in FIG.

  Compared with the clock control circuit 201 shown in FIG. 3, the clock control circuit 201 shown in FIG. 18 is provided with an AND circuit 701 to which WDATA is input instead of the AND circuit 303, and is synchronized with the AND circuit 701. A synchronous element 702, an inverter circuit 703, and an OR circuit 704 are added between the element 301 and the element 301.

1.6) Operation Verification FIG. 19 is a flowchart illustrating a schematic flow of operation verification of the circuit to be verified according to the first embodiment of the present invention. The circuit to be verified uses a clock signal CLK and a clock signal 2f_CLK having a frequency twice that of CLK as clock signals having different frequencies. As described above, since only the bus controller 11 becomes the bus master in the first embodiment, the setting of input signals and reading of signals of the devices 1 and 2 are all performed by the bus controller 11. Further, a history of signals designated in advance by the user is sequentially stored in the memory 15.

  First, the devices 1 and 2 are powered on (step S201).

  Subsequently, the bus controller 11 activates the reset signal RST of the divided circuit to be verified 103.1 and 103.2 through the communication circuits 102.1 and 102.2 of the devices 1 and 2 according to the command of the host computer system 12. By doing so, reset processing is performed (step S202). Further, communication between all the devices 1 and 2 is performed before inputting a clock as an initial process (step S203).

  Thereafter, clock input and inter-device communication are performed according to the scheduling result of step S103 shown in FIG. 6 (step S204). The clock CLK is activated by activating the CLK of the divided circuits 103.1 and 103.2 to be verified through the communication circuits 102.1 and 102.2 of the devices 1 and 2 according to a command from the host computer system 12. To do. In response to the command of the host computer system 12, the clock CLK is lowered through the communication circuits 102.1 and 102.2 of the devices 1 and 2 and the clock signal CLK of the divided circuits 103.1 and 103.2 to be verified is set to low. To do. The same applies to the rise and fall of the clock signal 2f_CLK. Inter-device communication is performed according to a schedule between these clock inputs. The inter-device communication is performed by the bus controller 11 reading the output signal of the communication source device and setting the input signal of the communication destination device.

  After completing the clock input for one cycle of CLK and the inter-device communication, the bus controller 11 determines whether or not the break condition stored in the memory 15 is matched (step S205). The state is stopped, and the process waits until the user specifies what operation is to be performed next through the user interface 13 (step S206). If the break condition is not met (No in step S205), the process proceeds to step S204, and the clock input and the inter-device communication are repeated.

  In step S206, the user can set a break, a step command, and how many cycles the user can operate without asking for opinions. At this time, since the history of the designated signal is stored in the memory 15, the user can refer to the past value of the designated signal through the display device 14, which is useful for debugging the circuit.

(Second Embodiment)
In the first embodiment, the two verified divided circuits 103.1 and 103.2 are mounted on the devices 1 and 2, respectively, but the present invention is not limited to the two-divided configuration. That is, the circuit to be verified can be divided into a desired number so that the number of times of communication is minimized between the divided circuits to be verified. Regardless of the number, each device has the above-described basic configuration and is connected to each other via the bus 10, and the operation verification of the circuit to be verified is executed as a whole.

  Further, in the first embodiment, the two verification divided circuits 103.1 and 103.2 are divided into devices 1 and 2, respectively, but the present invention is not limited to this. That is, it is also possible to divide a plurality of divided circuit to be verified 103.1 and 103.2 into devices and / or simulators and interconnect them by the bus 10. Hereinafter, a circuit operation verification apparatus in which two devices and one simulator are connected by a bus 10 will be described as a second embodiment of the present invention.

  FIG. 20 is a block diagram showing a schematic configuration of a circuit operation verification apparatus used in the circuit operation verification method according to the second embodiment of the present invention.

  Referring to FIG. 20, in this embodiment, as in the first embodiment, divided circuits 103.1 and 103.2 to be verified are mounted on devices 1 and 2, respectively, and the logic unit of the circuit to be verified is actually implemented. An additional simulator 3 is connected to the bus 10.

  The simulator 3 includes a bus interface 801 for communicating with the bus 10, a memory 802, and a simulation engine 803 that actually operates the logic portion of the circuit to be verified.

  The memory 802 temporarily holds an input signal and an output signal of the verification target divided circuit simulated by the simulation engine 803.

  Since the simulation engine 803 is in an event driven format, the calculation is executed when the input signal fluctuates, and the output signal as the calculation result is written in the memory 802. In this embodiment as well, the bus controller 11 is always the bus master.

  Also in this embodiment, as in the first embodiment, the source and destination synchronization elements of the path crossing the divided circuit to be verified and the through path are investigated, and the clock input and the inter-device communication schedule are determined based on the investigation result. decide.

  When the circuit to be verified uses clocks having a plurality of different frequencies, the operation of the circuit operation verification device differs depending on which clock the simulator 3 is operating in synchronization with.

  FIG. 21 is a flowchart illustrating a schematic flow of operation verification of a circuit to be verified according to the second embodiment of the present invention. In FIG. 21, it is assumed that the simulator 3 operates in synchronization with the clock having the lowest frequency.

  Referring to FIG. 21, first, the devices 1 and 2 are powered on (step S301), and as described with reference to FIG. 19, reset processing is performed on the verified divided circuits 103.1 and 103.2 (steps). S302) As an initial process, communication is performed between all the devices 1 and 2 (step S303).

  Next, before inputting the clock to each of the devices 1 and 2, communication from the simulator 3 to the devices 1 and 2 is performed (step S304). Next, communication from the devices 1 and 2 to the simulator 3 is performed (step S305). Thereafter, the scheduled clock input and inter-device communication are performed for one cycle of the clock having the smallest frequency (step S306).

  Next, it is determined whether or not the host computer system 12 matches the break condition set at the time of activation (step S307). If they match (Yes in step S307), the state is stopped, the user setting is performed as described above (step S308), and the process proceeds to step S309. If they do not match (No in step S307), the process proceeds as it is. The process proceeds to S309.

  Next, the bus controller 11 transmits a request to advance one cycle to the bus interface 801 of the simulator 3, thereby changing the clock signal in the simulator engine 803 (step S309). When the input signal of the logic part of the circuit to be verified that is operated by the simulator engine 803 is changed, the bus interface 801 not only writes a value to the memory 802 but also which signal is changed and how the simulator engine 803 changes. To inform. In response to this input signal change notification, the simulator engine 803 performs calculation so as to reflect the change, and executes circuit simulation. The result of this simulation is written in the memory 802. Thus, the control returns to step S304, and the above steps S304 to S309 are repeated thereafter.

(Third embodiment)
FIG. 22 is a block diagram showing a schematic configuration of a circuit operation verification apparatus used in the circuit operation verification method according to the third embodiment of the present invention.

  Referring to FIG. 22, in the present embodiment, the program control processor 901 is connected to the bus 10, and the program control processor 901 executes the operation verification program 902 stored in the ROM. The functions of the computer system 12 are realized. An input unit 13 and an output unit 14 are connected to the program control processor 901. Since the operation executed by the program control processor 901 is the same as that described in the first and second embodiments, description thereof is omitted.

(Fourth embodiment)
In the present embodiment, in the third embodiment described above, a device capable of mounting a circuit such as an ASIC (Application Specific Integrated Circuit) is used instead of the verification device, and firmware is used instead of the operation verification program 902. .

(Fifth embodiment)
In this embodiment, a plurality of circuit modules are connected to each other by a bus in a single board, and a control processor connected to the bus in the same board executes communication between the modules and is synchronized with each module. A control signal such as a clock signal is input.

  According to the present invention, it is possible to speed up the operation verification of a large-scale LSI. It is also useful for speeding up the operation verification of firmware that operates LSI. Furthermore, even when a circuit is divided into a plurality of modules for mutual communication within a single substrate or chip as in SoC (System On a Chip), the speeding up of verification according to the present invention is useful.

It is a block diagram which shows schematic structure of the circuit operation verification apparatus used for the circuit operation verification method by 1st Embodiment of this invention. FIG. 2 is a block diagram illustrating a configuration of a verification device illustrated in FIG. 1. FIG. 3 is a block diagram illustrating a configuration of a clock control circuit illustrated in FIG. 2. FIG. 3 is a block diagram illustrating a configuration of a register illustrated in FIG. 2. FIG. 3 is a block diagram illustrating a configuration of a selector illustrated in FIG. 2. 5 is a flowchart illustrating a schematic flow from dividing a circuit to be verified to mounting on each verification device in the first embodiment of the present invention. It is a figure explaining the synchronous element of the communication origin and communication destination of the path | pass straddling between to-be-verified division circuits based on 1st Embodiment of this invention. It is a figure which shows an example of the circuit division method (b) by 1st Embodiment of this invention, (A) is a block diagram which shows the structure after circuit division, (B) is the case at the time of performing the division of (A) The flowchart explaining the flow at the time of operation | movement verification, (C) is a figure which shows the waveform of each part at the time of the operation | movement verification at the time of dividing (A). It is a figure which shows an example of the conventional circuit division | segmentation method, (A) is a block diagram which shows the structure after circuit division, (B) is a flowchart explaining the flow at the time of the operation verification at the time of performing the division of (A). (C) is a figure which shows the waveform of each part at the time of the operation | movement verification at the time of dividing (A). It is a figure which shows the other example of the conventional circuit division | segmentation method, (A) is a block diagram which shows the structure after circuit division, (B) demonstrates the flow at the time of the operation | movement verification at the time of dividing (A). The flowchart which performs (C) is a figure which shows the waveform of each part at the time of operation verification at the time of performing the division | segmentation of (A). It is a figure which shows an example of the circuit division method (c) by 1st Embodiment of this invention, (A) is a block diagram which shows the structure after circuit division, (B) is the case at the time of performing the division of (A) The flowchart explaining the flow at the time of operation | movement verification, (C) is a figure which shows the waveform of each part at the time of the operation | movement verification at the time of dividing (A). It is a figure which shows the other example of the circuit division | segmentation method (c) by 1st Embodiment of this invention, (A) is a block diagram which shows the structure after circuit division, (B) performed the division of (A) The flowchart explaining the flow at the time of the operation | movement verification in a case, (C) is a figure which shows the waveform of each part at the time of the operation verification at the time of performing the division | segmentation of (A). It is a figure which shows the further another example of the circuit division | segmentation method (c) by 1st Embodiment of this invention, (A) is a block diagram which shows the structure after circuit division, (B) performs the division of (A) FIG. 8C is a flowchart illustrating the flow of operation verification in the case of the operation verification, and FIG. 10C is a diagram illustrating waveforms of respective units during operation verification when the division of (A) is performed. It is a figure explaining the penetration path concerning a 1st embodiment of the present invention. It is a block diagram which shows the structure of the circuit operation verification apparatus after the circuit division by 1st Embodiment of this invention. FIG. 16 is a diagram showing a schedule of clock input and inter-device communication timing generated for the circuit operation verification apparatus after circuit division shown in FIG. 15. FIG. 16 is a diagram illustrating an input signal input and an output signal output of a divided circuit to be verified on the left side of the circuit operation verification device after circuit division shown in FIG. 15. FIG. 4 is a block diagram showing a configuration in which a clock automatic falling function is added to the clock control circuit shown in FIG. 3. 3 is a flowchart illustrating a schematic flow of operation verification of a circuit to be verified according to the first embodiment of the present invention. It is a block diagram which shows schematic structure of the circuit operation verification apparatus used for the circuit operation verification method by 2nd Embodiment of this invention. 6 is a flowchart illustrating a schematic flow of operation verification of a circuit to be verified according to the second embodiment of the present invention. It is a block diagram which shows schematic structure of the circuit operation verification apparatus used for the circuit operation verification method by 3rd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 2 Device for verification 3 Simulator 10 Bus 11 Bus controller 12 Host computer system 13 User interface 14 Display device 15 Memory 101 Bus interface 102 Communication circuit 103 Verification division circuit 201 Clock control circuit 202 Register 203 Address decoder 204 Selector 301, 302 Synchronous elements 303 and 304 AND circuits 401 to 407 Synchronous elements 501 to 503 Selector circuits 601 and 602 Synchronous elements 701 AND circuit 702 Synchronous elements 703 Inverter circuit 704 OR circuit 801 Bus interface 802 Memory 803 Simulation engine 901 Program control processor 902 Operation verification program

Claims (9)

A circuit operation verification method for performing operation verification of a circuit to be verified that is divided into a plurality of divided circuits to be verified and performs mutual communication via a bus between the plurality of divided circuits to be verified.
An investigation step for investigating a synchronization method of a synchronization element synchronized with a clock in the circuit to be verified;
Based on the result of the investigation in the investigation step, the circuit to be verified is divided into a plurality of circuits to be verified so that the number of times that the synchronization element of the communication destination of the path across the circuit to be verified latches the signal value of the path is minimized. A dividing step of dividing into verification dividing circuits;
A circuit operation verification method comprising: a verification step of performing an operation verification of the circuit to be verified by performing mutual communication between the plurality of circuit to be verified via a bus.   2. The method according to claim 1, further comprising an implementation step that is performed after the division step and before the verification step, and each of the plurality of division circuits to be verified is separated and mounted on an FPGA, CPLD, or ASIC. The circuit operation verification method described.   3. The circuit operation verification method according to claim 1, wherein, in the checking step, a synchronization method is checked only for a communication source and a communication destination synchronization element of a path straddling the verification target divided circuits. In the investigating step, as a synchronizing method of the synchronizing element, when the circuit to be verified uses a plurality of clocks having different frequencies, it is investigated which frequency clock the synchronizing element synchronizes with,
In the division step, based on the investigation result in the investigation step, all the synchronization elements of the communication destination of the path crossing between the division circuits to be verified have a lower frequency than all of the synchronization elements of the communication source of the path. The circuit operation verification method according to any one of claims 1 to 3, wherein the circuit to be verified is divided into a plurality of divided circuits to be verified so as to be synchronized with a clock. In the investigation step, as a synchronization method of the synchronization element, investigate whether the synchronization element is synchronized at the rising edge or falling edge of the clock,
In the division step, based on the investigation result in the investigation step, all the synchronization elements of the communication sources of the paths crossing the division circuits to be verified are synchronized only at the rising edge or falling edge of the clock, or The circuit according to any one of claims 1 to 3, wherein the circuit to be verified is divided into a plurality of divided circuits to be verified so that all the synchronization elements at the communication destination are synchronized only at the rising or falling edge of the clock. Operation verification method. In the investigation step, as a synchronization method of the synchronization element, investigate whether the synchronization element is synchronized at the rising edge or falling edge of the clock,
In the division step, based on the investigation result in the investigation step, all the synchronization elements of the communication source of the path crossing between the divided circuits to be verified are synchronized only at the falling edge of the clock, or the communication destination of the path 4. The circuit operation verification method according to claim 1, wherein the circuit to be verified is divided into a plurality of divided circuits to be verified so that all of the synchronization elements are synchronized only at the rising edge of the clock. 5.   The circuit operation verification method according to claim 6, wherein, in the verification step, the clock is automatically decreased by the divided circuit to be verified after the clock rises. In the investigating step, as a synchronizing method of the synchronizing element, when the circuit to be verified uses a plurality of clocks having different frequencies, the synchronizing element investigates which frequency clock the synchronizing element synchronizes with. Investigate whether to synchronize at the rising edge or falling edge of the clock,
Performed after execution of the splitting step and before execution of the verification step;
A search step of searching for a through path having no synchronization element between an input signal and an output signal of the division circuit to be verified;
A priority order determining step for determining a communication priority order of a path connected to the through-passage among paths crossing between the divided circuit to be verified based on a search result by the search step;
A scheduling step for determining which clock is to be communicated after the rising edge or the falling edge thereof, based on the investigation result of the investigation step and the priority order of the priority order determination step; The circuit operation verification method according to claim 1, further comprising:   A signal that forms a path that can be input and output at the same timing in each divided circuit to be verified, based on the scheduling result of the scheduling step, after the scheduling step and before the verification step is executed. The circuit operation verification method according to claim 8, further comprising an address arrangement step of arranging at the same address.

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