JP2007323786A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device whose manufacturing time can be reduced. <P>SOLUTION: In a step S1, original data (bit string) [126:0] having 127 bit length are input. The process proceeds to a step S2 and it is decided whether the number of bits of "1" in the bit string [126:0] input in the step S1 is greater than half (that is, ≥64) of the total bits. When the number of the bits of "1" is ≥64, the process proceeds to a step S3. In the step S3, the bit string [126:0] is reversed and bit [127] as a reversed bit is set to "1" and then the process proceeds to a step S5. In the step S5, fuses corresponding to the bit string [126:0] and the bit [127] respectively are cut by LT (laser trimming). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a technique for shortening the manufacturing time in a semiconductor device having a fuse cutting type data recording means.

  Conventionally, in order to realize a secure function in SOC (System on Chip), a method of mounting a unique ID for each SOC has been performed (for example, Patent Document 1).

  This unique ID can be recorded in a flash ROM or HDD, but is difficult to record in a memory mounted on an SOC manufactured by a normal CMOS process. Therefore, in a general SOC manufacturing method, a method of creating a unique ID by cutting a fuse by laser trimming (hereinafter also simply referred to as LT) or the like in a wafer test process before an assembly process is used.

  Since this unique ID needs to be unique in order to realize a secure function, generally, a chip such as a lot number, a wafer number, a chip position on the wafer and a manufacturing date used in the manufacturing process is used. Consists of information. Then, this chip information is made to correspond to bits A0 to An-1 as n (natural number) bit values, and in a fuse box having n fuses, each fuse is cut according to bits A0 to An-1. (For example, if “1”, disconnect and “0” do not disconnect).

JP 2003-101527 A

  As described above, the unique ID is obtained by associating chip information with a bit value as a bit value. Therefore, as the number of chips formed on one wafer increases, the number of fuses also increases. Therefore, as the miniaturization and the increase in the diameter progress, the time for performing the LT becomes longer. For example, if 4000 chips can be formed on one wafer, and 128 fuses are provided on one chip (128 bits), and 64 of the half are cut, this one sheet In such a wafer, LT of 64 × 4000 = 256000 times is required. Therefore, there is a problem that the manufacturing time in a semiconductor device such as an SOC becomes long.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of shortening the manufacturing time.

  A semiconductor device according to the present invention is a semiconductor device that cuts each fuse in correspondence with each bit in a fuse group including a predetermined number of fuses in order to record data consisting of a predetermined number of bits. The group further includes an inversion fuse indicating inversion of data in recording, and when the number of first fuses to be cut out of the fuse group is more than half of the predetermined number, the first fuse is not cut and the inversion fuse is cut. At the same time, the second fuse except for the first fuse and the inversion fuse is cut from the fuse group.

  A semiconductor device according to the present invention is a semiconductor device that cuts each fuse in correspondence with each bit in a fuse group including a predetermined number of fuses in order to record data consisting of a predetermined number of bits. The group further includes an inversion fuse indicating inversion of data in recording, and when the number of first fuses to be cut out of the fuse group is more than half of the predetermined number, the first fuse is not cut and the inversion fuse is cut. At the same time, the second fuse except for the first fuse and the inversion fuse is cut from the fuse group. Therefore, the number of times of laser trimming in data recording can be reduced. Therefore, manufacturing time can be shortened.

  The semiconductor device according to the present invention is characterized in that, in a bit string representing data such as a unique ID, an inverted bit is provided to indicate the inversion / non-inversion of other bits, thereby reducing the total number of bits. Thereby, it is possible to reduce the number of times of laser trimming (LT number) for cutting the fuse. Hereinafter, each embodiment will be described in detail with reference to the drawings.

<Embodiment 1>
FIG. 1 is a block diagram showing a configuration of an SOC (System on Chip) 100 according to the first embodiment.

  As shown in FIG. 1, the SOC 100 includes a fuse box 10, an MPU 20, and an I / F (interface) 30. The fuse box 10 has a plurality of fuses (not shown in FIG. 1) for recording a unique ID, and each fuse corresponds to each bit of the unique ID. The MPU 20 has a register 21 and a memory 22.

  In FIG. 1, the unique ID recorded in the fuse box 10 is read to the register 21 of the MPU 20 and transferred to the external device 200 via the I / F 30. Alternatively, the unique ID read to the register 21 may be stored in the memory 22 from the register 21 and processed, and then read again to the register 21 and transferred to the external device 200 via the I / F 30.

  FIG. 2 is a block diagram showing a configuration of the fuse box 10 of FIG. The fuse box 10 incorporates (n + 1) (n: natural number) fuses 11, and is provided with one input terminal POR and (n + 1) output terminals A0 to An.

  FIG. 3A is a diagram illustrating signals of the input terminal POR and the output terminals A0 to An in the fuse box 10 of FIG. As shown in FIG. 3A, when the input signal at the input terminal POR is 0, the output signals at the output terminals A0 to An are indefinite, and when the input signal at the input terminal POR is 1, the output terminal The output signal at A0 to An is a bit string corresponding to recorded data, that is, a unique ID. That is, as shown in FIG. 3B, if the fuse 11 is not cut, Ai (0 ≦ i ≦ n) becomes “0”, and the fuse 11 is cut as shown in FIG. If so, Ai (0 ≦ i ≦ n) is “1”.

  FIG. 4 is a schematic diagram showing the effectiveness of inverted bits in the bit string (unique ID) recorded in the fuse box 10 of FIG.

  In FIG. 4A, a 32-bit long bit string A is shown. In the bit string A, 22 bits out of 32 bits are “1” (corresponding to the first fuse according to the present invention), and 10 bits are “0”. Accordingly, since 22 of the 32 fuses 11 need to be cut, the number of LTs is 22.

  FIG. 4B shows a bit string B having a total length of 33 bits obtained by adding one inverted bit to a 32-bit length bit string. The bit string B is obtained by inverting each bit of the bit string A and setting an inversion bit indicating inversion to “1”. That is, the bit string B represents the same value as the bit string A in a different format by setting the inverted bit to “1”. In the bit string B, 10 bits are “1” (corresponding to the second fuse according to the present invention), and 22 bits are “0”. Therefore, 11 of the 33 fuses 11 (the above 10 bits plus 1 inverted bit) need to be cut, so the LT count is 11.

  That is, in the bit string A, when the number of “1” bits is more than half of the total number of bits, an inversion bit indicating inversion is provided, and this inversion bit is set to “1” to represent the bit string B. This makes it possible to reduce the number of LTs.

  FIG. 5 is a flowchart showing one process (unique ID recording process) of the method of manufacturing the SOC 100 of FIG. 1 when the fuse box 10 contains 128 (128-bit) fuses 11. In this 128-bit bit string [127: 0], it is assumed that bit [127] is an inverted bit.

  First, in step S1, 127-bit original data (bit string) [126: 0] is input to the MPU 20.

  Next, the process proceeds to step S2, and the MPU 20 determines whether or not the number of bits “1” in the bit string [126: 0] input in step S1 is more than half (that is, 64 or more). And when it is 64 or more, it progresses to step S3, and when it is less than 64, it progresses to step S4.

  Next, in step S3, the MPU 20 inverts the bit string [126: 0] and sets the bit [127] = 1 that is the inversion bit. Then, the process proceeds to step S5.

  Next, in step S4, the MPU 20 does not invert the bit string [126: 0], and sets the bit [127] = 0 that is an inverted bit. Then, the process proceeds to step S5.

  Next, in step S5, the MPU 20 performs LT on the fuses corresponding to the bit string [126: 0] and the bit [127], respectively. As a result, the number of LTs can be reduced.

  That is, in FIG. 5, bit string [127: 0] corresponds to the fuse group according to the present invention, and bit [127] corresponds to the inversion fuse according to the present invention.

  Assuming that the bit string [126: 0] is random data, when the conventional semiconductor device is used, the maximum number of LTs is 127. In the semiconductor device according to the present embodiment, however, The maximum value of the number of LTs can be reduced to 64 times (if it exceeds 64 times, it can be reduced to 64 times or less by inversion using an inversion bit). For example, in FIG. 4, “1” has a maximum of 8 consecutive in the bit string A, but has a maximum of 4 consecutive in the bit string B. That is, the continuity of data can be reduced by reducing the number of “1” s using inverted bits. This makes it difficult for others to decipher.

  FIG. 6 is a diagram showing a difference in bit change rate (ratio of bit values being “1”) according to the presence or absence of inverted bits when an 8-bit bit string is random data. FIG. 6A shows the case without the inverted bit, and FIG. 6B shows the case with the inverted bit.

As shown in FIG. 6A, when there is no inversion bit, the number of change bits (the number of bits whose value is “1”) can take values from 0 to 8. Since the probability that the number of change bits is k (0 ≦ k ≦ 8) is ₈ C _k / 28 = ₈ C _k / 256, the total of bit change rates given by the change bit number × probability (expected value) ) Is 1024/256 = 4.

  On the other hand, as shown in FIG. 6 (b), when there is an inverted bit, the number of change bits can take a value from 0 to 4 (when the number of change bits is 5, 6, 7, 8). The number of change bits becomes 3, 2, 1, 0 by inversion, and the change bit number becomes 4, 3, 2, 1 by adding 1 of the inversion bit to this. Since the probabilities are the same as those in FIG. 6A, the total (expected value) of the bit change rate given by the number of change bits × probability is 837/256 = 3.27. That is, by setting the inversion bit, the LT number can be reduced to 3.27 / 4 = 81.75%.

  As described above, according to the semiconductor device of this embodiment, the number of LTs in recording unique IDs or the like can be reduced by reducing the number of “1” s using inverted bits. Therefore, the manufacturing time can be shortened.

  Moreover, since the continuity of data can be reduced, it is difficult for others to decipher. As described above, since chip information is used as a general unique ID, it is possible to conceal the chip information by making it difficult for others to decipher.

  In the present invention, the chip information is recorded only for ensuring uniqueness, and the content itself is not used. Therefore, in reading, the content itself does not necessarily have to be correctly decoded. Therefore, even when the inversion bit is “1”, it is not always necessary to invert and read, and in order to improve confidentiality, it is preferable to read without inversion (even if reading without inversion). Uniqueness).

  If it is necessary to decode the inverted data to the value before the inversion, the decoding may be performed by either hardware or software.

  In the above description, the unique ID is recorded on the SOC. However, the present invention is not limited to this, and the present invention is applicable to all cases where data recording is performed using a fuse.

  That is, the present invention is applicable not only to the memory mounted on the SOC but also to other products.

  Further, the present invention is not limited to the unique ID, and the present invention can also be applied to the case where data is recorded by a redundant circuit using a fuse generally used in a memory as shown in FIG. 7, for example. The redundant circuit 300 shown in FIG. 7 includes a memory cell array 310, a row decoder 320, a bit line load 330, a redundant (spare) cell 340, a redundant (spare) row decoder 350, an address buffer 360, and a comparator. 370 and a program circuit 380.

  In FIG. 7, the address buffer 360 receives an address signal S1 indicating the address of the memory to be accessed. The address buffer 360 generates an input address signal S2 based on the input address signal S1, and inputs the input address signal S2 to the comparator 370. Further, the program circuit 380 generates a defective address signal S3 based on the defective address programmed in advance by cutting the fuse, and inputs it to the comparator 370.

  The comparator 370 compares the inputted input address signal S2 and the defective address signal S3, and if they match, the normal circuit deactivation signal S4 is inputted to the row decoder 320, and the memory cell array 310 is set. In addition, the redundant circuit activation signal S5 is input to the redundant (spare) row decoder 350 to activate the redundant (spare) cell 340. That is, defective cells in the memory cell array 310 are repaired by replacing them with redundant (spare) cells 340 by cutting fuses in the program circuit 380 and programming them as defective addresses. In such a defective address program in the program circuit 380, it is possible to reduce the number of LTs by using the inversion bit as in the case of recording the unique ID as described above.

  As described above, when the data to be recorded is a unique ID, the content itself is not used. Therefore, even if the inverted bit is “1”, the data is not necessarily inverted and read. There is no need. However, when the data to be recorded is a defective address of the redundant circuit 300, it is necessary to read the defective address accurately (if the data is not read correctly, normal cells are replaced with the redundant cells 340). When the bit is “1”, it is necessary to invert and read the data.

  Also, depending on the product, the device internal voltage and timing adjustment may be adjusted with a fuse. In such a case, the inverted bit is used as in the case of the unique ID recording and the defective address program described above. As a result, the number of LTs can be reduced.

<Embodiment 2>
In the first embodiment, the case where one inverted bit is set for the entire data composed of one bit string has been described. However, in the data that is actually handled, there may be a portion where the ratio of the bit “1” is extremely small. In such a case, the LT count is further increased by excluding this portion from the target of the inverted bit. May be reduced. That is, one inversion bit may be set for only a part of data composed of one bit string.

  FIG. 8 is a flowchart showing one process (unique ID recording process) of the semiconductor device manufacturing method according to the second embodiment. In FIG. 8, bit [n] is provided as an inverted bit for bit string [n-1: 0], which is n-bit long data. This bit sequence [n-1: 0] is divided into an m-bit length bit sequence [m-1: 0] and an (n-m) -bit length bit sequence [n-1: m] (m is (n- 1) The following natural number), it is assumed that bit [n], which is an inverted bit, is set only for bit string [n−1: m]. That is, in the flowchart of FIG. 8, step S1 ′ is added to the flowchart of FIG. 5 according to the first embodiment, and the bit string [n−1: m] of the bit string [n−1: 0] is added from step S1. The process proceeds to step S2, and the bit string [m-1: 0] of the bit string [n-1: 0] is directly advanced from step S1 'to step S5.

  That is, in FIG. 8, bit strings [n−1: m] and [m−1: 0] correspond to the first and second fuse groups according to the present invention, respectively.

  For example, in FIG. 5, the inverted bit is set to “1” only when the number of bits “1” in the 127-bit length bit string [126: 0] is 64 or more. Therefore, if the bit string [63: 0] is all “0” and the bit string [126: 64] is all “1” in the bit string [126: 0], the number of bits that are “1” is 63. Therefore, the inversion bit is “0”. Therefore, the number of LTs is 63 (in practice, the ratio of “0” or “1” in the bit string may be extremely high, but almost all of them are “0” or “1”). Although not possible, in the present embodiment, for the sake of explanation, the most extreme case is taken as an example (the same applies to the third embodiment).

  On the other hand, in FIG. 8, when the bit string [63: 0] is all “0” and the bit string [126: 64] is all “1” in the bit string [126: 0], n = 127 and m = If 64, only the bit string [126: 64] of the bit string [126: 0] is to be inverted. That is, in the bit string [126: 64], the number of “1” bits is more than half (that is, 32 or more), so the process proceeds from step S1, S2 to step S3, and the bit string [126: 64] is inverted and inverted. After setting bit [127] = “1” as a bit, the process proceeds to step S5. Therefore, the LT count in the bit string [126: 64] is one. In the bit string [63: 0], the process proceeds directly from step S1 'to step S5. Therefore, the LT count in the bit string [63: 0] is zero. Therefore, the total number of LTs in the bit string [126: 0] is one.

  As described above, according to the semiconductor device of the present embodiment, one inverted bit is set by excluding a portion in which the ratio of “1” bits is extremely small from the data. To do. Therefore, in addition to the effect of the first embodiment, there is an effect that the number of LTs can be further reduced.

  In the above description, the case where the bit string [126: 0] is divided into the bit string [63: 0] and the bit string [126: 64] has been described. However, the present invention is not limited thereto, and the data is divided at arbitrary positions in units of bits. Alternatively, it may be divided in word units or byte units (the same applies to the third embodiment).

<Embodiment 3>
In the second embodiment, a case has been described in which one inverted bit is set for data consisting of one bit string. However, the present invention is not limited to this, or two or more inverted bits may be set for data consisting of one bit string.

  FIG. 9 is a flowchart showing one process (unique ID recording process) of the manufacturing method of the semiconductor device according to the third embodiment. In FIG. 9, bits [n−1] and [n] are set as inverted bits for the bit string [n−2: 0] which is (n−1) bit long data. The bit string [n-2: 0] includes a bit string [k-1: 0] having a k-bit length, a bit string [m-1: k] having a (m-k) bit length, and a (nm-1) bit length. Bit sequence [n-2: m] (k is a natural number equal to or less than (m-1)), and bit [n-1] which is an inverted bit is set only for bit sequence [m-1: k]. It is assumed that bit [n], which is an inverted bit, is set only for the bit string [n-2: m]. That is, in the flowchart of FIG. 9, steps S1 to S4 in the flowchart of FIG. 8 according to the second embodiment are replaced with steps S1-1 to S4-1 and steps S1-2 to S4-2, respectively. 1: k] and [n-2: m] are performed separately.

  That is, in FIG. 9, the bit strings [m−1: k], [n−2: m] and the bits [n−1], [n] are respectively the third to fourth fuse groups and the fourth fuse group according to the present invention. It corresponds to the first to second inversion fuses.

  For example, in FIG. 8, among the bit string [126: 0], the bit string [63: 0] is all “0”, the bit string [94:64] is all “1”, and the bit string [126: 95] is all “0”. If n = 127 and m = 64, only the bit string [126: 64] (that is, the bit string [94:64] and the bit string [126: 95]) is included in the bit string [126: 0]. It becomes the target of bit [127] as an inverted bit. That is, in the bit string [126: 64], the number of “1” bits is less than half (that is, less than 32), so the process proceeds from step S1, S2 to step S4 without inverting the bit string [126: 64]. After setting bit [127] = 0 as the inversion bit, the process proceeds to step S5. Therefore, the LT number in the bit string [126: 64] is 31 times. In the bit string [63: 0], the process proceeds directly from step S1 'to step S5. Therefore, the LT count in the bit string [63: 0] is zero. Therefore, the LT number in the bit string [126: 0] is 31 in total.

  On the other hand, in FIG. 9, among the bit string [126: 0], the bit string [63: 0] is all “0”, the bit string [94:64] is all “1”, and the bit string [126: 95] is all “0”. If n = 127, m = 64, and k = 95, only the bit string [94:64] of the bit string [126: 0] is to be inverted. That is, in the bit string [94:64], the number of “1” is more than half (that is, 16 or more), so the process proceeds from step S1-1, S2-1 to step S3-1, and the bit string [94:64]. ] Is inverted and bit [126] = 1 which is an inverted bit is set, and then the process proceeds to step S5. Accordingly, the LT number in the bit string [94:64] is one. Further, in the bit string [125: 95], the number of bits “1” is less than half (that is, less than 16), so the process proceeds from step S1-2 and S2-2 to step S4-2, and the bit string [125: 95] is inverted and bit [127] = 0, which is an inverted bit, is set, and then the process proceeds to step S5. Therefore, the LT count in the bit string [125: 95] is 0. In the bit string [63: 0], the process proceeds directly from step S1 'to step S5. Therefore, the LT count in the bit string [63: 0] is zero. Therefore, the total number of LTs in the bit string [126: 0] is one.

  As described above, according to the semiconductor device of the present embodiment, data consisting of one bit string is divided into a plurality of areas, and inverted bits are set for each area. Therefore, in addition to the effect of the second embodiment, there is an effect that the number of LTs can be further reduced.

  In the above description, the case where a part of the bit string is excluded from the target of the inversion bit and a plurality of inversion bits are set for the remaining area has been described. However, the present invention is not limited to this. A plurality of inversion bits may be set for all regions.

1 is a block diagram showing a configuration of an SOC according to a first embodiment. 2 is a block diagram showing a configuration of a fuse box according to Embodiment 1. FIG. FIG. 3 is a diagram illustrating signals at an input terminal and an output terminal in the fuse box according to the first embodiment. 6 is a schematic diagram showing the effectiveness of inverted bits in the bit string recorded in the fuse box according to Embodiment 1. FIG. 4 is a flowchart showing one process (unique ID recording process) of the method of manufacturing a semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a difference in bit change rate according to the presence / absence of inverted bits in the semiconductor device according to the first embodiment. 1 is a block diagram showing a configuration of a redundant circuit according to a first embodiment. 10 is a flowchart showing one process (unique ID recording process) of the method for manufacturing a semiconductor device according to the second embodiment. 10 is a flowchart showing one process (unique ID recording process) of the method for manufacturing a semiconductor device according to the third embodiment.

Explanation of symbols

10 fuse box, 11 fuse, 20 MPU, 21 register, 22 memory, 30 I / F, 100 SOC, 200 external device, 300 redundant circuit, 310 memory cell array, 320 row decoder, 330 bit line load, 340 redundant cell, 350 Redundant row decoder, 360 address buffer, 370 comparator, 380 program circuit.

Claims (6)

A semiconductor device for cutting each fuse in correspondence with each bit in a fuse group including the predetermined number of fuses in order to record data composed of a predetermined number of bits,
The fuse group further includes an inversion fuse indicating inversion of the data in the recording,
When the number of first fuses to be cut out of the fuse group is more than half of the predetermined number, the first fuse is cut without cutting the inversion fuse, and the first fuse and the fuse from the fuse group are cut. A semiconductor device for cutting a second fuse excluding an inversion fuse. The semiconductor device according to claim 1,
The fuse group is:
A first fuse group to be a target of the inversion fuse;
A semiconductor device having a second fuse group that is not a target of the inversion fuse. The semiconductor device according to claim 1,
The inversion fuse has at least a first inversion fuse and a second inversion fuse,
The fuse group includes at least a third fuse group to be a target of the first inversion fuse and a fourth fuse group to be a target of the second inversion fuse. The semiconductor device according to claim 2,
The inversion fuse has at least a first inversion fuse and a second inversion fuse,
The first fuse group includes at least a third fuse group that is a target of the first inversion fuse and a fourth fuse group that is a target of the second inversion fuse. A semiconductor device according to any one of claims 1 to 4,
The data is a semiconductor device which is a secure ID in the SOC. A semiconductor device according to any one of claims 1 to 5,
A semiconductor device in which the data is an address of a defective cell in a memory cell array.

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