JP2007318928A - Inverter device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To speedily and accurately detect the independent operation of an inverter device connected to an AC power system. <P>SOLUTION: An angular velocity variation amount detection means is provided that detects the variation amount of an output voltage of the inverter device connected to an AC power system. A positive phase bias value (+α) is generated in response to a positive value of an angular velocity variation amount (Δω) detected by the angular velocity variation amount detection means, while a negative phase bias value (-α) is generated in response to a negative value. The phase of the inverter output current is controlled by a current phase command with the positive and negative phase bias values. When the angular velocity variation amount shows the same direction continuously and repeatedly, an inclination phase bias value of a divergence type is given. A signal showing the independent operation is outputted when the angular velocity variation amount becomes larger than a reference value. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an inverter device that converts direct current power such as a solar power generation device or a fuel cell power generation device into alternating current power, and that is connected to an alternating current power system to supply power to a load. The present invention relates to an inverter device having a function of detecting.

  An inverter device that converts direct-current power such as a solar power generation device into alternating-current power is connected to a commercial power system via a connection point. Therefore, at normal times, power is supplied to the load from both the commercial power system and the inverter device.

  By the way, when carrying out maintenance inspection of a load or the like, it is necessary to disconnect the load from the commercial power system and simultaneously disconnect the inverter device from the load. If the load can be reliably disconnected from the commercial power system and the inverter device, no problem will occur, but in the unlikely event that the load is disconnected from the commercial power system, but the load is not disconnected from the inverter device If this occurs (hereinafter referred to as “independent operation”), there is a possibility that the load maintenance inspector may be at risk. Therefore, it is necessary to accurately detect the independent operation of the inverter device.

  Detection of isolated operation of the grid-connected inverter device can be achieved by detecting minute changes in the grid frequency. However, in rare cases, the system frequency may hardly change even when the unit is operated alone. In order to solve this kind of problem, the output current phase of the inverter device is shifted every predetermined time, and the isolated operation is detected by the difference in voltage phase change between the isolated operation and the interconnected operation. Preventing the occurrence is disclosed in Patent Document 1. That is, in the method of Patent Document 1, the phase of the alternating current is shifted every predetermined time in one cycle or a plurality of cycles of the alternating current, the output voltage phase of the inverter device is monitored, and the single operation is detected. .

However, in the method of Patent Document 1, the reactive power fluctuates with the period of the system frequency, which may cause disturbance in the AC power system and cause a problem in the connected load. In addition, since the phase is shifted over one cycle or a plurality of cycles of the alternating current, there is a problem that it takes more than one cycle to detect the isolated operation. In addition, when a plurality of distributed power supplies (inverter power supplies) are connected to the load, there is a problem that an isolated operation cannot be detected unless the phase shifts of the plurality of distributed power supplies are synchronized.
JP-A-7-31052

  Accordingly, the problem to be solved by the present invention is that it is difficult to quickly and accurately detect an isolated operation, and an object of the present invention is an inverter device that can quickly and accurately detect an isolated operation. Is to provide.

The present invention for solving the above problems and achieving the above object is an inverter device for supplying power to a load in conjunction with an AC power system,
A DC input terminal connected to a DC power supply;
An AC output terminal connected to the load and the AC power system;
A DC-AC conversion circuit connected to the DC input terminal and having a plurality of DC-AC conversion switches;
Current detection means for detecting current flowing through the AC output terminal;
Voltage detecting means for detecting a system voltage at the AC output terminal;
The plurality of current detection means, the voltage detection means, and the plurality of DC-AC conversion switches connected to the control terminals of the plurality of DC-AC conversion switches so that the phase of the current flowing through the AC output terminal matches the phase of the system voltage. Switch control means for controlling on / off of the DC-AC conversion switch;
Phase detection means for detecting the phase (θ) of the system voltage;
Angular velocity change amount detecting means for detecting the angular velocity change amount (Δω) of the system voltage;
When the direction of the angular velocity variation (Δω) obtained from the angular velocity variation detection means is the first direction, a phase bias value (+ α) in the first direction is output, and the angular velocity variation (Δω) Phase bias value generating means for outputting a phase bias value (−α) in the second direction when the direction is the second direction;
The current phase command signal (θi) is switch-controlled by adding the system voltage phase detection value (θ) obtained from the phase detection means and the phase bias value (Δθ ₁ ) obtained from the phase bias value generation means. Adding means for supplying to the means;
Angular velocity variation reference value generating means for generating an angular velocity variation reference value (Δω _r );
The angular velocity change amount (Δω) is compared with the angular velocity change amount reference value (Δω _r ), and when the angular velocity change amount (Δω) is larger than the angular velocity change amount reference value (Δω _r ), An inverter device comprising: an isolated operation detecting unit that outputs a signal indicating that power is supplied from the inverter device without supplying power from the AC power system to a load. It is related.

According to a second aspect of the present invention, the tilt phase bias value generating means for generating the tilt phase bias value (Δθ ₂ ) whose phase bias value increases with time and the direction of the angular velocity change amount (Δω) are further defined. Based on the output of the angular velocity change amount direction determining means and the output of the angular velocity change amount direction determining means, a counter for determining whether or not the angular velocity change amount (Δω) remains in the same direction for a predetermined number of times or for a predetermined time. And a phase bias value (+ α) in the first direction when the counter means obtains an output indicating that the angular velocity change amount (Δω) remains in the same direction for a predetermined number of times or a predetermined time. And a mode switching means for supplying the inclination phase bias value (Δθ ₂ ) to the adding means instead of the phase bias value (Δθ ₁ ) consisting of the phase bias value (−α) in the second direction. It is desirable that
According to a third aspect of the present invention, it is desirable that the tilt phase bias value generating means comprises means for amplifying the angular velocity change amount (Δω) with a predetermined gain (K).
Further, as shown in claim 4, in response to a signal indicating that power is supplied from the inverter device without power supply from the AC power system obtained from the isolated operation detecting means. It is desirable to have means for interrupting power supply from the inverter device to the load.
Further, as shown in claim 5, the switch control means includes an output current command value creating means (12, 13 or 12a) and an output obtained from the output current command value creating means (12, 13 or 12a). Feedback control signal forming means (14) for forming a feedback control signal based on a current command value and a current detection value obtained from the current detection means, and the feedback obtained from the feedback control signal forming means (14) Switch control pulse forming means (15) for forming a switch control pulse for ON / OFF control of the DC-AC conversion switch based on a control signal, and a current phase command signal obtained from the adding means (Θi) is preferably supplied to the feedback control signal forming means (14) or the output current command value creating means (12, 13 or 12a).

The present invention has the following effects.
(1) During the interconnected operation, the phase bias value generating means outputs the phase bias value in the first direction (+ α) and the phase bias value in the second direction (−α) based on the vibration of the angular velocity change amount (Δω). Occur alternately. The phase bias value (+ α) in the first direction and the phase bias value (−α) in the second direction are randomly generated. The repetition time length of the phase bias value (+ α) in the first direction and the phase bias value (−α) in the second direction at the time of this interconnection operation is also unspecified, but the maximum repetition time length is Shorter than the voltage period. On the other hand, in the independent operation, the inverter device and the load are disconnected from the AC power system and disconnected, so that the phase change of the system voltage (inverter output voltage) occurs depending on the load impedance, and the angular velocity change amount ( Δω) is continuously changed in the same direction (for example, the first direction), and the phase bias value generating means outputs the phase bias value (+ α) in the first direction and the phase bias value in the second direction (− α) and no longer occur alternately. As a result, phase bias values in the same direction (for example, the first direction) are continuously generated from the phase bias value generating means, and the angular velocity change amount (Δω) is accelerated in the first direction or the second direction. It increases and crosses the angular velocity change amount reference value (Δω _r ), and an isolated operation is detected. Accordingly, it is possible to quickly and accurately achieve the isolated operation detection. Even when the inverter output power and the load power are balanced, the phase control of the inverter output current is performed with the phase bias in the same direction even during the single operation, so the system voltage (inverter output voltage) Also changes in the same direction as the phase of the inverter output current, and the angular velocity change amount (Δω) is maintained in the same direction and is accelerated and increased, so that an isolated operation can be detected quickly and accurately.
(2) Since the isolated operation is detected based on the phase bias, there is no disturbance near the system frequency.
(3) In the case where a plurality of inverter devices (distributed power supplies) are connected to a common load, it is not necessary to synchronize the phase bias between the plurality of inverter devices and detect an isolated operation. Accordingly, it is possible to easily detect an isolated operation.
Further, according to claim 2, when the tilt phase bias value (Δθ ₂ ) is given, the angular velocity change amount (Δω) is further accelerated and increased, and the isolated operation can be detected more quickly and accurately.

  Next, an embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 shows an electric power system including first and second inverter devices 100 and 100 ′ according to the first embodiment of the present invention. The first and second DC input terminals 1a and 1b of the first inverter device 100 are connected to a first DC power source 1 including a solar cell, a fuel cell, a storage battery, and the like. The first, second and third phase AC output terminals 2u, 2v and 2w of the first inverter device 100 are connected to a load 101 having a resistance (R), an inductance (L) and a capacitance (C), and the circuit is interrupted. It is connected to the three-phase AC power system 3 via the device 102. Therefore, the first distributed power source including the first DC power source 1 and the first inverter device 100 and the three-phase AC power system 3 are connected to supply power to the load 101. In Example 1 of FIG. 1, in addition to the first distributed power source including the first DC power source 1 and the first inverter device 100, the first DC power source 1 and the first inverter device 100 A second distributed power source including a second DC power source 1 ′ and a second inverter device 100 ′ configured similarly is provided, and the second inverter device 100 ′ is also connected to the load 101. . That is, the first and second inverter devices 100 and 100 ′ are connected in parallel. Since the configuration and function of the second distributed power supply are substantially the same as those of the first distributed power supply, description thereof is omitted. In the following description, the first DC power source 1 and the first inverter device 100 are simply referred to as the DC power source 1 and the inverter device 100.

The inverter device 100 includes a DC-AC conversion circuit, that is, an inverter circuit 103 having a three-phase V connection configuration. As shown in FIG. 2, the inverter circuit 103 divides the voltage Vdc of the DC power supply 1 so that the first and second DC input terminals 1a and 1b connected to each other have substantially the same capacity. A series circuit of second voltage dividing capacitors Ca and Cb is provided. The potential of the intermediate terminal 1c corresponding to the interconnection point of the first and second voltage dividing capacitors Ca and Cb has an intermediate value between the potentials of the first and second DC terminals 1a and 1b. The DC power supply 1 can be omitted, and the first and second DC power supplies having substantially the same voltage can be provided in place of the first and second voltage dividing capacitors Ca and Cb.

In order to constitute a DC-AC conversion switching circuit, the series circuit of the first and second switches S1, S2 and the series circuit of the third and fourth switches S3, S4 are the first and second DC terminals 1a. 1b. The series circuit of the first and second switches S1, S2 is called a first-phase (U-phase) switching circuit or a first-phase half-bridge switching circuit, and the series circuit of the third and fourth switches S3, S4 is called a first circuit. It can also be called a three-phase (W-phase) switching circuit or a third-phase half-bridge switching circuit.
The first to fourth switches S1 to S4 are IGBTs (insulated gate type bipolar transistors), but these can be controlled on / off differently such as NPN type or PNP type transistors, field effect transistors, etc. A semiconductor switch or the like.

  First to fourth diodes D1 to D4 are connected in reverse parallel to the first to fourth switches S1 to S4. The first to fourth diodes D1 to D4 may be individual diodes, or may be well-known parasitic or built-in diodes formed in the semiconductor substrate of the first to fourth switches S1 to S4. . The first to fourth diodes D1 to D4 have a direction of conduction when power is regenerated from the first, second and third phase AC terminals 2u, 2v and 2w to the DC power source 1 side.

  The first, second and third phase AC terminals 2u, 2v and 2w output the first, second and third line currents Isu, Isv and Isw having a phase difference of 120 degrees with respect to each other. 1 to a three-phase AC power system 3 and a three-phase load 101.

  The first phase reactor Lu is connected in series between the interconnection point P1 of the first and second switches S1, S2 and the first phase AC output terminal 2u. The third phase reactor Lw is connected in series between the interconnection point P2 of the third and fourth switches S3 and S4 and the third phase AC output terminal 2w. The first-phase and third-phase reactors Lu and Lw function as filters that remove high-frequency components caused by turning on and off the first to fourth switches S1 to S4.

The first filter capacitor Cu is connected between the first and second phase AC output terminals 2u, 2v. The second filter capacitor Cw has substantially the same capacitance C as the first filter capacitor Cu and is connected between the second and third phase AC output terminals 2v, 2w. The first and second filter capacitors Cu and Cw are for removing high-frequency components due to on / off of the first to fourth switches S1 to S4.
A circuit breaker 104 for preventing isolated operation is connected between the inverter circuit 103 and the first, second and third phase AC output terminals 2u, 2v and 2w.

  The second-phase AC output terminal 2v is connected to the interconnection point of the first and second voltage dividing capacitors Ca and Cb, that is, the intermediate terminal 1c via the circuit breaker 104. Accordingly, the first and second switches S1 and S2 and the first phase reactor Lu constitute a first phase half-bridge type conversion circuit, and the third and fourth switches S3 and S4 and the third phase reactor Lw. A third-phase half-bridge conversion circuit is configured by the above.

  The first and third phase current detectors CTu and CTw exemplified by CT (current transformer) for controlling the first to fourth switches S1 to S4 on and off so as to enable power factor control and the control circuit 4 And are provided. 1 and 2, the first and third phase current detectors CTu and CTw are provided outside the control circuit 4. However, the first and third phase current detectors CTu and CTw are provided in the control circuit 4. It can also be included. In FIG. 2, the control circuit 4 is indicated by a voltage detection means 5 and a control unit 6.

  The first phase current detector CTu is electromagnetically coupled to the first phase current path 7u between the interconnection point P1 of the first and second switches S1, S2 and one end of the first filter capacitor Cu. The first phase output current Iou (instantaneous value) flowing through the phase current path 7u is detected and sent to the control unit 6 via the line 8u. The second phase current detector CTw is electromagnetically coupled to the third phase current path 7w between the interconnection point P2 of the third and fourth switches S3 and S4 and one end of the second filter capacitor Cw. A third phase output current Iow (instantaneous value) flowing through the phase current passage 7w is detected and sent to the control unit 6 via a line 8w. In order to simplify the explanation, the currents of the first and third phase current paths 7u and 7w and the currents of the first and third phase current detectors CTu and CTw are indicated by the same Iou and Iow. To.

  In this embodiment, the first, second and third phase are controlled in spite of controlling the power factor at the first, second and third phase AC output terminals 2u, 2v and 2w to a desired value (preferably 1). A current detector for detecting the first, second and third phase interconnection currents Isu, Isv, Isw flowing through the AC output terminals 2u, 2v, 2w is not provided. Instead of this current detector, a voltage detecting means 5 is provided in the embodiment of FIG. The voltage detection means 5 includes a first voltage detection circuit 5a for detecting a voltage of the first filter capacitor Cu, that is, a line voltage Vuv (instantaneous value) between the first and second phase AC terminals 2u and 2v, and a second voltage detection circuit 5a. A second voltage detection circuit 5b for detecting the voltage of the filter capacitor Cw, that is, the line voltage Vvw (instantaneous value) between the second and third phase AC terminals 2v and 2w, and the first and second voltage detection circuits 5a. And a third voltage detection circuit 5c for detecting a line voltage Vwu (instantaneous value) between the third and first phase AC terminals 2w and 2u by inverting and adding the outputs of 5b. Instead of connecting the third voltage detection circuit 5c to the first and second voltage detection circuits 5a and 5b, the line voltage is directly connected to the first and third AC output terminals 2u and 2w. You can also ask for Vwu. In the present embodiment, for ease of explanation, the line voltage at the first, second and third phase AC output terminals 2u, 2v, 2w and the first, second and third voltage detection circuits 5a, 5b, The output voltage of 5c is represented by the same Vuv, Vvw, and Vwu. Output lines 9uv, 9vw, 9wu of the first, second and third voltage detection circuits 5a, 5b, 5c are connected to the control unit 6.

  The control unit 6 is configured to connect the first and third phase output currents Iou and Iow obtained from the first and second phase current detectors CTu and CTw and the line between the first and second phases obtained from the voltage detection means 5. Based on the voltage Vuv, the line voltage Vvw between the second and third phases, and the line voltage Vwu between the third phase and the first phase, the first, second and third phase AC output terminals 2u, 2v and 2w First, second, third and fourth switch control pulses G1 for controlling the flowing first, second and third phase interconnection currents Isu, Isv and Isw to have a desired power factor (preferably 1). , G2, G3, G4 are formed and sent to the control terminals (gates) of the first, second, third and fourth switches S1, S2, S3, S4. The control unit 6 is connected to the control terminal of the circuit breaker 104 for preventing isolated operation by a line 54. Therefore, when the control unit 6 detects an isolated operation, the circuit breaker 104 is turned off by the isolated operation detection signal on the line 54, and the isolated operation is prevented.

  FIG. 3 is a block diagram showing in detail the control unit 6 of FIG. The control unit 6 can form many parts by a digital circuit such as a DSP (digital signal processing device) or a microcomputer. The control unit 6 is roughly divided into first to fourth switches S1 to S4 of the inverter circuit 103. It comprises switch control means 10 for controlling and phase bias and islanding detection means 50 according to the present invention.

The switch control means 10 includes a capacitor current value creation means 11, an interconnection current command value generation means 12, an output current command value creation means 13, a feedback control signal formation means 14, and a switch control pulse formation means 15. .

  The capacitor current value creating means 11 is connected to the output lines 9uv, 9vw, 9wu of the voltage detecting means 5 in FIG. 2, and currents Icu, Icv, Icw indicated by three phases of the first and second filter capacitors Cu, Cw. Is obtained by calculation, and the calculated value is converted into first and second signals Icd and Icq indicated by a two-phase axis and output. The first and second signals Icd and Icq output from the capacitor current value creating unit 11 indicate the d-axis component and the q-axis component which are well-known three-phase / dq coordinate transformed. Therefore, in the following description, the first signal Icd may be referred to as a d-axis component current, and the second signal Icq may be referred to as a q-axis component current. Details of the capacitor current value creating means 11 will be described later.

The interconnection current command value generation means 12 is a target of the first, second and third phase interconnection currents Isu, Isv, Isw (instantaneous values) flowing through the first, second and third phase AC terminals 2u, 2v, 2w. D-axis component target interconnection current and q-axis component target linkage obtained by converting the first, second and third phase target interconnection currents Isu ', Isv' and Isw 'indicating the values by known three-phase / dq coordinate transformation. First and second interconnection current command values Isd ^* and Isq ^* corresponding to the system current are generated. The first and second interconnection current command values Isd ^* and Isq ^* can be arbitrarily set. Further, the interconnection current command value generating means 12 can be constituted by an arithmetic circuit, and the values of the first and second interconnection current command values Isd ^* and Isq ^* can be obtained by calculation. The first and second interconnection current command values Isd ^* and Isq ^* are expressed by the following determinant of (1), where the frequency of the interconnection current is ω, the effective value is I, and the power factor is cos θ. be able to.

The output current command value creating means 13 in FIG. 3 adds the d-axis component signal Icd obtained from the capacitor current value creating means 11 to the first linked current command value Isd ^* obtained from the connected current command value generating means 12. Is added to create the first output current command value Iod ^* , and the q-axis component signal Icq obtained from the capacitor current creation means 11 is added to the second interconnection current command value Isq ^* to obtain the second Create output current command value Ioq ^* . Details of the output current command value creating means 13 will be described later.

The feedback control signal forming means 14 is obtained from the first and second output current command values Iod ^* and Ioq ^* obtained from the output current command value creating means 13 and the first and third phase current detectors CTu and CTw. On the basis of the first and third phase output currents Iou and Iow of the lines 8u and 8w, the d-axis feedback control signal Ifd and the q-axis feedback control signal Ifq on the two-phase axis are formed, and dq / 3 The d-axis feedback control signal Ifd and the q-axis feedback control signal Ifq are rotationally transformed into the feedback control signal on the three-phase axis by the phase coordinate conversion means, and the first and the third of the three feedback control signals on the three-phase axis are converted. 2 feedback control signals Ifuv and Ifwv are output. Details of the feedback control signal forming means 14 will be described later.

  The switch control pulse forming means 15 is based on the first and second feedback control signals Ifuv and Ifwv obtained from the feedback control signal forming means 14, and the first, second, third and fourth switches S1, S2,. Well-known switch control pulses G1, G2, G3, G4 for ON / OFF control of S3 and S4 are formed. Details of the switch control pulse forming means 15 will be described later.

  FIG. 4 is a block diagram showing the control unit 6 of FIG. 3 in more detail. As is apparent from FIG. 4, the capacitor current value creating means 11 has a phase detecting means 20. This phase detection means 20 is connected to the output lines 9uv, 9vw9wu of the voltage detection means 5 of FIG. 1, and outputs a signal indicating the system voltage phase detection value θ = ωt of the system voltages Vuv, Vvw, Vwu.

  The lead phase angle signal forming means 21 connected to the phase detecting means 20 has a π / 2 generator 21a and an adding means 22b. The adding means 22b adds the phase angle π / 2 obtained from the π / 2 generator 21a to the system voltage phase detected value θ = ωt obtained from the phase detecting means 20, that is, 90 degrees, and advances by ωt + π / 2. A phase angle signal is formed.

  The three-phase output lines 9uv, 9vw, 9wu of the voltage detection means 5 of FIG. 1 and the first three-phase / dq coordinate conversion means 22 connected to the advance phase angle signal forming means 21 are obtained from the voltage detection means 5. The three-phase line voltages Vuv, Vvw, and Vwu are converted into rotational coordinates at the advance phase angle (ωt + π / 2) obtained from the advance phase angle signal forming means 21, and d-axis component voltages Vd and q indicated by the dq coordinate axes are used. The shaft component voltage Vq is output. That is, the first three-phase / dq coordinate conversion means 22 converts from three phases to two phases using rotational coordinate conversion. The three-phase line voltages Vuv, Vvw, Vwu input to the first three-phase / dq coordinate conversion means 22 can be expressed by the following equation (2), and a coordinate conversion matrix based on the lead phase angle ωt + π / 2. T can be expressed by the following equation (3), and the d-axis component voltage Vd and the q-axis component voltage Vq obtained from the first three-phase / dq coordinate conversion means 22 can be expressed by the following equation (4). The result can be shown by the following equation (5). In the following equations (2) to (5), V represents the effective value of each line voltage at the first, second and third phase AC terminals 2u, 2v and 2w, and Vs represents the line-to-line value represented by the instantaneous value. The voltages Vuv, Vvw, and Vwu are collectively shown, and Vdq is a d-axis component voltage Vd and a q-axis component voltage Vq that are instantaneous values.

  The two-phase axis virtual reactive current signal forming unit 23 connected to the first three-phase / dq coordinate conversion unit 22 includes first and second multipliers 23a and 23b. The first and second multipliers 23 a and 23 b connected to the first three-phase / dq coordinate conversion means 22 are connected to the d-axis component voltages Vd and q obtained from the first three-phase / dq coordinate conversion means 22. The axial component voltage Vq is multiplied by ωC to form the d-axis component virtual reactive current Iad and the q-axis component virtual reactive current Iaq. Here, ω represents the angular frequency of the fundamental wave, and C represents the capacitance of the first and second filter capacitors Cu and Cw. Here, the d-axis and q-axis component virtual reactive currents Iad and Iaq are obtained by the first and second multipliers 23a and 23b, but the d-axis and q-axis component voltages Vd and Vq are converted into the first and second filters. Dividing by the impedance 1 / ωC of the capacitors Cu and Cw can also be converted into d-axis and q-axis component virtual reactive currents Iad and Iaq. The d-axis and q-axis component virtual reactive currents Iad and Iaq here are filter capacitors having the same capacity as the first and second filter capacitors Cu and Cw between the first and third phase AC terminals 2u and 2w in FIG. Are connected to each other, and a value is assumed when a three-phase balanced filter capacitor circuit is formed.

  The inverse coordinate conversion means connected to the two-phase axis virtual reactive current signal forming means 23 and the phase detection means 20, that is, the dq / 3-phase coordinate conversion means 24 is the d-axis obtained from the two-phase axis virtual reactive current signal forming means 23. The component virtual reactive current Iad and the q-axis component virtual reactive current Iaq are subjected to rotational inverse coordinate conversion using the system voltage phase detection value (ωt), and a filter capacitor is also connected between the first and third phase AC terminals 2u and 2w. When the signal is assumed to be, signals indicating the first, second, and third three-phase axis virtual reactive currents Iau, Iav, Iaw are output. The input of the dq / 3-phase coordinate conversion means 24 is expressed by the following equation (6), the inverse coordinate conversion matrix T2 is expressed by the following equation (7), and the three-phase output is expressed by the following equation (8). A result can be shown by (9) Formula. Here, Iadq collectively indicates the d-axis and q-axis component virtual reactive currents Iad and Iaq, and Iauvw collectively indicates the three-phase axial virtual reactive currents Iau, Iav, and Iaw.

  The reactive current detection unit 25 connected to the dq / 3-phase coordinate conversion unit 24 is indicated by a phase inversion unit 26 and a termination unit 28. The dq / 3-phase coordinate conversion means 24 converts the two-phase input into the three-phase in the case of a three-phase balanced capacitor circuit assuming that the filter capacitor is also connected between the first and third phase AC terminals 2u and 2w. And reverse rotation coordinate conversion. Accordingly, it is necessary to form a signal indicating the actual current of the first and second filter capacitors Cu and Cw from the output of the dq / 3-phase coordinate conversion means 24. Therefore, the reactive current detection unit 25 regards the first three-phase virtual virtual reactive current Iau of the dq / 3-phase coordinate conversion means 24 as the first phase signal Icu indicating the reactive current flowing through the first filter capacitor Cu and transmits it. And a third-phase signal that is output as a third-phase signal Icw indicating a reactive current that flows through the second filter capacitor Cw by inverting the phase of the second three-phase virtual virtual reactive current Iav. Forming means 26 and termination means 28 for terminating the third three-phase virtual reactive current Iaw are provided. The termination means 28 is a signal termination means for not using the third three-phase axis virtual reactive current Iaw.

  In the second three-phase / dq coordinate conversion means 29, transmission paths 25u and 25w for the first and third phase signals Icu and Icw indicating the currents (reactive currents) of the first and second filter capacitors Cu and Cw are provided. The output transmission path 25v of the second phase signal forming means 27 is connected to form the second phase signal Icv. The second phase signal forming means 27 forms a second phase signal Icv corresponding to a phase inversion signal of a combined signal (addition signal) of the first phase signal Icu and the third phase signal Icw.

  The second three-phase / dq coordinate conversion means 29 connected to the transmission paths 25u, 25v, 25w and the phase detection means 20 for the first, second and third phase signals Icu, Icv, Icw are the first, second, The third phase signals Icu, Icv, and Icw are rotationally transformed with the system voltage phase detection value ωt to output a two-phase signal composed of the d-axis component current Icd and the q-axis component current Icq indicated by the dq coordinate axis. The input, coordinate transformation matrix T3, and output of the second three-phase / dq coordinate transformation means 29 can be expressed by the following equations (10), (11), and (12). In these equations, Icuvw collectively indicates the input first, second and third phase signals Icu, Icv and Icw, and Icdq indicates two outputs collectively.

The output current command value creating means 13 includes first and second adding means 30 and 31. The first addition means 30 includes a first interconnection current command value Isd ^* supplied from the interconnection current command value generation means 12 and a d-axis component current Icd supplied from the second three-phase / dq coordinate conversion means 29. Are added to create a first (d-axis) output current command value Iod ^* . The second addition means 31 includes a second interconnection current command value Isq ^* supplied from the interconnection current command value generation means 12 and a q-axis component current supplied from the second three-phase / dq coordinate conversion means 29. Icq is added to create a second (q-axis) output current command value Ioq ^* . Note that Isd ^* , Isq ^* , Icd, Icq, Iod ^* , and Ioq ^* indicate instantaneous values.

The feedback control signal forming unit 14 includes first and second deviation signal generating units 32 and 33, first and second amplifier circuits 34a and 34b, a dq / 3-phase coordinate converting unit 35, and a converting unit 41.
The conversion means 41 is connected to the first and third phase current detectors CTu, CTw of FIG. 1 by lines 8u, 8w, and is also connected to the phase bias and islanding detection means 50 according to the invention and is shown in three phases. Forming a current, and converting the current indicated by the three phases into a two-phase signal composed of a d-axis component current Iod and a q-axis component current Ioq indicated by the dq coordinate axes. This is sent to the second deviation signal creating means 32, 33.

More specifically, as shown in FIG. 5, the converting means 41 includes a second phase signal forming means 44 and a third three-phase / dq coordinate converting means 45. The second phase signal forming means 44 is connected to the lines 8u and 8w and corresponds to a signal obtained by inverting the phase of the combined signal (addition signal) of the first phase output current Iou of the line 8u and the third phase output current Iow of the line 8w. The second phase output current Iov is sent to the line 8v. Therefore, the second phase signal forming means 44 in FIG. 5 has the same function as the second phase signal forming means 27 in FIG. Instead of providing the second phase signal forming means 44, the second phase output current Iov of the current path between the intermediate terminal 1c in FIG. 2 and the connection point of the first and second filter capacitors Cu and Cw is changed. It is also possible to provide a second phase current detector for detection and send the output of the second phase current detector to the third three-phase / dq coordinate conversion means 45 in FIG.

The third three-phase / dq coordinate conversion means 45 connected to the lines 8u, 8v, 8w in FIG. 5 is a current phase command θi after the addition of the phase bias obtained from the line 53 of the phase bias and islanding detection means 50. , Which has the same function as that of the second three-phase / dq coordinate conversion means 29 in FIG. 4, and includes the first phase, the second phase, and the third phase indicated by three phases. The phase output currents Iou, Iov, and Iow are converted into two-phase signals composed of a d-axis component current Iod and a q-axis component current Ioq indicated by the well-known dq coordinate axes, and sent to lines 42 and 43.

4 is connected to the first addition means 30 of the output current command value creation means 13 and the output line 42 of the conversion means 41, and the first (d-axis) output current command value. A signal indicating the difference between Iod ^* and the d-axis component current Iod is output. The second deviation signal creation means 33 is connected to the second addition means 31 of the output current command value creation means 13 and the output line 43 of the conversion means 41, and the second (q-axis) output current command value Ioq ^* and A signal indicating a difference from the q-axis component current Ioq is output. The first and second amplifying circuits 34 and 35 connected to the first and second deviation signal generating means 32 and 33 respectively amplify, amplify and adjust the respective deviation signals to adjust the d-axis on the two-phase axis. A feedback control signal Ifd and a q-axis feedback control signal Ifq are formed. A known dq / 3-phase coordinate conversion means 35 connected to the first and second amplifier circuits 34a and 34b rotates the d-axis feedback control signal Ifd and the q-axis feedback control signal Ifq to a feedback control signal on the three-phase axis. The first and second feedback control signals Ifuv and Ifwv of the three feedback control signals on the three-phase axis are output after coordinate conversion.

  The switch control pulse forming means 15 is a known PWM pulse forming circuit comprising a sawtooth wave generator 36, first and second comparators 37 and 38, and a drive circuit 39.

  The sawtooth generator 36 generates a sawtooth voltage Vt at a frequency (for example, 10 to 100 kHz) sufficiently higher than the frequency (for example, 50 Hz) of the AC voltage of the first, second, and third phase AC terminals 2u, 2v, and 2w. To do. Instead of the sawtooth wave generator 36, a means for generating another comparative wave (carrier wave or periodic waveform) such as a triangular wave may be provided.

  The first comparator 37 is connected to the terminal for outputting the first feedback control signal Ifuv of the dq / 3-phase coordinate conversion means 35 included in the feedback control signal forming means 14 and the sawtooth generator 36. The feedback control signal Ifuv of 1 and the sawtooth voltage Vt are compared as shown in FIG. 9A, and the first PWM pulse Vp1 shown in FIG. 9B is output. The second comparator 38 is connected to the terminal for outputting the second feedback control signal Ifwv of the dq / 3-phase coordinate conversion means 35 included in the feedback control signal forming means 14 and the sawtooth generator 36. The second feedback control signal Ifwv and the sawtooth voltage Vt are compared as shown in FIG. 9A, and the second PWM pulse Vp2 shown in FIG. 9C is output. Since the first feedback control signal Ifuv controls the first phase current of the three-phase alternating current, it can also be called the first phase feedback control signal. Further, since the second feedback control signal Ifwv controls the third-phase AC third-phase current, it can also be called a third-phase feedback control signal.

  The drive circuit 39 connected to the first and second comparators 37 and 38 amplifies the first PWM pulse Vp1 to form the first control pulse G1, which is converted into the first switch S1 in FIG. And the first PWM pulse Vp1 is inverted and amplified to form the second control pulse G2, which is sent to the second switch S2, and the second PWM pulse Vp2 is amplified and the third PWM pulse Vp2 is amplified. Control pulse G3 is formed and sent to the third switch S3, and the second PWM pulse Vp2 is inverted and amplified to form the fourth control pulse G4, which is sent to the fourth switch S4. .

FIG. 6 shows in detail the phase detection means 20 and the phase bias and islanding detection means 50 of FIG. The phase detection means 20 is roughly divided into an angular velocity detection means 55 and a system voltage phase detection means 56, which outputs a signal indicating the angular speed ω _c from the angular speed detection means 55 to the line 52 and from the system voltage phase detection means 56 to the line. A signal indicating the system voltage phase detection value θ = ωt is output to 51.

FIG. 7 shows the system voltage phase detection means 20 of FIG. 6 in more detail. The angular velocity detection means 55 included in the phase detection means 20 includes a three-phase / dq coordinate conversion means 57 and a proportional integration circuit 58. The three-phase / dq coordinate conversion means 57 of the angular velocity detection means 55 is connected to the three-phase output lines 9uv, 9vw, 9wu as well as the first three-phase / dq coordinate conversion means 22 in FIG. It is connected to a line 51 that outputs a signal indicating the detected value θ = ωt. Therefore, the three-phase / dq coordinate conversion means 57 converts the three-phase phase voltages Vu, Vv, Vw created based on the three-phase line voltages Vuv, Vvw, Vwu obtained from the voltage detection means 5 into the system voltage. A rotational coordinate conversion is performed with the phase detection value ωt to obtain a two-phase signal indicated by the dq coordinate axis, and a q-axis component voltage Vq which is one of the two-phase signals is output. The q-axis component voltage Vq includes information indicating the phase difference between the voltage phase (reference phase) of the three-phase AC power system 3 and the system voltage phase detection value. Accordingly, a signal indicating the angular frequency of the system voltage, that is, the angular velocity ω _c can be obtained from the proportional integration means 58 connected to the three-phase / dq coordinate conversion means 57. A signal indicating the angular velocity ω _c (rad / sec) obtained from the proportional integration means 58 is sent to the system voltage phase detection means 56 and also to the phase bias and islanding detection means 50.

The system voltage phase detection means 56 of FIG. 7 comprises a reference angular velocity generation means 59, a subtraction means 60, and an integration means 61 indicated by 1 / s. The reference angular velocity generating means 59 outputs a signal indicating the reference angular velocity ω _b (rad / sec) according to the frequency of the three-phase AC power system 3. The subtracting means 60 outputs a signal indicating the difference between the reference angular velocity ω _b obtained from the reference angular velocity generating means 59 and the angular velocity ω _c obtained from the proportional integration means 58. The integrating means 61 connected to the subtracting means 60 outputs a signal indicating the system voltage phase detection value θ = ωt (rad). This system voltage phase detection value θ means a reference phase command for the inverter output current, and is sent to the three-phase / dq coordinate conversion means 57 of FIG. Further, as shown in FIG. 4, the signal is also sent to the advance phase angle signal forming means 21, the dq / 3 phase coordinate converting means 24, the 3 phase / dq coordinate converting means 29, and the dq / 3 phase coordinate converting means 35. This system voltage phase detection value θ has a value for making the phase of the inverter output current coincide with the voltage phase (reference phase) of the three-phase AC power system 3.

  As apparent from FIG. 6, the phase bias and islanding detection means 50 is roughly divided into an angular velocity change amount detection means 62, a phase bias value generation means 63, a tilted phase bias value generation means 64, a mode switching means 65, An independent operation detection unit 66 and a phase bias addition unit 67 are included. Hereinafter, each part will be described in more detail with reference to the waveform diagram of FIG.

The angular velocity change amount detection means 62 detects the angular velocity change amount of the inverter output, and comprises a delay means 62a and a subtraction means 62b as shown in FIG. The delay means 62a gives 1 / {1 + sT}, where T is the time required for the output to rise to a predetermined value (0.632), and s is a known first order delay that can be represented by a known differential symbol. Therefore, it is connected to the angular velocity detection means 55 and outputs a delayed signal of the angular velocity ω _c . The subtracting means 62b has one input terminal connected to the angular velocity detecting means 55 and the other input terminal connected to the delay means 62a. The subtracting means 62b is obtained from the angular velocity ω _c obtained from the angular velocity detecting means 55 and the delay means 62a. The system voltage angular velocity change Δω consisting of the difference from the delayed signal is output.
Note that the angular velocity ω _c input to the subtraction means 62b is the average of a plurality of samples of the angular speed ω _c obtained from the angular velocity detection means 55, and the delay signal input to the subtraction means 62b is the delay signal obtained from the delay means 62a. The average of multiple samples. Therefore, the angular velocity change amount Δω of the present invention means one angular velocity change amount or an average angular velocity change amount of a plurality of samples.

In this embodiment, the inverter output current phase command value θi changes with a minute phase bias according to the sign of the angular velocity change amount Δω obtained from the angular velocity detecting means 55. In FIG. 8A, an ideal voltage waveform A composed of a sine wave is indicated by a dotted line, and a detection voltage waveform (actual voltage waveform) B is schematically indicated by a solid line. The ideal voltage waveform A shows an ideal AC system voltage waveform when the first phase voltage is connected to the AC terminal 2u. The detected voltage waveform B shows the detected voltage waveform of the first phase voltage at the AC terminal 2u, that is, the actual system voltage waveform. Since the output current of the inverter device 100 is controlled to be in phase with the system voltage, the output current waveform of the inverter device 100 corresponds to the detected voltage waveform B of FIG.
8 shows a grid-connected operation state, that is, a state in which power is supplied to the load 101 in both the inverter device 100 and the three-phase AC power system 3 in the period from time t0 to time t5. A single operation state after time t5, that is, a state where electric power is supplied to the load 101 only by the inverter device 100 is shown.
In the grid interconnection operation before time t5, the detected voltage waveform (actual voltage waveform) B changes along with the ideal voltage waveform A with a slight phase change. The output current also follows the system voltage, that is, the detected voltage waveform B, with a slight phase change based on the positive (first direction) phase bias value + α and the negative (second direction) phase bias value −α. Change. At the time of the independent operation after the time t5, the inverter device 100 and the AC power system are disconnected from each other, so that the detected voltage waveform B (inverter output voltage waveform) is unidirectional from the ideal voltage waveform A at the time of interconnection due to the load impedance characteristics Deviation (for example, in the positive direction).

In FIG. 8, for example, at time t1, the angular velocity change amount (Δω) shown in (B) is negative, so that the negative phase bias value −α is added as the phase bias value (θ1) in the period t1 to t2, Since the angular velocity change amount (Δω) is positive at t2, the positive phase bias + α is added as the phase bias value (θ1) during the period from t2 to t3.
Further, during the single operation after t5 in FIG. 8, the angular velocity change amount Δω increases with an inclination in one direction (for example, the positive direction). Therefore, it is possible to detect whether or not the vehicle is operating alone by monitoring the angular velocity change amount Δω obtained from the angular velocity change amount detecting means 62. Further, the phase bias value can be determined based on the angular velocity change amount Δω.

The positive / negative phase bias value generating means 63 includes an angular velocity change amount direction determining means 63a connected to the angular velocity change amount detecting means 62 via the contact a of the changeover switch 65a of the mode changing means 65, and the angular velocity change amount direction determining means. It comprises a positive phase bias value generating means 63b and a negative phase bias value generating means 63c connected to 63a, respectively.

The angular velocity change amount direction determining means 63a determines whether or not the angular velocity change amount Δω is a value in the first direction, that is, a positive direction (in this embodiment, zero is also regarded as a value in the positive direction). The positive phase bias value generating means 63b responds to the output of the angular velocity change amount direction determining means 63a indicating that the angular velocity change amount Δω is a value in the positive direction, for example, the positive phase shown in the period t0 to t1 in FIG. A bias value + α is generated. The negative phase bias value generating means 63c responds to the output of the angular velocity change amount direction determining means 63a indicating that the angular velocity change amount Δω is not a positive value, that is, a negative value, for example, as shown in FIG. The negative phase bias value −α shown in the period from t1 to t2 is generated. The generation position and the duration of the positive phase bias value + α and the negative phase bias value −α vary irregularly. The duration of the positive phase bias value + α and the negative phase bias value −α is sufficiently shorter than the system voltage period.
Even if no phase bias is applied to the inverter current phase, the ideal voltage waveform A and the detected voltage waveform B shown in FIG. Therefore, the positive phase bias value + α and the negative phase bias value −α are automatically obtained after the operation of the inverter device is started.
The positive phase bias value generating means 63b and the negative phase bias value generating means 63c are further different from a common output line 63d that transmits a positive / negative phase bias value Δθ ₁ composed of a composite value of the positive phase bias value and the negative phase bias value. The line 68 is connected to one input terminal of the phase bias adding means 67. The other input terminal of the phase bias adding means 67 is connected to the system voltage phase detecting means 56 via the line 51. The phase bias adding means 67 obtains a current phase command value θ _i = ω _it which is a value obtained by adding the phase bias value Δθ of the line 68 to the signal indicating the system voltage phase detection value θ = ωt (rad) of the line 51 in FIG. Output to the output line 53 as shown in E).

The output line 53 of the phase bias adding means 67 is connected to the converting means 41 of the feedback control signal forming means 14 as shown in FIG. The feedback control signal forming means 14 is a first and second (first phase and third phase) feedback control signal for flowing an inverter output current corresponding to the current phase command value θ _i given from the phase bias adding means 67. Forms Ifuv, Ifwv.

The inclination phase bias value generation means 64 is connected to the angular velocity change amount detection means 62 via the contact b of the changeover switch 65a of the mode change means 65, and diverges from the time point t8 during the single operation as shown in FIG. A tilt phase bias value Δθ _2, which can also be called a phase bias value, is output. The gradient phase bias value generating means 64 can be constituted by, for example, an amplifying means for gain K or a multiplying means for multiplying a coefficient K. The output line 64 a of the gradient phase bias value generating means 64 is connected to one input terminal of the phase bias adding means 67 via a line 68. The phase bias adding means 67 generates a current phase command value θ _i consisting of a value obtained by adding the slope phase bias value Δθ ₂ of the line 68 to the signal indicating the system voltage phase detection value θ = ωt from the time point t8 in FIG. Output as shown in E). The tilt phase bias value Δθ ₂ generated from the tilt phase bias value generating means 64 is used to accelerate the increase in the angular velocity change amount Δω and accelerate the detection of the single operation.

The mode switching means 65 includes an angular velocity change level determining means 65b, a counter 65c, and a switching control means 65d in addition to the changeover switch 65a. The angular velocity change amount direction determining means 65b connected to the angular velocity change amount detecting means 62 has a predetermined sampling period in which the direction of the angular velocity change amount Δω is the first direction, that is, the positive direction (however, zero is also regarded as the positive direction). A positive pulse is generated when Δω = 0 and Δω> 0, and a negative pulse is generated when Δω <0. More specifically, for example, the angular velocity change amount determining means 65b indicates the direction of the angular velocity change amount Δω in FIG. 8B during the periods t4 to t5, t5 to t6, t6 to t7, and t7 to t8 in FIG. The determination is made, and the determination results are output at time points t5, t6, t7, and t8. Note that the angular velocity change amount direction determining means 65b of the mode switching means 65 has the same function as the angular velocity change amount direction determining means 63a of the positive / negative phase bias value generating means 63 described above, so two angular velocity change amount direction determining means. Either one of 63a and 65b can be omitted, and the remaining one can be shared by the mode switching means 65 and the positive / negative phase bias value generating means 63.

The counter 65c connected to the angular velocity change amount direction determining means 65b receives a determination result indicating a positive direction (including zero) or a negative direction continuously from the angular velocity change amount direction determining means 65b a predetermined number of times (here, four times). It is counted whether it was obtained or not. Since four positive pulses are continuously input to the counter 65c from t5 to t8 in FIG. 8B, the counter 65c outputs a signal indicating that four positive pulses have been continuously counted at time t8. Output.
That is, during the grid connection operation before time t5 in FIG. 8, the amount of change in the angular velocity of the system voltage (Δω) does not continuously become the same direction four times, but during the single operation after time t5, The detected voltage waveform B (inverter voltage waveform) deviates from the ideal voltage waveform A (system voltage waveform at the time of interconnection), and the angular velocity change Δω becomes positive four times (four sampling cycles) continuously, at time t8. Thus, the output of the counter 65c is changed from the first value (for example, low level) to the second value (for example, high level). The counter 65c in the present embodiment generates an output indicating that when the signal indicating that the angular velocity change amount Δω is in the positive or negative direction is continuously generated four times or more, the four times However, the number of times can be changed to any number of times capable of estimating the isolated operation. The counter 65c can be replaced with a logic circuit having an equivalent function.

  The switching control means 65d connected to the counter 65c responds to the output indicating that the angular velocity change amount Δω obtained from the counter 65c is four times or more in the positive or negative direction, and the mode switching control shown in FIG. The signal Sm is sent to the control terminal of the mode changeover switch 65a, and the contact of the mode changeover switch 65a is turned on.

In FIG. 8, the contact b of the mode changeover switch 65a is turned on at time t8, the tilt phase bias value generating means 64 is connected to the angular velocity change amount detecting means 62, and the divergent type as shown in FIG. A tilt phase bias value Δθ ₂ is generated from time t8.

The isolated operation detecting means 66 comprises a reference value generating means 66a and a comparing means 66b. As shown in FIG. 8B, the reference value generating means 66a generates a reference value Δω _r that is a little higher than the amount of change in angular velocity during grid connection operation.

The comparison means 66b has one input terminal connected to the angular velocity change amount detection means 62 via the contact b of the mode changeover switch 65a and the other input terminal connected to the reference value generation means 66a. The angular velocity change amount Δω is compared with the reference value Δω _r as shown at time t9 in B), and the first level (logic 0) when the angular velocity change amount Δω becomes higher than the reference value Δω _r. An isolated operation detection signal Ss that changes from the current level to the second level (theoretical value 1) is output to the line 54 as shown in FIG. The line 54 is connected to the control terminal of the circuit breaker 104 as shown in FIG. 2, and the circuit breaker 104 is turned off in response to the second level isolated operation detection signal Ss on the line 54. . It is also possible to connect an alarm device such as sound or light to the line 54 to notify the individual operation by the alarm device.

  In FIG. 6, one input terminal of the comparison means 66b is connected to the angular velocity change amount detection means 62 via the mode changeover switch 65a, but this input terminal does not go through the mode changeover switch 65a as indicated by a broken line 69. It can also be directly connected to the angular velocity change amount detecting means 62.

Next, an operation for supplying power to the load 101 using the inverter device 100 will be described. During the grid connection operation, the circuit breakers 102 and 104 in FIG. 1 are kept on. The interconnection current command value generation means 12 in FIG. 4 is a value in which the power factor by the voltage Vs of the three-phase AC power system 3 and the first, second and third phase interconnection currents Isu, Isv, Isw is close to 1 or 1. (It is desirable to be 0.85 or more.) First and second interconnection current command values Isd ^* and Isq ^* having values that can be obtained are generated. The first and second interconnection current command values Isd ^* and Isq ^* are the d-axis component and q-axis component currents Icd and Icq obtained from the second three-phase / dq coordinate conversion unit 29 of the capacitor current value creation unit 11. Are the same d-axis component and q-axis component of the known dq coordinate axis (orthogonal coordinate axis), so that the first and second output current command values Iod ^* and Ioq ^* can be easily determined by combining them. . The first-phase and third-phase output currents Iou, Iow flowing in the first-phase and third-phase reactors Lu, Lw are in the state of the desired power factor (preferably 1), the first, second, and third-phase interconnection currents Isu. , Isv, Isw are feedback controlled. As a result, the first, second, and third phase interconnection currents Isu, Isv, Isw can be caused to flow so that the power factor becomes 1 by controlling the first and third phase output currents Iou, Iow of the inverter. Since the operation of the main circuit of the three-phase V-connection inverter is well known, the description thereof is omitted.

  During maintenance inspection of the load 101, the circuit breakers 102 and 104 are turned off in principle. If one circuit breaker 102 is off and the other circuit breaker 104 is kept on, the circuit breaker 104 is in an isolated operation, which poses a risk to the maintenance inspector of the load 101 as already described. In this embodiment, even if the circuit breaker 104 is forgotten to be manually turned off, the single operation is immediately canceled by the action of the phase bias and the single operation detection means 50, and the power supply from the inverter device 100 to the load 101 is stopped. Stop.

This embodiment has the following effects.
(1) In this embodiment, a positive / negative phase bias value Δθ ₁ that changes so as not to depend on the system frequency is created, the phase of the inverter output current is shifted by this positive / negative phase bias value Δθ ₁ , and the inverter device 100 is based on this. Detecting isolated operation. Therefore, it is possible to detect an isolated operation without giving a disturbance at or near the system frequency. For this reason, the load 101 is not disturbed at or near the system frequency, and the malfunction of the load 101 can be prevented. Note that the minute change in the inverter output current due to the positive / negative phase bias value Δθ ₁ in this embodiment is within the THD defined in IEC60950 and does not adversely affect the load 101.
(2) The angular velocity change amount Δω changes in a time sufficiently shorter than the system voltage cycle during grid connection operation, and continuously shows the value in the same direction during the single operation, so that the single operation can be detected quickly (for example, the system Within one cycle of the voltage cycle).
(3) Since the isolated operation is detected by adding the divergence type tilt phase bias value Δθ ₂ to the current phase command, the isolated operation can be detected quickly and accurately.
(4) In this embodiment, the power factor can be controlled to 1 or almost 1 with a circuit that does not include two current detectors for detecting the first-phase and third-phase interconnection currents Isu and Isw. Therefore, it is possible to reduce the size and cost of the three-phase V-connection inverter. This effect is obtained regardless of the addition of the phase bias value Δθ ₁ . Therefore, when only this effect is obtained, the conversion means 41 can be directly connected to the output line 51 of the phase detection means 20 without the phase bias and the isolated operation detection means 50. Further, the output line 53 of the phase bias and islanding detection means 50 and the output line 51 of the phase detection means 20 can be selectively connected to the conversion means 41.
(5) Since it is a three-phase V-connection inverter, the number of switches can be reduced by two compared to a three-phase full-bridge type inverter, and miniaturization and cost reduction are achieved.
(6) The d-axis component current Icd and the q-axis component current Icq are formed by the capacitor current value creation means 11, and the first and second linkages as the d-axis and q-axis components from the interconnection current command value generation means 12. Since system current command values Isd ^* and Isq ^* are generated, control of the three-phase V-connection inverter can be easily achieved.
(7) It is not necessary to synchronize the current phase command values θ _i in the first and second inverter devices 100 and 100 ′ for detecting an independent operation. Therefore, the isolated operation detection of the first inverter device 100 can be performed independently without being restricted by the isolated operation detection of the second inverter device 100 ′.

  In the inverter device of the second embodiment, the capacitor current creating means 11 of the first embodiment is transformed into a capacitor current value creating means 11a shown in FIG. Therefore, also in the description of the second embodiment, reference is made to FIGS. 1 to 9 showing the first embodiment, and description of common portions is omitted.

  10 includes a fixed current value generating means 40, a phase detecting means 20, a second phase signal forming means 27, and a three-phase / dq coordinate converting means 29.

  The fixed current value generation means 40 has substantially the same function as the reactive current detection unit 25 and the portion before this in the capacitor current value creation means 11 of the first embodiment of FIG. In addition, a signal substantially the same as the third phase signals Icu and Icw is fixedly generated. That is, the first-phase and third-phase signals Icu and Icw generated from the fixed current value generating means 40 are the effective value V and the frequency of the line voltage at the first, second and third-phase AC terminals 2u, 2v and 2w. ω and the capacitance C of the first and second filter capacitors Cu and Cw are fixed values, and are determined by calculations according to the following equations (13), (14), and (15).

  Since the phase detection means 20, the second phase signal formation means 27, and the three-phase / dq coordinate conversion means 29 in FIG. 10 are the same as those indicated by the same symbols in FIG.

  In the second embodiment, when the voltage of the three-phase AC power system 3 is stable, the first phase and the third phase indicating the reactive currents of the first and second filter capacitors Cu and Cw are fixed. Even if the phase signals Icu and Icw are determined, these values are almost the same as when the actual measurement values are used.

  The second embodiment has the same effect as the first embodiment. In addition, since the first and third phase signals Icu and Icw are generated by the fixed current value generating means 40, the number of operations in the capacitor current value creating means 11a is determined according to the embodiment. Compared to 1, it has the effect of being able to reduce and enabling high-speed arithmetic processing.

  The inverter device of Example 3 is the same as that of Example 1 except that the control unit 6 of FIG. 4 of Example 1 is changed to the control unit 6a of FIG. Therefore, also in description of Example 3, FIGS. 1-9 which show Example 1 are referred, and description of a common part is abbreviate | omitted.

Modified control unit 6a in FIG. 11, a line 53 for transmitting the current phase command theta _i of phase bias and independent operation detecting unit 50 to the converting means 41 contained in the feedback control signal forming means 14 shown in FIG. 4 Instead of the connection, the line 53 is connected to the interconnection current command value generating means 12, and the others are formed in the same manner as in FIG.

11 generates first and second interconnection current command values Isd ^* and Isq ^* in accordance with the current phase command θ _i given from the phase bias and islanding detection means 50. The interconnection current command value generation unit 12 shown in FIG. . The first and second interconnection current command values Isd ^* and Isq ^* in FIG. 11 indicate target values of the inverter output current, and the first and second interconnection current command values Isd ^* , It is created in the same way as Isq ^* .

As shown in the third embodiment of FIG. 11, even if the phase of the target value of the inverter output current is changed according to the current phase command θ _i of the line 53, the isolated operation can be detected quickly and accurately as in the first embodiment. And the same effects as those of the first embodiment can be obtained.

FIG. 12 shows an electric power system including a modified inverter device 100a according to the fourth embodiment. The modified inverter device 100a of FIG. 12 replaces the inverter device 100 having the three-phase V-connection configuration shown in FIGS. 1 and 2 with the inverter device 100a having the three-phase full bridge configuration, and the other configuration is the inverter device of the first embodiment. 100. Therefore, in FIG. 12, the same reference numerals are given to the portions configured substantially the same as those in FIGS. 1 to 7, and the description thereof is omitted.

The inverter circuit 103a included in the inverter device 100a of FIG. 12 is formed of an inverter circuit having a well-known three-phase full bridge configuration including six switching elements. Reactors Lu, Lv, Lw of each phase are connected between the inverter circuit 103a and the first, second, and third AC output terminals 2u, 2v, 2w. Further, first, second and third filter capacitors Cu, Cv, Cw Y-connected to the first, second and third AC lines are connected. The first, second, and third filter capacitors Cu, Cv, and Cw can be connected between the first, second, and third AC lines. The first, second, and third phase current detectors CTu, CTv, CTw for detecting the current flowing through the first, second, and third AC output terminals 2u, 2v, 2w are the first, second. And electromagnetically coupled to the third phase AC line.

12 has the same function as that of the control circuit 4 of FIG. 1, and in order to obtain the same function as the switch control means 10 of FIG. It has a control signal forming means 14a, a switch control pulse forming means 15a, and a phase detection means 20, and further has a phase bias and islanding detection means 50 according to the present invention. For convenience, the voltage detection means 5 'shown outside the control circuit 4' is connected to the first, second and third phase AC lines and has the same function as the voltage detection means 5 of FIG. The voltage detection means 5 ′ and the first, second and third current detectors CTu, CTv, CTw can be included in the control circuit 4 ′.

The interconnection current command value generation means 12a has the same function as the interconnection current command value generation means 12 and the output current command value creation means 13 in FIG. 3, and generates an interconnection current command value, that is, an inverter output current command value. This is a known circuit. In FIG. 12, the current phase command θ _i generated from the phase bias and isolated operation detecting means 50 according to the present invention is supplied to the interconnection current command value generating means 12a.

  The feedback control signal forming means 14a connected to the interconnection current command value generating means 12a and the first, second and third current detectors CTu, CTv, CTw is similar to the feedback control signal forming means 14 of FIG. This is a known circuit having a function. The switch control pulse forming means 15a connected to the feedback control signal forming means 14a is a well-known circuit having the same function as the switch control pulse forming means 15 of FIG. 3, and is a control pulse for the six switches of the inverter circuit 103a. Form. The phase detection means 20 and the phase bias / independent operation detection means 50 of FIG. 12 are configured in the same manner as shown by the same reference numerals in FIG.

The inverter device 100a having the three-phase full bridge configuration in FIG. 12 has the same phase bias and single operation detection means 50 as in FIG. 3, and thus has the same effect as that of the first embodiment in FIGS.

The present invention is not limited to the above-described embodiments, and for example, the following modifications are possible.
(1) The first-phase and third-phase current detectors CTu and CTw in FIG. 1 are connected to the current path between the first and second filter capacitors Cu and Cw and the first and third-phase AC terminals 2u and 2w. The first phase and the third phase interconnection currents Isu and Isw can be detected by moving. In the case of this modification, the same capacitor current value creating means 11 of FIG. 2 or the capacitor current value creating means 11a of FIG. 6 is provided, and the position of the interconnecting current command value generating means 12 of FIG. An output current command value creating means is arranged, and a linkage current command value generating means is arranged at the position of the output current command value creating means 13 in FIG. 2, and the output stage of this linkage current command value generating means is the same as in FIG. The feedback control signal forming means 14 and the switch control pulse forming means 15 are arranged in the above.
The output current command value creating means in the case of this modification corresponds to the first, second and third phase output currents Iou, Iov, Iow of the inverter of FIG. 1 (d axis) and second (q axis) output current command values Iod ^* and Ioq ^* are generated. Further, the interconnected current command value generating means in the case of this modification is the first (d-axis) output current command value Iod ^* and the capacitor current value creating means obtained from the output current command value creating means of this modification. The first (d-axis) interconnection current command value Isd ^* is created based on the first signal Icd obtained from 11 or 11a, and the second (q-axis) output current command value Ioq ^* and the capacitor Based on the second signal Icq obtained from the current value creating means 11 or 11a, a second (q-axis) interconnection current command value Isq ^* is created. In addition, the feedback control signal forming means in this modification example is input with the detected values of the first and third phase interconnection currents Isu and Isw obtained from the first and third phase current detectors CTu and CTw. And a means for forming the second phase interconnection current Isv based on the detected values of the first phase and third phase interconnection currents Isu and Isw, and further, the first phase, second and third phase interconnection currents Isu and Isv. , Isw is subjected to rotational coordinate conversion to provide a three-phase / dq coordinate conversion means for obtaining a d-axis component current Isd and a q-axis component current Isd of the dq coordinate axis. The first and second deviation signal creation means 32 and 33 shown in FIG. 3 are the first and second linkage current command values Isd ^* and Isq ^* obtained from the linkage current command value creation means and the three-phase / dq. A deviation between the d-axis component current Isd and the q-axis component current Isd obtained from the coordinate conversion means is obtained to form a d-axis feedback control signal Ifd and a q-axis feedback control signal Ifq on the two-phase axis. Further, similarly to FIG. 4, the d-axis feedback control signal Ifd and the q-axis feedback control signal Ifq are rotationally converted into feedback control signals on the three-phase axis by known dq / 3-phase coordinate conversion means, and the three-axis axis is converted. Of the three feedback control signals, the first and third phase feedback control signals Ifuv and Ifwv are formed. Even in this modification, a second phase current detector for detecting the second interconnection current Isv can be provided instead of obtaining the second phase interconnection current Isv by calculation.
(2) Instead of the first and second voltage dividing capacitors Ca and Cb having the same capacity, the first and second storage batteries having the same voltage can be connected.
(3) If the harmonic currents or the high-frequency components may be included in the interconnection currents Isu, Isv, Isw, the linkage current command value generation means 12 can be modified to correspond to this.
(4) The phase detection means 20 for phase control is not used as the angular velocity change amount detection means 62, but a dedicated phase detection means for the angular velocity change amount detection means 62 can be provided.
(5) In FIG. 6, instead of detecting whether or not the angular velocity change amount Δω is continuously in the positive direction four times by the counter 65c, the angular velocity change amount Δω indicates the positive direction continuously for a predetermined time or more. It is possible to detect whether or not the vehicle is isolated.
(6) When the single operation can be accurately detected by the counter 65c, the gradient phase bias value generating means 64 can be omitted.
(7) In FIG. 6, the angular velocity change amount direction determining means 63a is shown separately from the positive phase bias value generating means 63b and the negative phase bias value generating means 63c, but the angular velocity change amount direction determining means 63a and the positive phase bias are shown. The value generating unit 63b is integrated, the angular velocity change amount direction determining unit 63a and the negative phase bias value generating unit 63c are integrated, or the angular velocity change amount direction determining unit 63a and the positive phase bias value generating unit 63b. The negative phase bias value generating means 63c can be integrated. In short, the positive / negative phase bias value generating means 63 may be any circuit as long as it can generate the positive phase bias value and the negative phase bias value according to the angular velocity change amount.

It is a circuit diagram which shows the electric power grid | system containing the inverter apparatus according to Example 1 of this invention. It is a circuit diagram which shows the inverter apparatus of FIG. 1 in detail. It is a block diagram which shows the control part of FIG. 2 in detail. It is a block diagram which shows the control part of FIG. 3 in more detail. FIG. 5 is a block diagram illustrating in detail a conversion unit included in the feedback control signal forming unit of FIG. 4. It is a block diagram which shows in detail the phase detection means of FIG. 4, a phase bias, and an independent operation detection means. It is a block diagram which shows the phase detection means and angular velocity change amount detection means of FIG. 6 in more detail. It is a wave form diagram which shows the state of each part of FIG.2 and FIG.6. It is a wave form diagram which shows the state of each part of FIG. It is a block diagram which shows the capacitor electric current value preparation means of Example 2. FIG. 10 is a block diagram illustrating a control unit according to a third embodiment. It is a circuit diagram which shows the electric power system containing the inverter apparatus according to Example 4.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 DC power supply 1a, 1b 1st and 2nd DC input terminal 2u, 2v, 2w 1st, 2nd, and 3rd phase alternating current output terminal 3 3 phase alternating current power system 4 Control circuit 5 Voltage detection means 6 Control part 20 Phase Detection means 50 Phase bias and isolated operation detection means 62 Angular velocity change amount detection means 63 Positive / negative phase bias value generation means 64 Inclination phase bias value generation means 67 Phase bias addition means

Claims (5)

An inverter device for supplying power to a load in connection with an AC power system,
A DC input terminal connected to a DC power supply;
An AC output terminal connected to the load and the AC power system;
A DC-AC conversion circuit connected to the DC input terminal and having a plurality of DC-AC conversion switches;
Current detection means for detecting current flowing through the AC output terminal;
Voltage detecting means for detecting a system voltage at the AC output terminal;
The plurality of current detection means, the voltage detection means, and the plurality of DC-AC conversion switches connected to the control terminals of the plurality of DC-AC conversion switches so that the phase of the current flowing through the AC output terminal matches the phase of the system voltage. Switch control means for controlling on / off of the DC-AC conversion switch;
Phase detection means for detecting the phase (θ) of the system voltage;
Angular velocity change amount detecting means for detecting the angular velocity change amount (Δω) of the system voltage;
When the direction of the angular velocity variation (Δω) obtained from the angular velocity variation detection means is the first direction, a phase bias value (+ α) in the first direction is output, and the angular velocity variation (Δω) Phase bias value generating means for outputting a phase bias value (−α) in the second direction when the direction is the second direction;
The current phase command signal (θi) is switch-controlled by adding the system voltage phase detection value (θ) obtained from the phase detection means and the phase bias value (Δθ ₁ ) obtained from the phase bias value generation means. Adding means for supplying to the means;
Angular velocity variation reference value generating means for generating an angular velocity variation reference value (Δω _r );
The angular velocity change amount (Δω) is compared with the angular velocity change amount reference value (Δω _r ), and when the angular velocity change amount (Δω) is larger than the angular velocity change amount reference value (Δω _r ), An inverter device comprising: an isolated operation detecting unit that outputs a signal indicating that power is supplied from the inverter device without supplying power from the AC power system to a load. Furthermore, a tilt phase bias value generating means for generating a tilt phase bias value (Δθ ₂ ) whose phase bias value increases with time,
Angular velocity change amount direction determining means for determining the direction of the angular velocity change amount (Δω);
Counter means for determining, based on the output of the angular velocity change amount direction determining means, whether or not the angular velocity change amount (Δω) remains in the same direction for a predetermined number of times or for a predetermined time;
When the counter means obtains an output indicating that the angular velocity change amount (Δω) remains in the same direction a predetermined number of times or for a predetermined time, the phase bias value (+ α) in the first direction and the first Mode switching means for supplying the tilting phase bias value (Δθ ₂ ) to the adding means instead of the phase bias value (Δθ ₁ ) composed of the phase bias value (−α) in the direction of 2;
The inverter device according to claim 1, comprising:   3. The inverter device according to claim 2, wherein the tilt phase bias value generating means comprises means for amplifying the angular velocity change amount (Δω) with a predetermined gain (K).   Further, the power from the inverter device to the load is obtained in response to a signal indicating that power is supplied from the inverter device without power supply from the AC power system obtained from the isolated operation detecting means. 4. The inverter device according to claim 1, further comprising means for interrupting supply. The switch control means includes
Output current command value creating means (12, 13 or 12a);
Feedback control signal forming means for forming a feedback control signal based on the output current command value obtained from the output current command value creating means (12, 13 or 12a) and the current detection value obtained from the current detecting means ( 14)
Switch control pulse forming means (15) for forming a switch control pulse for on / off control of the DC-AC conversion switch based on the feedback control signal obtained from the feedback control signal forming means (14); Have
The current phase command signal (θi) obtained from the adding means is supplied to the feedback control signal forming means (14) or the output current command value creating means (12, 13 or 12a). The inverter device according to 1 or 2 or 3 or 4.

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