JP2007318656A - Radio communication apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To acquire a high-accuracy answer signal without noise when receiving an answer signal from a radio tag circuit element. <P>SOLUTION: In a radio communication apparatus, a reader/writer 1 includes: a PLL circuit 300 which comprises a VCO 305, a frequency divider-phase comparator 302 for comparing the phase of an oscillation output from the VCO with the phase of a reference signal from a reference oscillator 301, and a loop filter 304 for smoothing the output of the frequency divider-phase comparator, and executes PLL control for outputting a control voltage to the VCO 305 in accordance with the comparison result of the frequency divider-phase comparator 302; a variable amplifier 217 for modulating a carrier wave generated from the VCO 305; an antenna 3 for transmitting the carrier wave to a radio tag circuit element To and receiving an answer signal corresponding to transmission signal; and a switch 303 capable of stopping execution of PLL control by the PLL circuit 300 when the answer signal is received. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a wireless communication apparatus that performs wireless communication of information with the outside.

  RFID (Radio Frequency Identification) systems that read and write information on wireless tags by sending and receiving inquiries and receiving responses from a reader / writer as a wireless communication device to a small wireless tag are known. It has been.

  For example, a wireless tag circuit element included in a label-like wireless tag includes an IC circuit unit that stores predetermined wireless tag information and an antenna that is connected to the IC circuit unit and transmits / receives information. The IC circuit unit demodulates and interprets the signal received by the antenna, modulates and reflects the received carrier wave based on the information signal stored in the memory, and returns it to the reader / writer via the antenna.

  As such a wireless communication device, a device disclosed in, for example, Patent Document 1 is conventionally known. In this prior art, the carrier wave output from the VCO of the PLL circuit as an oscillator is modulated and transmitted from the antenna to the RFID tag circuit element to be communicated, and the response signal from the RFID tag circuit element corresponding to this is received by the antenna. By being demodulated, information transmission / reception is performed.

Japanese Patent Laying-Open No. 2005-122633 (paragraph number 0074, FIG. 16)

  In general, the VCO of a PLL circuit has a property that when the output intensity of an amplifier connected to the output side thereof changes, the output frequency of the VCO changes accordingly. Due to such disturbances, when amplitude modulation such as ASK modulation accompanied by change in output intensity is used during carrier wave modulation, the output frequency of the VCO during transmission from the antenna changes. Due to the change in the output frequency of the VCO, the phase comparison result of the phase comparator provided in the PLL circuit is changed by the PLL control. The control voltage changes in response to the deviation at the time of change, and the output frequency of the VCO is controlled to a predetermined frequency in accordance with this change. In this way, when returning to the occurrence of disturbance by PLL control, There is a risk of significant noise when receiving with the antenna. Even when the frequency is constant, there may be phase noise whose phase fluctuates, and in this case as well, there is a possibility of receiving noise. These phase noises are factors that limit the sensitivity at the time of obtaining the response signal.

  An object of the present invention is to provide a wireless communication apparatus capable of acquiring a highly accurate response signal without noise when receiving a response signal from a wireless tag circuit element.

  In order to achieve the above object, the first invention provides a VCO that oscillates at a frequency corresponding to an applied control voltage and generates a carrier wave for accessing a communication target, an oscillation output of the VCO, and a reference oscillator. PLL control including a phase comparator for phase comparison with a reference signal and a loop filter for smoothing the output of the phase comparator, and outputting the control voltage to the VCO according to the comparison result of the phase comparator A carrier wave modulation means for modulating the carrier wave generated from the VCO of the PLL circuit, and a transmission means for sending the carrier wave output from the carrier wave modulation means to the communication target. A receiving means for receiving a response signal from the communication object according to a transmission signal from the transmitting means, and at the time of receiving the response signal by the receiving means, the P And having a stop capable PLL stop control means execution of the PLL control by L circuit.

  In the first invention of this application, the carrier wave output from the VCO of the PLL circuit is modulated by the carrier wave modulation means, transmitted from the transmission means to the communication target, and a response signal from the communication target corresponding thereto is received by the reception means. Thus, information transmission / reception with the communication target is performed.

Here, generally, the VCO of the PLL circuit has a property that when the output intensity of the amplifier connected to the output side thereof changes, the output frequency of the VCO also changes accordingly. Due to such disturbance, when the carrier wave modulation means uses amplitude modulation such as ASK modulation with a change in output intensity, the output frequency of the VCO at the time of transmission from the transmission means changes. Due to the change of the output frequency of the VCO, the phase comparison result of the phase comparator is changed by the PLL control. The control voltage to the VCO changes corresponding to the deviation at the time of the change, and the output frequency of the VCO is controlled to a predetermined frequency in accordance with this change. In such a case, there is a risk that a large amount of noise will be generated particularly when receiving by the receiving means. Even when the output frequency of the VCO is constant, there may be phase noise in which the phase of the VCO output fluctuates, and in this case as well, there is a possibility of receiving noise.
Since these noises cause the reception sensitivity to be limited, in the first invention of this application, when the PLL stop control means receives the response signal by the receiving means, it stops the execution of the PLL control by the PLL circuit. As a result, a highly accurate response signal free from noise can be acquired.

  According to a second invention, in the first invention, the PLL stop control means is configured such that the PLL after the transmission signal is transmitted by the transmission means and before the response signal is received by the reception means corresponding to the transmission. The execution of the PLL control by the circuit is stopped.

  By stopping the PLL control before receiving the response signal, the time during which the PLL control is not performed can be shortened.

  According to a third invention, in the second invention described above, there is provided an amplitude reduction control means for reducing the amplitude of the transmission signal transmitted from the transmission means before the execution of the PLL control by the PLL stop control means is stopped. Features.

  When the execution of the PLL control is stopped, the VCO output tends to fluctuate greatly at that moment. Therefore, in the third invention of the present application, the fluctuation of the VCO output is stabilized from before the PLL control is stopped by the amplitude reduction control means. By reducing the transmission output, it is possible to reduce the influence on other communication used in the vicinity.

  In a fourth aspect based on the third aspect, the amplitude reduction control means includes a VCO output control means for reducing the amplitude of the previous carrier wave generated from the VCO.

  In the fourth invention of the present application, the amplitude of the VCO output can be changed as the amplitude reduction control means, so that the disturbance of the VCO output can be reduced and the influence on other communication used in the vicinity can be reduced. .

  According to a fifth invention, in any one of the first to fourth inventions, when the PLL stop control means stops the execution of the PLL control, the output frequency from the PLL circuit is out of a predetermined range. And a transmission stop control means for stopping transmission from the transmission means according to a detection result of the frequency detection means.

  When the PLL control for stabilizing the output frequency is stopped, the carrier frequency from the VCO from the PLL circuit gradually changes, and there is a possibility of deviating greatly from the original frequency as it is. Therefore, in the fifth invention of this application, the frequency detection means detects the output frequency of the PLL circuit, and the transmission stop control means stops the transmission from the transmission means according to the detection result. Thereby, as described above, it is possible to prevent the carrier frequency from deviating greatly from the beginning, for example, from deviating outside the legally stipulated range.

  A sixth invention is characterized in that, in the fifth invention, there is provided frequency range setting means for variably setting the predetermined range of the output frequency.

  As a result, the allowable range of the carrier frequency can be changed each time according to the operator's needs, geographical conditions, etc., so that convenience can be improved.

  In a sixth aspect based on the sixth aspect, the frequency range setting means sets the predetermined range of the output frequency according to a communication channel to be used.

  Since the allowable range of the output frequency can be changed every time the communication channel is changed, a plurality of communication channels can be handled.

  An eighth invention is the detection filter according to any one of the fifth to seventh inventions, wherein the frequency detection means has substantially the same configuration as the loop filter, and an output from the phase comparator is input. And a voltage comparison circuit for comparing the output voltage of the detection filter with a voltage corresponding to the predetermined range of the output frequency.

  By comparing in the voltage comparison circuit using the output voltage of the detection filter having substantially the same configuration as the loop filter, the VCO output fluctuation is detected by converting it to a voltage level, and whether or not the output frequency is within the allowable range. Can be detected.

  In a ninth aspect based on the eighth aspect, the voltage comparison circuit obtains an upper limit voltage and a lower limit voltage respectively corresponding to an upper limit and a lower limit of the predetermined range of the output frequency, and an output voltage of the detection filter. Each of the transmission stop control means stops transmission from the transmission means when the output voltage of the detection filter becomes larger than the upper limit voltage or smaller than the lower limit voltage. It is characterized by that.

  By performing voltage comparison using a limiter circuit, it is possible to accurately detect that the tolerance has been exceeded, and accordingly, transmission of the transmission means can be stopped with high accuracy.

  According to a tenth aspect of the present invention, in any one of the first to ninth aspects, the loop filter of the PLL circuit is connected in parallel to the VCO, and a discharge time constant thereof is equal to or longer than a reception time by the reception unit. It is characterized by having a capacitor set up like this.

  By setting the capacitor discharge time constant to be equal to or longer than the reception time, it is possible to suppress the band fluctuation amount at the time of reception.

  An eleventh invention is characterized in that, in any one of the first to tenth inventions, the carrier wave modulating means modulates the carrier wave by changing an amplitude of the carrier wave generated from the VCO.

  When the carrier modulation means performs amplitude modulation, a change in the output frequency of the VCO at the time of transmission from the transmission means may cause a large noise at the time of reception at the reception means. Sometimes, by stopping the PLL control, it is possible to obtain a highly accurate response signal without noise.

  In a twelfth aspect according to any one of the first to eleventh aspects, the PLL stop control means is a switch means for cutting off output transmission from the phase comparator of the PLL circuit to the loop filter. Features.

  As a result, when the response signal is received by the receiving means, the output transmission from the PLL circuit to the loop filter can be cut off, thereby reliably stopping the frequency control function by the PLL control and ensuring the generation of noise due to a sudden change in the VCO output frequency. Can be prevented.

  In a thirteenth aspect of the present invention, in any one of the first to twelfth aspects, modulation control means for stopping modulation by the carrier wave modulation means and outputting an unmodulated wave when the response signal is received by the reception means. It is characterized by.

  When an unmodulated wave is transmitted from the modulation control means at the time of reception of the response signal, the influence of noise generated on the transmission side is particularly large because the wraparound of the transmission signal with respect to the reception signal is large. However, by stopping the execution of the PLL control by the PLL circuit, it is possible to reliably acquire a highly accurate response signal without noise.

  According to a fourteenth aspect of the present invention, in any one of the first to thirteenth aspects, the transmission unit includes an IC circuit unit that stores information and an antenna that transmits and receives information as the communication target. The carrier wave for accessing the wireless tag circuit element is transmitted to the RFID circuit element, and the receiving means receives a response signal from the RFID circuit element.

  When the communication partner is a wireless tag circuit element, information is returned by reflected waves (especially with passive tags and semi-passive tags), and the influence of noise is particularly large because the level of the received signal is small. In the 14th invention, the PLL stop control means stops the execution of the PLL control by the PLL circuit, so that a highly accurate response signal free from noise can be obtained with certainty.

  In a fifteenth aspect based on the fourteenth aspect, after the execution of the access to the RFID circuit element, a determination is made as to whether or not the access to the IC circuit unit to the RFID circuit element is successful. The PLL stop control means when the determination means determines that the access has failed when accessing the RFID circuit element in a state where the PLL circuit is executing the PLL control. , Before the access retry, the execution of the PLL control by the PLL circuit is stopped.

  Since the PLL control is not always stopped from the normal time and the PLL control is stopped only when an access failure occurs, the time during which the PLL control is not performed can be shortened as much as possible.

  In a sixteenth aspect based on any one of the first to fifteenth aspects, the response signal received by the receiving means is demodulated using a branch of the carrier wave output from the PLL circuit as a local signal. It has a demodulating means.

  When homodyne detection is performed by the demodulating means, noise generated by a change in the VCO output affects both the local signal (LO) and the received signal (RO). At this time, the timing at which noise is added is shifted due to the path difference between the two signals, and the influence of noise becomes particularly large. However, in the 16th invention of the present application, the PLL stop control means stops execution of PLL control by the PLL circuit, It is possible to reliably acquire a highly accurate response signal without noise.

  According to the present invention, when receiving a response signal from the RFID circuit element, it is possible to acquire a highly accurate response signal without noise.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a system configuration diagram illustrating a wireless tag communication system including the wireless tag communication device of the present embodiment.

  In FIG. 1, the wireless tag communication system 100 includes at least one wireless tag T attached to (or bundled with) an object (article or the like) as described above, and wireless communication with the wireless tag T, respectively. It is comprised from the reader / writer 1 as a wireless tag information communication apparatus which detects the wireless tag information containing this tag ID.

  The wireless tag T has a wireless tag circuit element To including a tag-side antenna 151 and an IC circuit unit 150, and the wireless tag circuit element To is provided on a base material or the like not specifically shown ( The wireless tag circuit element To will be described in detail later).

  The reader / writer 1 has a main body control unit 2 and an antenna 3 (transmitting means, receiving means). The main body control unit 2 includes a CPU 4, a memory 6 including, for example, a RAM and a ROM, an operation unit (operation unit) 7 for inputting instructions and information from an operator, and a display unit 8 for displaying various information and messages. And an RF communication unit 9 that controls wireless communication with the wireless tag T via the antenna 3.

  FIG. 2 is a functional block diagram showing a schematic configuration of the CPU 4, the RF communication unit 9, and the antenna 3 in the reader / writer 1. In FIG. 2, the RF communication unit 9 of the reader / writer 1 accesses information (RFID tag information including a tag ID) of the IC circuit unit 150 of the RFID circuit element To via the antenna 3. Further, the CPU 4 of the reader / writer 1 processes a signal read from the IC circuit unit 150 of the RFID circuit element To and reads information, and at the same time, a response request command for accessing the IC circuit unit 150 of the RFID circuit element To. (Details will be described later).

  The RF communication unit 9 includes a transmission unit 212 that transmits a signal to the RFID circuit element To via the antenna 3, a reception unit 213 that receives a response wave from the RFID circuit element To received by the antenna 3, And a transmission / reception separator 214.

  The transmission unit 212 includes a PLL (Phase Locked Loop) circuit 300 that generates a signal of a predetermined frequency under the control of the CPU 4, and the PLL circuit 300 based on a signal supplied from the CPU 4 (in detail, from a VCO 305 described later). The generated carrier wave is modulated (in this example, amplitude modulation based on the “TX_ASK” signal from the CPU 4), and the modulated wave is amplified (in this example, the amplification factor is determined by the “TX_PWR” signal from the CPU 4). And a variable transmission amplifier 217 (carrier wave modulation means). The generated carrier wave uses, for example, a frequency in the UHF band, microwave band, or short wave band, and the output of the transmission amplifier 217 is transmitted to the antenna 3 via the transmission / reception separator 214 to be a RFID circuit. It is supplied to the IC circuit unit 150 of the element To. Note that the RFID tag information is not limited to the signal modulated as described above, but may be only a carrier wave.

  The receiving unit 213 multiplies the response wave from the RFID circuit element To received by the antenna 3 and the generated carrier wave and demodulates the received first multiplication circuit 218 (demodulation means), and the reception first A first band pass filter 219 for extracting only a signal of a necessary band from the output of the multiplier circuit 218, a reception first amplifier 221 that amplifies the output of the first band pass filter 219, and the reception first amplifier 221 The first limiter 220 that further amplifies the output and converts it into a digital signal, the response wave from the RFID tag circuit element To received by the antenna 3, and the phase shifter 227 after the generation, delay the phase by 90 °. A reception second multiplication circuit 222 (demodulation means) that multiplies and demodulates the carrier wave, and a signal in a necessary band is extracted from the output of the reception second multiplication circuit 222. The second bandpass filter 223, a reception second amplifier 225 that amplifies the output of the second bandpass filter 223, and a second limiter 224 that further amplifies the output of the reception second amplifier 225 and converts it into a digital signal. And. The signal “RXS-I” output from the first limiter 220 and the signal “RXS-Q” output from the second limiter 224 are input to the CPU 4 and processed.

  The outputs of the reception first amplifier 221 and the reception second amplifier 225 are also input to an RSSI (Received Signal Strength Indicator) circuit 226 as intensity detection means, and a signal “RSSI” indicating the intensity of these signals is input to the CPU 4. It is designed to be entered. In this way, in the reader / writer 1, the response wave from the RFID circuit element To is demodulated by homodyne detection (in this example, in particular, IQ orthogonal demodulation) in which the signal received by the antenna 3 is demodulated using the transmission carrier wave. Is done.

  FIG. 3 is a functional block diagram illustrating a detailed configuration of a main part of the transmission unit 212 illustrated in FIG. In FIG. 3, the PLL circuit 300 provided in the transmission unit 212 uses a reference oscillator 301 and a carrier wave for oscillating at a frequency corresponding to the applied control voltage and for accessing the RFID circuit element To that is a communication target. A generated VCO (Voltage Controlled Oscillator) 305, a frequency divider / phase comparator 302 for phase comparison between the oscillation output of the VCO 305 and the reference signal from the reference oscillator 301, and the frequency divider / phase comparator A loop filter 304 for smoothing the output of 302 and a switch 303 (switch means, PLL stop control means) capable of interrupting output transmission from the frequency divider / phase comparator 302 to the loop filter 304 are provided.

  The frequency divider / phase comparator 302 outputs a control voltage to the VCO 305 in accordance with the phase comparison result described above, whereby the PLL control by the entire PLL circuit 300 is executed.

  The switch 303 (PLL stop control means) is based on a control signal from the CPU 4 (see the flow of FIG. 8 described later), and a response signal from the RFID circuit element To corresponding to the transmission after transmission of the transmission signal by the antenna 3 Before the reception by the antenna 3, the execution of the PLL control by the PLL circuit 300 can be stopped. As a result, when the response signal is received from the RFID circuit element To by the antenna 3, execution of the PLL control by the PLL circuit 300 is stopped (details will be described later).

  The transmission unit 212 further includes a filter circuit 310 (detection filter) to which an output from the frequency divider / phase comparator 302 is input, and a filter circuit 310 having substantially the same configuration as the loop filter 304. The output voltage is a predetermined voltage range (upper limit voltage and lower limit) respectively corresponding to a predetermined range (upper limit value and lower limit value) as an allowable range of the output frequency of the PLL circuit 300 (for example, to comply with the law). And the limiter circuits 331 and 330 (voltage comparison circuit) that respectively compare with the voltage) and the predetermined range (upper and lower limits) of the output frequency of the PLL circuit 300 in accordance with the control signal from the CPU 4. D / A converters 321 and 320 (frequency range setting means) for variably setting via 330, and limiter circuits 331 and 330 OR circuit 332 for taking a logical OR of the forces, and an AND circuit that takes the logical product of the output signal from this AND circuit 332 and the above-mentioned “TX_ASK” and “TX_PWR” signals from CPU 4 and outputs the result to variable transmission amplifier 217 333.

  With such a configuration, the filter circuit 310, the limiter circuits 331 and 330, and the OR circuit 332 detect that the output frequency from the PLL circuit 300 is out of a predetermined range (frequency detection means). The AND circuit 333 stops transmission from the antenna 3 (sets PA ON / OFF to 0 (Low)) when the output voltage of the filter circuit 310 becomes larger than the upper limit voltage or smaller than the lower limit voltage. (Transmission stop control means).

  FIG. 4 is a circuit diagram illustrating an example of a specific configuration of the loop filter 304. In FIG. 4, in this example, the loop filter 304 includes capacitors C <b> 1 and C <b> 2 connected in parallel to the VCO 305. The capacitors C1 and C2 are set so that the discharge time constant is equal to or longer than the reception time by the antenna 3. This time constant will be described below.

  In general, a discharge time constant τ is used as a constant indicating the length of time required for discharge. For a simple circuit made only of capacitors of capacitance C (capacitors C1, C2 in the example of FIG. 4) and resistors of resistance R (resistors R1, R2, R3 in the example of FIG. 4), the discharge time constant τ is set as the capacitance. As shown in FIG. 5, it is known that this value is a time that is 0.37 times the voltage at the start of discharge. In the present embodiment, by configuring as shown in FIG. 4, when the switch 303 is cut off, the discharge time constant of the circuit formed by the loop filter 304 and the VCO 305 is lengthened. It is possible to make it difficult to happen.

  FIG. 6 is a circuit diagram showing an equivalent circuit when the switch 303 is cut off in the configuration of FIG. When the output of the frequency divider / phase comparator 302 is cut off and turned off, power supply to the circuit constituted by the loop filter 304 and the VCO 305 is lost. As a result, the charges charged in the capacitors C1 and C2 of the loop filter 304 are consumed and discharged by the resistors R2 and R3 in the loop filter and the input terminal resistor R0 of the VCO 305. Therefore, by making the resistance values of the resistors R2 and R3 relatively small and the capacitances of the capacitors C1 and C2 relatively large, the discharge time constant is increased and the discharge time is known in advance (or assumed). The loop filter 304 can be designed so as to be longer than the reception time of the antenna 3.

  FIG. 7 is a block diagram showing an example of a functional configuration of the RFID circuit element To provided in the RFID tag T.

  In FIG. 7, the RFID circuit element To transmits and receives signals in a non-contact manner using the antenna 3 on the reader / writer 1 side and a high frequency such as a short wave band (eg, 13.56 MHz), UHF band, and microwave band. A tag-side antenna 151 and the IC circuit unit 150 connected to the tag-side antenna 151 are provided.

  The IC circuit unit 150 includes a rectifying unit 152 that rectifies the carrier wave received by the tag-side antenna 151, a power source unit 153 that accumulates energy of the carrier wave rectified by the rectifying unit 152, and serves as a driving power source. A clock extraction unit 154 that extracts a clock signal from a carrier wave received by the side antenna 151 and supplies the clock signal to the control unit 157, and a memory that functions as an information storage unit that can store a predetermined information signal such as a tag ID of the wireless tag T Unit 155, a modulation / demodulation unit 156 that is connected to the tag-side antenna 151 and modulates and demodulates signals, the rectification unit 152, the clock extraction unit 154, the modulation / demodulation unit 156, etc. And a control unit 157 for controlling the operation.

  The modem 156 demodulates the communication signal received from the antenna 3 of the reader / writer 1 received by the tag antenna 151 and modulates the carrier wave received by the antenna 151 based on the return signal from the controller 157. Then, it is retransmitted as a reflected wave from the antenna 151.

  The control unit 157 performs control for storing the predetermined information in the memory unit 155 by communicating with the reader / writer 1, and transmits the interrogation wave (response request command) received by the tag-side antenna 151 to the modulation / demodulation unit. In 156, basic control such as control for returning a response wave from the tag-side antenna 151 by performing a response wave (response signal) after modulation based on the information signal stored in the memory unit 155 is executed.

  The clock extraction unit 154 extracts a clock component from the received signal and extracts the clock to the control unit 157, and supplies a clock corresponding to the speed of the clock component of the received signal to the control unit 157.

  FIG. 8 is a flowchart showing an example of a control procedure executed by the CPU 4.

  In FIG. 8, first, in step S199, a counter N indicating the number of communication attempts is set to zero.

Next, in step S200, a “Scroll ALL ID” command (or a hierarchical search for a response) that is an unconditional tag information acquisition command that reads information stored in the RFID circuit element To in a manner that follows predetermined communication parameters and the like. A “Ping” command for processing may be output to the variable transmission amplifier 217 via the AND circuit 333 (output in the form of “TX_ASK” and “TX_PWR” signals). Based on this, a “Scroll ALL ID” signal (or “Ping” signal) as access information is generated by the variable transmission amplifier 217 and transmitted to the RFID circuit element To to be accessed via the antenna 3 to prompt a reply.

  Next, the process proceeds to step S210, where a control signal is output to the switch 303 of the PLL circuit 300, and the circuit is turned off (OFF). As a result, the output voltage from the frequency divider / phase comparator 302 to the loop filter 304 is cut off, and the PLL control in the PLL circuit 300 is turned off. As a result, the charge charged in the loop filter 304 is discharged to the VCO 305.

  At this time, the output frequency of the VCO 305 is obtained when the pulse signal indicating the difference from the phase of the reference oscillator 301 is input to the filter circuit 310 by the frequency divider / phase comparator 302 and the output voltage is within the predetermined range. The output of the OR circuit 332 becomes 1 (High) based on the result of the comparison circuits 330 and 331, and the “TX_ASK” and “TX_PWR” signals from the CPU 4 are selected from the AND circuit 333 and output to the variable transmission amplifier 217 for modulation. Is continued. On the other hand, when the output voltage deviates from the predetermined range, the output of the OR circuit 332 becomes 0 based on the results of the comparison circuits 330 and 331, so the output from the AND circuit 333 to the variable transmission amplifier 217 also becomes 0. The transmission output from the variable transmission amplifier 217 is stopped.

  Next, in step S230, the above-described “TX_ASK” signal is turned on for a certain time and output to the variable transmission amplifier 217. In this way, the modulation by the variable transmission amplifier 217 is stopped (= modulation control means), and an unmodulated wave is output and transmitted via the antenna 3, so that the wireless to be accessed corresponds to the “Scroll ALL ID” signal. A reply signal (including wireless tag information such as tag ID) transmitted from the tag circuit element To is received via the antenna 3 and taken in via the receiving unit 213.

  Next, in step S231, a control signal is output to the switch 303 of the PLL circuit 300 for the next communication to be turned on (ON).

  Next, in step S240, it is determined whether there is no error in the reply signal received in step S230 using, for example, a known error detection code (CRC code; Cyclic Redundancy Check, etc.) (determination means).

  If the determination is not satisfied, the process moves to step S250, and 1 is added to N. Further, in step S260, N is a predetermined number of retries set in advance (in this example, 5 times. Other times may be set as appropriate). It is determined whether or not. If N ≦ 4, the determination is not satisfied and the routine returns to step S200 and the same procedure is repeated. If N = 5, the process proceeds to step S270, where an error display signal is output to, for example, a display unit of the reader / writer 1 (not shown) to cause reading failure (error) display, and this flow is terminated. In this way, even if reading is unsuccessful, retry is performed up to a predetermined number of times (in this example, 5 times).

  When the determination in step S240 is satisfied, the reading of the RFID tag information from the RFID circuit element To to be read is completed, and this flow ends. By the above procedure, the RFID tag information of the IC circuit unit 151 can be accessed and read from the RFID tag circuit element To to be accessed.

  As described above, in the reader / writer 1 of the present embodiment, the carrier wave output from the VCO 305 of the PLL circuit 300 is modulated by the variable amplification amplifier 217 and transmitted from the antenna 3 to the RFID circuit element To. When the response signal from the RFID circuit element To is received by the antenna 3, information transmission / reception with the RFID circuit element To is performed.

  Here, in general, the VCO 305 of the PLL circuit 300 has a property that when the output intensity of the amplifier connected to the output side thereof changes, the output frequency of the VCO 305 temporarily changes accordingly. Due to such disturbance, when the variable amplification amplifier 217 performs amplitude modulation such as ASK modulation with a change in output intensity, the output frequency of the VCO 305 during transmission from the antenna 3 changes. Due to the change in the output frequency of the VCO 305, the phase comparison result of the frequency divider / phase comparator 302 is changed by PLL control. The control voltage changes in accordance with the deviation at the time of change, and the output frequency of the VCO 305 is controlled to a predetermined frequency in accordance with this change. In this way, when returning to the occurrence of disturbance by PLL control, There is a risk of large noise during demodulation at the receiving unit 213 (particularly when amplitude modulation is performed like the variable amplifier 217, and when an unmodulated wave is transmitted during reception, the transmission signal The effect is even greater due to the increased wraparound). Even when the frequency is constant, there may be phase noise whose phase fluctuates, and in this case as well, there is a possibility of receiving noise.

  In the present embodiment, when the response signal is received by the antenna 3, the phase noise is reduced by stopping the execution of the PLL control by the PLL circuit 300. A highly accurate response signal can be acquired. In particular, when the communication partner is the RFID circuit element To as in the present embodiment, the information is returned by the reflected wave as described above (particularly in the case of a passive tag or a semi-passive tag). Since the level is small, the influence of noise is particularly large, and the effect of obtaining a highly accurate response signal by stopping execution of the PLL control is great. Further, when demodulation is performed by homodyne detection as in the reception first multiplication circuit 218 and the reception second multiplication circuit 222 of the above embodiment, the noise generated by the change in the VCO output is a local signal (LO, see FIG. 3). And the received signal (RO, see FIG. 3). At this time, the timing at which the noise is added is shifted due to the path difference between the two signals, and the influence of the noise becomes particularly large. Therefore, as described above, the effect of obtaining a highly accurate response signal by stopping execution of the PLL control is great.

  In the present embodiment, in particular, by stopping the PLL control in step S210 before receiving the response signal from the RFID circuit element To, the time during which the PLL control is not performed can be shortened as much as possible.

  On the other hand, when the PLL control for stabilizing the output frequency is stopped as described above, the control signal input to the VCO 305 becomes the discharge output of the loop filter 304, so that the carrier frequency from the VCO 305 gradually changes. If it is as it is, there is a possibility of deviating greatly from the original frequency. Particularly in the present embodiment, as described with reference to FIGS. 4 to 6, by setting the discharge time constants of the capacitors C <b> 1 and C <b> 2 to be equal to or longer than the reception time, it is possible to suppress the band fluctuation amount during reception.

  In the present embodiment, in particular, the PLL circuit is configured by converting the fluctuation of the output of the VCO 305 into a voltage level by performing comparison in the voltage comparison circuits 330 and 331 using the output voltage of the filter circuit 310 having substantially the same configuration as the loop filter 304. The output frequency of the circuit 300 is detected, and transmission from the antenna 3 is stopped according to the detection result (particularly, it is accurately detected that the voltage is out of the allowable range by performing voltage comparison using the limiter circuits 330 and 331). And transmission can be stopped accurately according to this.) As a result, it is possible to prevent the carrier frequency from deviating greatly as described above, for example, from deviating outside the legally stipulated range. In particular, at this time, the frequency setting range can be changed by the D / A converters 320 and 321 via the CPU 4 according to the needs of the operator, geographical conditions, etc., thereby improving convenience. be able to. Further, the frequency range may be automatically set by the D / A converters 320 and 321 according to the communication channel to be used. In this case, the permissible range of the output frequency can be changed every time the communication channel is changed, so that a plurality of communication channels can be handled.

  The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and technical idea of the present invention. Hereinafter, such modifications will be described.

(1) When PLL control is turned off only when communication is retried. That is, as in the above embodiment, after transmission is completed, PLL control is not turned off at the time of reception, but PLL control is turned on for the first time. May be transmitted and received, and the PLL control may be turned OFF only at the time of communication retry (retry).

  FIG. 9 is a flowchart showing a control procedure executed by the CPU 4 in this modification, and corresponds to FIG. 8 in the above embodiment. The same steps as those in FIG. 8 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  In FIG. 9, in this modified example, when step S200 is completed, it is determined in step S211 whether N is 0 (whether the communication performed in S200 is the first trial). If the determination in S211 is not satisfied, the PLL control is turned OFF in S212 and the process proceeds to the steps after S230. However, if the determination in S211 is satisfied, the state of the switch 303 remains ON and the process proceeds to S230. . As a result, after the transmission in step S200 is completed, reception is performed in step S230 for the first time with the PLL control turned on. Only when the determination in step S240 is not satisfied and communication retry (retry) is performed, in step S212. Control is performed so as to turn off the PLL control by turning off the switch 303.

  Also in this modification, the effect similar to the said embodiment is acquired. In addition, the PLL control is not always stopped from the normal time, and the PLL control is stopped only when a communication (access) failure occurs, so that the time during which the PLL control is not performed can be shortened as much as possible.

(2) When the comparison circuit is not used In the above embodiment and the modified example of (1), the output frequency of the VCO 305 is detected using the comparison circuits 330 and 331, and the transmission from the antenna 3 is performed by the AND circuits 332 and 333. Although the stop control is performed, the present invention is not limited to this, and other methods may be used.

  FIG. 10 is a functional block diagram showing a detailed configuration of the main part of the transmission unit 212A provided in the RF communication unit 9 of such a modification, and corresponds to FIG. 3 described above. Components equivalent to those in FIG. 3 are denoted by the same reference numerals, and description thereof is omitted or simplified as appropriate.

  In FIG. 10, in the transmission unit 212 </ b> A of this modification, the output of the filter circuit 310 is digitized by the A / D converter 322 and then input to the CPU 4. Based on this input signal, the CPU 4 detects and determines whether or not the output frequency of the VCO 305 is within the above-mentioned predetermined range, and outputs a switching signal for turning ON / OFF the variable amplifier 217 to the AND circuit 333 accordingly. (Refer to FIG. 11 described later for details). At this time, the “TX_ASK” and “TX_PWR” signals from the CPU 4 are also input to the AND circuit 333, and the AND circuit 333 calculates the logical product of these two signals and outputs the logical product to the variable transmission amplifier 217. It has become.

  FIG. 11 is a flowchart showing an example of a control procedure executed by the CPU 4 of this modification, and corresponds to FIG. 8 described above. The same steps as those in FIG. 8 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  In FIG. 11, in this flow, step S220 is newly provided between step S210 and step S230 similar to FIG. In step S220, as described above, the fluctuation of the VCO output is output as a voltage level in the filter circuit 310, and the output frequency of the VCO 305 is set within the predetermined range based on the signal converted into the digital signal by the A / D converter 322. It is determined whether it is within. If it is within the predetermined range, the determination is satisfied, and the process proceeds to step S230. On the other hand, when the output frequency deviates from the predetermined range, the determination is not satisfied (= frequency detection means), and the process proceeds to newly provided step S280.

  In step S280, a control signal for turning OFF (stops transmission) the variable amplifier 217 is output to the AND circuit 333 (= transmission stop control means). As a result, regardless of what TX_PWR signal / TX_ASK signal is input from the CPU 4, the AND circuit 333 selects the transmission stop control signal in step S 280, and inputs it to the variable amplification amplifier 217. Transmission is stopped. When step S280 is completed, this flow ends.

  Also by this modification, the effect similar to the said embodiment is acquired.

  Further, in this modified example, the PLL control may be stopped only at the time of retry as in the modified example (1). FIG. 12 is a flowchart showing the control procedure in this case. In the flow of FIG. 11, steps S211 and S212 similar to those of the modified example (1) are provided. In this case, as in the modified example (1), there is an effect that the time during which the PLL control is not performed can be shortened as much as possible.

(3) When the switch means is not used In the above embodiment and the modified examples of (1) and (2), output transmission from the frequency divider / phase comparator 302 to the loop filter 304 can be cut off as the PLL stop control means. Although the switch 303 is provided, the present invention is not limited to this, and other means may be used.

  FIG. 13 is a functional block diagram illustrating a detailed configuration of a main part of the transmission unit 212B provided in the RF communication unit 9 of such a modification, and corresponds to FIG. 3 and FIG. Components equivalent to those in FIG. 3 and the like are denoted by the same reference numerals, and description thereof is omitted or simplified as appropriate.

  In FIG. 13, in the transmission unit 212B of this modification, the switch 303 and the filter circuit 310 are omitted, and the output from the frequency divider / phase comparator 302 is input to the limiter circuits 330 and 313, and the output voltage is And a predetermined voltage range (upper limit voltage and lower limit voltage) respectively corresponding to a predetermined range (upper limit value and lower limit value) as an allowable range of the output frequency of the PLL circuit 300 (for example, in compliance with laws and regulations) Each is compared. In the OR circuit 332, the logical sum of the outputs of the limiter circuits 331 and 330 is taken as described above, and the AND circuit 333 further outputs the “TX_ASK” and “TX_PWR” signals from the CPU 4 and the output signal from the AND circuit 332. And is output to the variable transmission amplifier 217.

  Further, a control signal (PLLON / OFF switching control signal) for directly controlling ON / OFF of the PLL control is output from the CPU 4 to the frequency divider / phase comparator 302 (a diagram to be described later). 14 step S210A).

  FIG. 14 is a flowchart showing an example of a control procedure executed by the CPU 4 of this modification, and corresponds to FIG. 8 of the above embodiment. The same steps as those in FIG. 8 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  In FIG. 14, in this flow, step S210A is newly provided instead of step S210 in FIG. In step S210A, as described above, a control signal (PLLOFF switching control signal) for turning off the PLL control is output to the frequency divider / phase comparator 302 (= PLL stop control means). As a result, the frequency divider / phase comparator 302 is stopped (paused), and the output terminal from the frequency divider / phase comparator 302 to the loop filter 304 is in a high impedance state. As a result, it is possible to obtain the same effect as when the switch 303 provided between the frequency divider / phase comparator 302 and the loop filter 304 is cut off in the above embodiment.

  In this case, assuming that the output from the loop filter 304 (the voltage at the control terminal of the VCO 305) is substantially proportional to the output frequency of the VCO 305, the output voltage of the loop filter 304 is directly input to the limiter circuits 331 and 330 as described above. . In the limiter circuits 331 and 330, a predetermined range (an upper limit value and a lower limit value) that is set in advance as an allowable range of the output voltage of the loop filter 304 and the output frequency of the PLL circuit 300 (for example, in compliance with laws and regulations). Each of the predetermined voltage ranges (upper limit voltage and lower limit voltage) respectively corresponding to (value) is compared. The subsequent functions of the OR circuit 332 and the AND circuit 333 are as described above.

  When step S210A ends, the process of step S230 similar to FIG. 8 is performed, and then the process proceeds to step S231A provided instead of step S231. In S231A, a control signal for turning on the PLL control is output to the frequency divider / phase comparator 302. As a result, the frequency divider / phase comparator 302 is activated, and the output frequency of the VCO 305 is controlled to be a predetermined value. Since the subsequent steps are the same as those in FIG.

  Also by this modification, the same effect as the above-mentioned embodiment is acquired. In this modification, the PLL control may be stopped only at the time of retry, as in the modification (1) above.

(4) In the case of directly observing the PLL control signal In the modified example of (2) above, the switch 303 is used, the output of the filter circuit 310 is A / D converted and input to the CPU 4 to detect the frequency. Although omitted, a signal that does not pass through the filter circuit can also be input to the CPU 4.

  FIG. 15 is a functional block diagram showing a detailed configuration of the main part of the transmission unit 212C provided in the RF communication unit 9 of such a modification, and corresponds to FIG. 3, FIG. 10, FIG. Parts equivalent to those in FIG. 3 and the like are denoted by the same reference numerals, and description thereof will be omitted or simplified as appropriate.

  In FIG. 15, in the transmission unit 212 </ b> C of this modified example, the output from the frequency divider / phase comparator 302 is converted into a pull-up circuit 341 including a diode 344 and a resistor 340, a pull-down circuit 342 including a diode 345 and a resistor 342. To introduce. That is, at the output terminal of the frequency divider / phase comparator 302, the divided signal of the high frequency signal is compared with the divided signal of the reference frequency signal from the reference oscillator 301, and when the phase of the high frequency signal is delayed, “High” output, “Low” output when the phase is advanced, and “Z” when there is no phase difference. Therefore, the signal (P1) obtained by pulling up the output signal from the frequency divider / phase comparator 302 by the pull-up circuit 341 and the signal (P2) pulled down by the pull-down circuit 343 are input to the CPU 4 and shown in FIG. As described above, the CPU 4 can detect the logical product (AND) of the P1 signal and the P2 signal to detect the high pulse width, and the negative logical sum (NOR) to detect the low pulse width. Therefore, the phase shift with respect to the reference frequency signal from the reference oscillator 301 can be calculated from these two calculation results, and the output frequency of the VCO 305 can be detected based on this result. Then, when the pulse width generated as a result of the AND calculation or the NOR calculation becomes a certain value or more, it is detected and determined that the output frequency has deviated from the predetermined range, and the variable amplification amplifier 217 is turned off ( Stop transmission).

  The control procedure executed by the CPU 4 of this modification is the same as that in the flow of FIG. 11 used in the modification of (2). That is, in step S220, as described above, the logical product (AND) or negative logical sum (NOR) of the P1 and P2 signals in the CPU 4 is calculated to detect the width of the High or Low pulse, and the detection is based on these. It is determined whether the output frequency of the VCO 305 is within the predetermined range. If it is within the predetermined range, the determination is satisfied, and the routine goes to step S230 and thereafter. If the output frequency deviates from the predetermined range, the determination is not satisfied (= frequency detection means), the process proceeds to step S280, and the variable amplification amplifier 217 is turned off (stops transmission) with respect to the AND circuit 333. The control signal is output (= transmission stop control means). As a result, regardless of what TX_PWR signal / TX_ASK signal is input from the CPU 4, it is input to the variable amplification amplifier 217 and transmission from the antenna 3 is stopped.

  Also by this modification, the effect similar to the said embodiment is acquired.

(5) When amplitude control is performed in cooperation with PLL stop control When the execution of PLL control is stopped, the VCO output tends to fluctuate greatly at that moment. Therefore, before the PLL control is stopped by the amplitude reduction control means as described above. By reducing the carrier wave output, the influence on others can be reduced.

  That is, the amplitude (signal strength) of the transmission signal is reduced by, for example, reducing the gain of the variable amplifier 217 before stopping the PLL control by the PLL stop control means such as the step S210A executed by the switch 303 or the CPU 4. Amplitude reduction control means for reducing the size is provided. In this case, for example, variable amplification is performed between step S200 and step S210 in FIGS. 8 and 11, between step S200 and step S210A in FIG. 14, and between step S260 and step S290 in FIGS. A procedure for outputting an amplitude reduction control signal to the amplifier 217 may be provided (amplitude reduction control means).

  Further, the amplitude of the carrier wave generated from the VCO 305 may be reduced (for example, minimized) in advance as amplitude reduction control means. When the VCO 305 has an output control terminal, a procedure for outputting an amplitude reduction control signal similar to the above control to the terminal may be provided (VCO output control means).

  If the amplitude of the carrier wave is reduced as described above, the supply of electric energy to the RFID circuit element To may stop, the operation may stop, and there may be no response. In order to avoid this, the amplitude is restored immediately after the amplitude is decreased and the PLL control is stopped, or the period during which the PLL control is stopped is set to a very short period so that the operation of the RFID circuit element is not stopped ( For example, the PLL control may be stopped only in the “EOF” section indicating the end of the command indicated by the standard in EPC global).

  Further, a sample hold circuit can be preferably used as the PLL stop control means.

  It is assumed that the “Scroll ALL ID” signal and the like used above conform to the specifications established by EPC global. EPC global is a non-profit corporation established jointly by the International EAN Association, which is an international organization of distribution codes, and the United Code Code Council (UCC), which is an American distribution code organization. Note that signals conforming to other standards may be used as long as they perform the same function.

  In addition to those already described above, the methods according to the above-described embodiments and modifications may be used in appropriate combination.

  In addition, although not illustrated one by one, the present invention is implemented with various modifications within a range not departing from the gist thereof.

1 is a system configuration diagram illustrating a wireless tag communication system including a wireless tag communication device according to an embodiment of the present invention. It is a functional block diagram showing schematic structure of CPU, RF communication part, and an antenna in a reader / writer. It is a functional block diagram showing the principal part detailed structure of the transmission part shown in FIG. It is a circuit diagram showing an example of a specific configuration of a loop filter. It is a graph showing a discharge curve. FIG. 5 is a circuit diagram showing an equivalent circuit when a switch is cut off in the configuration of FIG. 4. It is a block diagram showing an example of a functional structure of the radio | wireless tag circuit element with which the radio | wireless tag was equipped. It is a flowchart showing an example of the control procedure which CPU performs. It is a flowchart showing the control procedure which CPU performs in the modification which turns off PLL control only at the time of communication retry. It is a functional block diagram showing the principal part detailed structure of the transmission part with which RF communication part of the modification which does not use a comparison circuit was equipped. It is a flowchart showing an example of the control procedure which CPU performs. It is a flowchart showing the control procedure in the case of stopping PLL control only at the time of retry. It is a functional block diagram showing the principal part detailed structure of the transmission part with which RF communication part of the modification which does not use a switch means was equipped. It is a flowchart showing an example of the control procedure which CPU performs. It is a functional block diagram showing the principal part detailed structure of the transmission part with which the RF communication part of the modification which uses neither a comparison circuit nor a filter circuit was equipped. It is a figure showing a logical operation when detecting a pulse width based on the output signal from a frequency divider and a phase comparator.

Explanation of symbols

1 Reader / Writer (wireless communication device)
3 Antenna (transmitting means, receiving means)
217 Variable amplification amplifier (carrier modulation means)
300 PLL circuit 302 Frequency divider / phase comparator (phase comparator)
303 switch (switch means, PLL stop control means)
304 Loop filter 305 VCO
310 Filter circuit (detection filter, frequency detection means)
320,321 D / A converter (frequency range setting means)
330,331 Limiter circuit (voltage comparison circuit, frequency detection means)
332 AND circuit (frequency detection means)
333 AND circuit (transmission stop control means)
C1, C2 capacitors

Claims (16)

A VCO that oscillates at a frequency corresponding to an applied control voltage and generates a carrier wave for accessing a communication target, a phase comparator that compares the phase of the oscillation output of the VCO and a reference signal from the reference oscillator, and the phase A loop filter that smoothes the output of the comparator, and a PLL circuit that executes PLL control for outputting the control voltage to the VCO according to the comparison result of the phase comparator;
Carrier modulation means for modulating the carrier generated from the VCO of the PLL circuit;
Transmitting means for transmitting the carrier wave output from the carrier wave modulating means to the communication target;
Receiving means for receiving a response signal from the communication object according to the transmission signal from the transmitting means;
A wireless communication apparatus comprising: a PLL stop control unit capable of stopping execution of the PLL control by the PLL circuit when the response signal is received by the receiving unit. The wireless communication device according to claim 1, wherein
The PLL stop control means includes:
The wireless communication device, wherein after the transmission signal is transmitted by the transmission unit, the PLL control by the PLL circuit is stopped before the reception signal corresponding to the transmission is received by the reception unit. The wireless communication device according to claim 2, wherein
A radio communication apparatus comprising amplitude reduction control means for reducing the amplitude of the transmission signal transmitted from the transmission means before stopping execution of the PLL control by the PLL stop control means. The wireless communication device according to claim 3, wherein
The radio communication apparatus according to claim 1, wherein the amplitude reduction control means is VCO output control means for reducing the amplitude of the carrier wave generated from the VCO. The wireless communication device according to any one of claims 1 to 4,
Frequency detection means for detecting that the output frequency from the PLL circuit is out of a predetermined range when the PLL stop control means stops execution of the PLL control;
A radio communication apparatus comprising: a transmission stop control unit that stops transmission from the transmission unit according to a detection result of the frequency detection unit. The wireless communication device according to claim 5, wherein
A radio communication apparatus comprising frequency range setting means for variably setting the predetermined range of the output frequency. The wireless communication device according to claim 6, wherein
The frequency range setting means includes
The wireless communication apparatus, wherein the predetermined range of the output frequency is set according to a communication channel to be used. The wireless communication device according to any one of claims 5 to 7,
The frequency detection means includes
A detection filter having substantially the same configuration as the loop filter, to which an output from the phase comparator is input,
A wireless communication apparatus comprising: a voltage comparison circuit that compares an output voltage of the detection filter with a voltage corresponding to the predetermined range of the output frequency. The wireless communication apparatus according to claim 8, wherein
The voltage comparison circuit includes:
A limiter circuit for comparing an upper limit voltage and a lower limit voltage respectively corresponding to an upper limit and a lower limit of the predetermined range of the output frequency, and an output voltage of the detection filter;
The transmission stop control means includes
The wireless communication apparatus, wherein when the output voltage of the detection filter becomes larger than the upper limit voltage or smaller than the lower limit voltage, the transmission from the transmission means is stopped. The wireless communication apparatus according to any one of claims 1 to 9,
The loop filter of the PLL circuit is:
A wireless communication apparatus comprising: a capacitor connected in parallel to the VCO and having a discharge time constant set to be equal to or longer than a reception time by the receiving means. The wireless communication apparatus according to any one of claims 1 to 10,
The carrier wave modulation means includes
A radio communication apparatus that performs modulation by changing an amplitude of the carrier wave generated from the VCO. The wireless communication device according to any one of claims 1 to 11,
The PLL stop control means includes:
A wireless communication apparatus, characterized in that the wireless communication apparatus is switch means for blocking output transmission from the phase comparator of the PLL circuit to the loop filter. The wireless communication apparatus according to any one of claims 1 to 12,
A radio communication apparatus comprising modulation control means for stopping modulation by the carrier wave modulation means and outputting an unmodulated wave when the response signal is received by the reception means. The wireless communication device according to any one of claims 1 to 13,
The transmission means transmits the carrier wave for accessing a wireless tag circuit element including an IC circuit unit that stores information and an antenna that transmits and receives information as the communication target, to the wireless tag circuit element,
The wireless communication apparatus, wherein the receiving means receives a response signal from the RFID circuit element. The wireless communication device according to claim 14, wherein
A determination means for determining whether or not the access to the IC circuit unit to the RFID circuit element is successful after the access to the RFID circuit element;
The PLL stop control means includes:
When access to the RFID circuit element is performed in a state in which the PLL circuit is performing the PLL control, if the access is determined to be unsuccessful by the determination means, the access is performed by the PLL circuit before the access is retried. A wireless communication apparatus, wherein execution of the PLL control is stopped. The wireless communication device according to any one of claims 1 to 15,
A radio communication apparatus comprising demodulating means for demodulating the response signal received by the receiving means using a signal obtained by branching the carrier wave outputted from the PLL circuit as a local signal.

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