JP2007317808A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

Info

Publication number
JP2007317808A
JP2007317808A JP2006144733A JP2006144733A JP2007317808A JP 2007317808 A JP2007317808 A JP 2007317808A JP 2006144733 A JP2006144733 A JP 2006144733A JP 2006144733 A JP2006144733 A JP 2006144733A JP 2007317808 A JP2007317808 A JP 2007317808A
Authority
JP
Japan
Prior art keywords
electrodes
circuit board
semiconductor device
electrode
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006144733A
Other languages
Japanese (ja)
Inventor
Shigeru Nonoyama
茂 野々山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2006144733A priority Critical patent/JP2007317808A/en
Publication of JP2007317808A publication Critical patent/JP2007317808A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/85951—Forming additional members, e.g. for reinforcing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which ensures the number of electrodes corresponding to the number of electrodes on a semiconductor element on a circuit board which is highly functional while being reduced in a size, and to provide its manufacturing method. <P>SOLUTION: The semiconductor device has a semiconductor element 4, the circuit board 1 mounting the semiconductor element 4, and a metallic fine line 7 for electrically connecting a plurality of electrodes 6 formed on an upper face of the semiconductor element 4 to a plurality of electrodes 3 formed around the element mounting part 1a of the circuit board 1 corresponding to the plurality of electrodes 6 of the semiconductor element 4. In this case, a conductive projection 10 is formed on the plurality of electrodes 3 of the circuit board 1 so as to gradually increase in a level along a direction from the center of the element mounting part to an outer periphery. Accordingly, since a difference in the level between the metallic fine lines 7 and a possibility of bringing the metallic fine lines 7 into contact with each other, the electrode area of the circuit board 1 is reduced and its size is reduced, whereas the semiconductor device can be stably produced. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体素子を回路基板上に搭載して金属細線で電気的に接続した半導体装置およびその製造方法に関するものである。   The present invention relates to a semiconductor device in which a semiconductor element is mounted on a circuit board and electrically connected with a thin metal wire, and a method for manufacturing the same.

半導体素子を回路基板上に搭載して金属細線で電気的に接続した半導体装置として、たとえばＢＧＡ（ボール・グリッド・アレイ）型半導体装置がある。
図６に従来の一般的なＢＧＡ型半導体装置の概略構成を示す。回路基板１は、ポリイミド樹脂等からなる有機基板、或いは窒化アルミニウム（ＡｌＮ）等からなるセラミック基板などを基材２とし、銅（Ｃｕ）等の金属により電極３を表面に形成するとともに裏面電極（図示せず）を形成し、表裏の電極間を接続する基板内金属配線（図示せず）を形成している。 As a semiconductor device in which a semiconductor element is mounted on a circuit board and electrically connected with a thin metal wire, for example, there is a BGA (ball grid array) type semiconductor device.
FIG. 6 shows a schematic configuration of a conventional general BGA type semiconductor device. The circuit board 1 includes an organic substrate made of polyimide resin or the like, or a ceramic substrate made of aluminum nitride (AlN) or the like as a base material 2, and an electrode 3 is formed on the surface with a metal such as copper (Cu) and a back electrode ( In-substrate metal wiring (not shown) for connecting the front and back electrodes is formed.

半導体素子４は回路基板１の表面の所定位置に接着剤５により接着しており、半導体素子４の電極６と回路基板１上の電極３とを金（Ａｕ）などの金属細線７により電気的に接続し、半導体素子４及び金属細線７を外部から保護するためにエポキシ樹脂等からなる封止樹脂８により回路基板１の表面を被覆している。また回路基板１の裏面電極上に外部基板との接続を行うための半田ボール等の突起電極９を形成している。   The semiconductor element 4 is bonded to a predetermined position on the surface of the circuit board 1 with an adhesive 5, and the electrode 6 of the semiconductor element 4 and the electrode 3 on the circuit board 1 are electrically connected by a metal thin wire 7 such as gold (Au). In order to protect the semiconductor element 4 and the fine metal wire 7 from the outside, the surface of the circuit board 1 is covered with a sealing resin 8 made of an epoxy resin or the like. Further, a protruding electrode 9 such as a solder ball for connecting to an external substrate is formed on the back electrode of the circuit board 1.

なおこの半導体装置では、半導体素子４の電極６の数が多いため、回路基板１上に形成する電極３を基板中央部から基板外周部に向かって複数列配列しており、半導体素子４上の電極６と回路基板１上の電極３とを接続する金属細線７は互いに接触しないようにそれぞれのループ高さを変えている（特許文献１）。
特開平５−１２９３５７号公報 In this semiconductor device, since the number of the electrodes 6 of the semiconductor element 4 is large, the electrodes 3 formed on the circuit board 1 are arranged in a plurality of rows from the center of the substrate toward the outer periphery of the substrate. The loop heights of the thin metal wires 7 connecting the electrodes 6 and the electrodes 3 on the circuit board 1 are changed so as not to contact each other (Patent Document 1).
JP-A-5-129357

しかしながら、拡散プロセスの微細化並びに半導体素子４の高機能化に伴って、半導体素子４上の電極６の数が飛躍的に増加してきているため、回路基板１上での電極３の配置が困難になり、回路基板１のサイズを大きくせざるをえず、半導体装置のサイズが大きくなるという問題がある。   However, since the number of electrodes 6 on the semiconductor element 4 has increased dramatically with the miniaturization of the diffusion process and the higher functionality of the semiconductor element 4, it is difficult to arrange the electrodes 3 on the circuit board 1. Therefore, the size of the circuit board 1 must be increased, and there is a problem that the size of the semiconductor device increases.

回路基板１のサイズの拡大を抑えつつ多数の電極３を配置しようとすると、電極３，３間の距離が近くなるだけでなく、上述したように金属細線７のループ高さを変えても高低差が小さくなり、金属細線７どうしが接触する恐れがある。電極３，３間の距離を確保するためには電極３幅を小さくすることが考えられるが、金属細線７との接合性が低下する懸念がある。   If an attempt is made to arrange a large number of electrodes 3 while suppressing an increase in the size of the circuit board 1, not only the distance between the electrodes 3 and 3 is reduced, but also the height of the metal thin wire 7 can be changed by changing the loop height as described above. The difference becomes small, and there is a possibility that the fine metal wires 7 come into contact with each other. In order to secure the distance between the electrodes 3 and 3, it is conceivable to reduce the width of the electrode 3, but there is a concern that the bondability with the thin metal wire 7 may be reduced.

本発明は、上記問題に鑑み、半導体素子上の電極数に対応する電極数を回路基板に確保しながらも小型化された半導体装置およびその製造方法を提供することを目的とするものである。   In view of the above problems, an object of the present invention is to provide a semiconductor device that is reduced in size while ensuring the number of electrodes corresponding to the number of electrodes on a semiconductor element on a circuit board, and a manufacturing method thereof.

上記課題を解決するために、本発明の半導体装置は、半導体素子と、前記半導体素子を搭載した回路基板と、前記半導体素子の上面に形成された複数の電極と前記半導体素子の複数の電極に対応して前記回路基板の素子搭載部の周囲に形成された複数の電極とを電気的に接続した金属細線とを有した半導体装置において、前記回路基板の複数の電極上に、前記素子搭載部の中央から外周に向かう方向に沿って次第に高くなるように導電性突起物が形成されていることを特徴とする。   In order to solve the above problems, a semiconductor device of the present invention includes a semiconductor element, a circuit board on which the semiconductor element is mounted, a plurality of electrodes formed on an upper surface of the semiconductor element, and a plurality of electrodes of the semiconductor element. Correspondingly, in a semiconductor device having a thin metal wire electrically connected to a plurality of electrodes formed around an element mounting portion of the circuit board, the element mounting portion is disposed on the plurality of electrodes of the circuit board. Conductive protrusions are formed so as to gradually increase along the direction from the center to the outer periphery.

導電性突起物はさらに、回路基板の端辺の中央から両端のそれぞれに向かう方向に沿って次第に高くなるように形成されていることを特徴とする。また導電性突起物は、素子搭載部の中央から外周に向かう方向に沿って高くなる段差形状を有していることを特徴とする。   The conductive protrusion is further characterized by being formed so as to gradually become higher along the direction from the center of the edge of the circuit board toward each of both ends. Further, the conductive protrusion has a step shape that increases in a direction from the center of the element mounting portion toward the outer periphery.

本発明の半導体装置の製造方法は、半導体素子を回路基板上に搭載する工程と、前記半導体素子の上面に形成された複数の電極と前記半導体素子の複数の電極に対応して前記回路基板の素子搭載部の周囲に形成された複数の電極とをそれぞれ金属細線で電気的に接続する工程とを有して、上記の半導体装置を製造する際に、前記回路基板の複数の電極のそれぞれに金属細線を接続するに先立って、前記複数の電極上に所定の方向に沿って次第に高くなるように導電性突起物を形成し、この導電性突起物に対して金属細線を接続することを特徴とする。   The method of manufacturing a semiconductor device according to the present invention includes a step of mounting a semiconductor element on a circuit board, a plurality of electrodes formed on an upper surface of the semiconductor element, and a plurality of electrodes of the semiconductor element corresponding to the plurality of electrodes of the semiconductor element. Electrically connecting a plurality of electrodes formed around the element mounting portion with thin metal wires, respectively, and when manufacturing the semiconductor device, each of the plurality of electrodes on the circuit board Prior to connecting the thin metal wires, conductive protrusions are formed on the plurality of electrodes so as to gradually increase along a predetermined direction, and the thin metal wires are connected to the conductive protrusions. And

導電性突起物は、ワイヤボンド法を利用して金属ボールを所望高さまで積み重ねることにより形成することができる。
また導電性突起物は、めっき工法によって形成することができる。めっき工法によって導電性突起物を形成する際には、回路基板上に電極とその周囲を囲む前記電極よりも厚いソルダーレジストとを形成し、前記電極とその所定方向に隣接したソルダーレジストの一部とをマスク開口より露出させてめっきを施すことにより、前記電極上とソルダーレジスト上とにわたる段差形状の導電性突起物を形成するのが都合よい。 The conductive protrusions can be formed by stacking metal balls to a desired height using a wire bond method.
In addition, the conductive protrusion can be formed by a plating method. When forming conductive protrusions by a plating method, an electrode and a solder resist thicker than the electrode surrounding the electrode are formed on a circuit board, and a part of the solder resist adjacent to the electrode and its predetermined direction is formed. It is convenient to form a stepped conductive protrusion extending over the electrode and the solder resist by performing plating by exposing and from the mask opening.

本発明によれば、導電性突起物の存在により電極面に高低差が生じ、各電極に接続する金属細線の高低差が拡大するので、金属細線どうしが接触する恐れは低減され、信頼性を高めることができる。   According to the present invention, the height difference occurs on the electrode surface due to the presence of the conductive protrusions, and the height difference of the fine metal wires connected to each electrode increases. Therefore, the risk of contact between the fine metal wires is reduced, and reliability is improved. Can be increased.

したがって、電極間の距離を小さくしても、各電極に接続する金属細線の高低差を確保することが可能となり、金属細線どうしが接触する恐れは小さく、金属細線と導電性突起物との接合面積を確保することで、半導体装置の安定した生産が可能となる。   Therefore, even if the distance between the electrodes is reduced, it is possible to ensure a difference in height of the fine metal wires connected to each electrode, and there is little risk of contact between the fine metal wires, and the joining of the fine metal wires and the conductive protrusions By securing the area, the semiconductor device can be stably produced.

このことにより、回路基板上の電極数を減らすことなく電極領域を小さくして、したがって回路基板全体のサイズを小さくして、半導体装置を小型化することが可能となる。あるいは、回路基板上の電極数を多くしながらも電極領域を増やすことなく、したがって回路基板全体のサイズを変えることなく、電極数がより多い高機能の半導体素子を搭載することが可能になる。   As a result, it is possible to reduce the size of the semiconductor device by reducing the electrode area without reducing the number of electrodes on the circuit board and thus reducing the size of the entire circuit board. Alternatively, it is possible to mount a high-performance semiconductor element having a larger number of electrodes without increasing the number of electrodes on the circuit board and increasing the number of electrodes without changing the size of the entire circuit board.

以下、本発明の実施の形態を図面に基づいて説明する。
図１（ａ）は本発明の実施形態１の半導体装置の概略構成を示す平面模式図、図１（ｂ）は同半導体装置の図１（ａ）におけるＡ−Ａ’断面図である。この半導体装置はＢＧＡ型半導体装置であって、先に図６を用いて説明した従来のものと同様の部材に図６と同じ符号を付して説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1A is a schematic plan view showing a schematic configuration of a semiconductor device according to Embodiment 1 of the present invention, and FIG. 1B is a cross-sectional view taken along the line AA ′ in FIG. This semiconductor device is a BGA type semiconductor device, and the same members as those of the conventional device described above with reference to FIG.

回路基板１は、エポキシ樹脂、ポリイミド樹脂等からなる有機基板或いは窒化アルミニウム（ＡｌＮ）等からなるセラミック基板などを基材２とし、銅（Ｃｕ）等の金属により電極３を表面に形成するとともに裏面電極（図示せず）を形成し、表裏の電極間を接続する基板内金属配線（図示せず）を形成している。   The circuit board 1 includes an organic substrate made of epoxy resin, polyimide resin, or the like, or a ceramic substrate made of aluminum nitride (AlN) or the like as a base material 2, and an electrode 3 is formed on the surface with a metal such as copper (Cu) and the back surface. Electrodes (not shown) are formed, and in-substrate metal wiring (not shown) for connecting the front and back electrodes is formed.

半導体素子４は上面周縁部に電極６を配列したもので、回路基板１の表面の中央の所定位置（以下、素子搭載部１ａという）に接着剤５により接着しており、半導体素子４の電極６と回路基板１上の電極３とを金（Ａｕ）などの金属細線７により電気的に接続し、半導体素子４及び金属細線７を外部から保護するためにエポキシ樹脂等からなる封止樹脂８により回路基板１の表面を被覆している。また回路基板１の裏面電極上に外部基板との接続を行うための半田ボール等の突起電極９を形成している。   The semiconductor element 4 has electrodes 6 arranged on the peripheral edge of the upper surface, and is adhered to a predetermined position (hereinafter referred to as an element mounting portion 1 a) at the center of the surface of the circuit board 1 with an adhesive 5. 6 and the electrode 3 on the circuit board 1 are electrically connected by a metal thin wire 7 such as gold (Au), and the sealing resin 8 made of an epoxy resin or the like is used to protect the semiconductor element 4 and the metal thin wire 7 from the outside. Thus, the surface of the circuit board 1 is covered. Further, a protruding electrode 9 such as a solder ball for connecting to an external substrate is formed on the back electrode of the circuit board 1.

回路基板１および半導体素子４は矩形であり、半導体素子４の電極６の数が多いため、回路基板１上に形成する電極３を素子搭載部１ａの中央から基板外周部に向かって複数列配列しており、半導体素子４上の電極６と回路基板１上の電極３とを接続する金属細線７は互いに接触しないようにそれぞれのループ高さを変えている。   Since the circuit board 1 and the semiconductor element 4 are rectangular and the number of the electrodes 6 of the semiconductor element 4 is large, the electrodes 3 formed on the circuit board 1 are arranged in a plurality of rows from the center of the element mounting portion 1a toward the outer periphery of the board. The metal thin wires 7 that connect the electrodes 6 on the semiconductor element 4 and the electrodes 3 on the circuit board 1 have their loop heights changed so as not to contact each other.

この実施形態１の半導体装置が従来のものと相違するのは、回路基板１の複数の電極３上に、素子搭載部１ａの中央から外周に向かう方向に沿って次第に高い導電性突起物１０を形成している点である（電極３，導電性突起物１０に中央寄りから順に符号にａ，ｂ，ｃ・・を加えて示す）。つまり、最も中央寄りの電極３ａには加工は施さず、それより外周側の電極３ｂ上に導電性突起物１０ｂを形成し、さらに外周側の電極３ｃ上により高い導電性突起物１０ｃを形成している。   The semiconductor device of the first embodiment is different from the conventional one in that gradually higher conductive protrusions 10 are formed on the plurality of electrodes 3 of the circuit board 1 along the direction from the center of the element mounting portion 1a toward the outer periphery. (It is shown by adding a, b, c,... To the electrode 3 and the conductive protrusion 10 in order from the center). That is, the electrode 3a closest to the center is not processed, and the conductive protrusion 10b is formed on the electrode 3b on the outer peripheral side, and the higher conductive protrusion 10c is formed on the electrode 3c on the outer peripheral side. ing.

このことにより、先の図６と比較すると明らかなように、電極３の配置は従来と同じであっても、導電性突起物１０ｂ，１０ｃの存在により電極面に高低差が生じ、各電極３に接続する金属細線７の高低差が従来よりも拡大する。   Thus, as is clear from the comparison with FIG. 6 described above, even if the arrangement of the electrodes 3 is the same as the conventional one, the presence of the conductive protrusions 10b and 10c causes a difference in height on the electrode surface, and each electrode 3 The height difference of the thin metal wire 7 connected to the wire is larger than before.

したがって、電極３の配置が従来と同じであれば、金属細線７どうしが接触する恐れは確実に低減され、信頼性を高めることができる。
よって、電極３，３間の距離を小さくしても、各電極３に接続する金属細線７の高低差を確保することが可能なので、金属細線７どうしが接触する恐れは小さく、金属細線７と導電性突起物８との接合面積を確保することで、半導体装置の安定した生産が可能となる。 Therefore, if the arrangement of the electrodes 3 is the same as that of the prior art, the possibility that the fine metal wires 7 are in contact with each other is reliably reduced, and the reliability can be improved.
Therefore, even if the distance between the electrodes 3 and 3 is reduced, it is possible to ensure the height difference of the thin metal wires 7 connected to each electrode 3, so that the possibility that the fine metal wires 7 are in contact with each other is small. By securing the bonding area with the conductive protrusion 8, stable production of the semiconductor device is possible.

その結果、回路基板１上の電極数を減らすことなく電極領域を小さくして、したがって回路基板１全体のサイズを小さくして、半導体装置を小型化することが可能となる。
あるいは、回路基板１上の電極数を多くしながらも電極領域を増やすことなく、したがって回路基板１全体のサイズを変えることなく、電極数がより多い高機能の半導体素子４を搭載することが可能になる。 As a result, it is possible to reduce the size of the semiconductor device by reducing the electrode area without reducing the number of electrodes on the circuit board 1 and thus reducing the overall size of the circuit board 1.
Alternatively, it is possible to mount a highly functional semiconductor element 4 having a larger number of electrodes without increasing the number of electrodes while increasing the number of electrodes on the circuit board 1, and thus without changing the size of the entire circuit board 1. become.

図２（ａ）は本発明の実施形態２の半導体装置の概略構成を示す平面模式図、図２（ｂ）は同半導体装置の図２（ａ）におけるＢ−Ｂ’断面図である。
この半導体装置では、回路基板１上にその端辺に沿う方向（たとえばＢ−Ｂ’方向）に配列された複数の電極３上に、前記端辺の中央部から両端部に向かう方向に沿って次第に高い導電性突起物１０を形成している（電極３，導電性突起物１０に中央寄りから順に符号にａ１，ｂ１，ｃ１・・を加えて示す）。つまり、最も中央寄りの電極３ａ1にはごく低い導電性突起物１０ａ１を形成し、それより端部側の電極３ｂ１上に導電性突起物１０ｂ１を形成し、さらに端部側の電極３ｃ１上により高い導電性突起物１０ｃ１を形成し、さらに端部側の電極３ｄ１上により高い導電性突起物１０ｄ１を形成している。 2A is a schematic plan view showing a schematic configuration of the semiconductor device according to the second embodiment of the present invention, and FIG. 2B is a cross-sectional view taken along the line BB ′ in FIG. 2A of the semiconductor device.
In this semiconductor device, on the plurality of electrodes 3 arranged on the circuit board 1 in the direction along the edge (for example, the BB ′ direction), along the direction from the center of the edge toward both ends. Higher conductive protrusions 10 are gradually formed (shown by adding a1, b1, c1,... To the electrodes 3 and the conductive protrusions 10 in order from the center). That is, a very low conductive protrusion 10a1 is formed on the electrode 3a1 closest to the center, a conductive protrusion 10b1 is formed on the electrode 3b1 on the end side, and further higher on the electrode 3c1 on the end side. A conductive protrusion 10c1 is formed, and a higher conductive protrusion 10d1 is formed on the electrode 3d1 on the end side.

この構造でも、導電性突起物１０ａ１，１０ｂ１，１０ｃ１，１０ｄ１の存在により電極面に高低差が生じるので、金属細線７の長さが長くなっている場合でも、したがって金属細線７が垂れる恐れがある場合も、各電極３に接続する金属細線７の高低差が従来よりも拡大し、金属細線７どうしが接触する恐れが小さくなる。このことによって得られる効果は実施形態１と同様である。実施形態１の電極構造と実施形態２の電極構造とを組み合わせてもよい。   Even in this structure, since there is a difference in height on the electrode surface due to the presence of the conductive protrusions 10a1, 10b1, 10c1, and 10d1, even when the length of the fine metal wire 7 is long, the fine metal wire 7 may hang down. Also in this case, the height difference of the fine metal wires 7 connected to the respective electrodes 3 is larger than that in the conventional case, and the possibility that the fine metal wires 7 are in contact with each other is reduced. The effect obtained by this is the same as that of the first embodiment. The electrode structure of the first embodiment and the electrode structure of the second embodiment may be combined.

図３（ａ）は本発明の実施形態３の半導体装置の概略構成を示す平面模式図、図３（ｂ）は同半導体装置の図３（ａ）におけるＡ−Ａ’断面図である。
この半導体装置は、実施形態１の半導体装置と同様に、回路基板１の複数の電極３上に、素子搭載部１ａの中央から外周に向かう方向に沿って次第に高い導電性突起物１０を形成している。つまり最も中央寄りの電極３ａには加工は施さず、それより外周側の電極３ｂ上に導電性突起物１０ｂを形成し、さらに外周側の電極３ｃ上により高い導電性突起物１０ｃを形成している。その内、導電性突起物１０ｃは、素子搭載部の中央から外周に向かう方向に沿って高くなる段差形状に形成している。 FIG. 3A is a schematic plan view showing a schematic configuration of a semiconductor device according to Embodiment 3 of the present invention, and FIG. 3B is a cross-sectional view taken along the line AA ′ of FIG. 3A of the semiconductor device.
In the same manner as the semiconductor device of the first embodiment, this semiconductor device has progressively higher conductive protrusions 10 formed on the plurality of electrodes 3 of the circuit board 1 along the direction from the center of the element mounting portion 1a toward the outer periphery. ing. That is, the electrode 3a closest to the center is not processed, the conductive protrusion 10b is formed on the electrode 3b on the outer peripheral side, and the higher conductive protrusion 10c is formed on the electrode 3c on the outer peripheral side. Yes. Among them, the conductive protrusion 10c is formed in a stepped shape that increases along the direction from the center of the element mounting portion toward the outer periphery.

このような段差形状であれば、図３（ｃ）に示すように、金属細線７を接続するためのキャピラリ１１を移動可能とするための領域を縮小することが可能となり、回路基板１上の電極領域をより小さくすることが可能となる。よって半導体装置をより小型化することが可能となる。   With such a step shape, as shown in FIG. 3C, it is possible to reduce the area for allowing the capillary 11 for connecting the fine metal wires 7 to move. The electrode area can be made smaller. Therefore, the semiconductor device can be further downsized.

上記の各半導体装置の製造方法を図４を参照しながら説明する。
図４（ａ）に示すように、フレーム内に形成された複数区画の回路基板１のそれぞれについて、その素子搭載部（１ａ）に半導体素子４を接着剤５により接着する。 A method for manufacturing each of the semiconductor devices will be described with reference to FIG.
As shown in FIG. 4 (a), the semiconductor element 4 is bonded to the element mounting portion (1a) with an adhesive 5 for each of the plurality of sections of the circuit board 1 formed in the frame.

図４（ｂ）に示すように、回路基板１の電極３上に導電性突起物８を形成する。このためには、従来より電極３上に金属細線７を接続するために使用されているワイヤボンド法（図３ｃ参照）を利用し、キャピラリに挿通した金属細線の先端部を溶融させてボール状として電極３上に圧接し、その状態で金属細線を引きちぎることにより、電極３上にボール状物（バンプ）を残す。導電性突起物８をより高くするためにはバンプを積み重ねる。   As shown in FIG. 4B, conductive protrusions 8 are formed on the electrodes 3 of the circuit board 1. For this purpose, a wire bond method (see FIG. 3c) conventionally used to connect the fine metal wire 7 on the electrode 3 is used to melt the tip of the fine metal wire inserted into the capillary to form a ball shape. As shown in FIG. 2, the metal thin wire is torn off in this state, thereby leaving a ball-shaped object (bump) on the electrode 3. In order to make the conductive protrusion 8 higher, bumps are stacked.

図４（ｃ）に示すように、半導体素子４の電極６と回路基板１上の電極３とを金（Ａｕ）などの金属細線７により電気的に接続する。この際には、金属細線７どうしの接触を防止するため、基板外周部分の電極３に接続する金属細線７のループ高さを高くする。   As shown in FIG. 4C, the electrode 6 of the semiconductor element 4 and the electrode 3 on the circuit board 1 are electrically connected by a thin metal wire 7 such as gold (Au). At this time, in order to prevent the metal wires 7 from contacting each other, the loop height of the metal wires 7 connected to the electrode 3 on the outer peripheral portion of the substrate is increased.

図４（ｄ）に示すように、半導体素子４及び金属細線７を外部から保護するために、封止樹脂８により複数区画の回路基板１の表面を一括して被覆して封止する。このための封止工法としては、例えば金型を用いたトランスファー成型方法や液状樹脂を用いた印刷工法等を実施することができる。   As shown in FIG. 4D, in order to protect the semiconductor element 4 and the fine metal wires 7 from the outside, the surface of the circuit board 1 in a plurality of sections is collectively covered and sealed with a sealing resin 8. As the sealing method for this purpose, for example, a transfer molding method using a mold or a printing method using a liquid resin can be carried out.

図４（ｅ）に示すように、樹脂封止体１２の回路基板１の裏面電極上に半田ボール等の外部接続用突起電極９を形成する。この形成方法としては、例えば裏面電極上に半田ボールを搭載するか、或いは半田ペーストを印刷した後、リフロー等の温度を加えることで電極材料に溶着させる。   As shown in FIG. 4E, external connection protruding electrodes 9 such as solder balls are formed on the back electrode of the circuit board 1 of the resin sealing body 12. As this formation method, for example, a solder ball is mounted on the back electrode, or after solder paste is printed, a temperature such as reflow is applied to weld the electrode material.

図４（ｆ）に示すように、樹脂封止体１２を１区画の回路基板１ごとに分割することで個片の半導体装置を形成する。分割方法には、例えばダイシングブレードを使用する方法や、金型による打ち抜き方法がある。   As shown in FIG. 4F, the resin sealing body 12 is divided for each section of the circuit board 1 to form individual semiconductor devices. Examples of the dividing method include a method using a dicing blade and a punching method using a mold.

なお、導電性突起物１０を形成するためには、上述したようにワイヤボンド法を利用できるほか、回路基板１上にあらかじめＡｕめっきやはんだめっき等を施すめっき工法を利用することも可能である。   In order to form the conductive protrusions 10, the wire bonding method can be used as described above, and a plating method in which Au plating or solder plating or the like is applied to the circuit board 1 in advance can also be used. .

図３に示した段差形状の導電性突起物１０をめっき工法で形成するためには、たとえば、図５（ａ），（ｂ）に示すように、回路基板１の基材２上に円形等の電極３およびその周囲を囲む前記電極３の電極面よりも厚いソルダーレジスト１３を形成し、図５（ｃ）に示すように、電極３とその所定方向における隣接部分のソルダーレジスト１３とが露出する開口１４ａを持ったマスク１４をレジストなどを用いて形成し、図５（ｄ），（ｅ）に示すように、マスク１４を介してめっきを施すことにより、電極３上とソルダーレジスト１３上とにわたる段差形状の導電性突起物１０を形成する。   In order to form the step-shaped conductive protrusion 10 shown in FIG. 3 by a plating method, for example, as shown in FIGS. 5A and 5B, a circular shape or the like is formed on the base material 2 of the circuit board 1. The electrode 3 and the solder resist 13 thicker than the electrode surface of the electrode 3 surrounding the electrode 3 are formed, and as shown in FIG. 5C, the electrode 3 and the solder resist 13 of the adjacent portion in the predetermined direction are exposed. A mask 14 having an opening 14a is formed using a resist or the like, and plating is performed through the mask 14 as shown in FIGS. 5D and 5E, so that the electrode 3 and the solder resist 13 are formed. Step-shaped conductive protrusions 10 are formed.

以上、ＢＧＡ型半導体装置について説明してきたが、ＢＧＡ型でないアレイ型半導体装置などにも適用できる。さらには樹脂で直接に封止するタイプでなくとも、たとえば凹状のパッケージ内に半導体素子を封止するタイプの半導体装置にも適用できる。   Although the BGA type semiconductor device has been described above, the present invention can also be applied to an array type semiconductor device that is not a BGA type. Further, even if the type is not directly sealed with a resin, the present invention can be applied to a semiconductor device in which a semiconductor element is sealed in a concave package, for example.

本発明は、電極数の多い半導体素子を搭載しながらも小型の半導体装置を安定に製造するのに有用である。   The present invention is useful for stably manufacturing a small semiconductor device while mounting a semiconductor element having a large number of electrodes.

本発明の実施形態１の半導体装置の概略構成図1 is a schematic configuration diagram of a semiconductor device according to a first embodiment of the present invention. 本発明の実施形態２の半導体装置の概略構成図Schematic configuration diagram of a semiconductor device according to a second embodiment of the present invention. 本発明の実施形態３の半導体装置の概略構成図Schematic configuration diagram of a semiconductor device according to a third embodiment of the present invention. 本発明の半導体装置の製造方法を説明する断面図Sectional drawing explaining the manufacturing method of the semiconductor device of this invention 本発明の半導体装置の導電性突起物を形成する工程の説明図Explanatory drawing of the process of forming the conductive protrusion of the semiconductor device of this invention 従来の半導体装置の概略構成図Schematic configuration diagram of a conventional semiconductor device

符号の説明Explanation of symbols

１ 回路基板
２ 基材
３ 電極
４ 半導体素子
６ 電極
７ 金属細線
10 導電性突起物
13 ソルダーレジスト
14 マスク DESCRIPTION OF SYMBOLS 1 Circuit board 2 Base material 3 Electrode 4 Semiconductor element 6 Electrode 7 Metal fine wire
10 Conductive protrusion
13 Solder resist
14 Mask

Claims (7)

半導体素子と、前記半導体素子を搭載した回路基板と、前記半導体素子の上面に形成された複数の電極と前記半導体素子の複数の電極に対応して前記回路基板の素子搭載部の周囲に形成された複数の電極とを電気的に接続した金属細線とを有した半導体装置において、前記回路基板の複数の電極上に、前記素子搭載部の中央から外周に向かう方向に沿って次第に高くなるように導電性突起物が形成されている半導体装置。   A semiconductor element; a circuit board on which the semiconductor element is mounted; a plurality of electrodes formed on an upper surface of the semiconductor element; and a plurality of electrodes on the semiconductor element corresponding to the plurality of electrodes on the circuit board. In the semiconductor device having the thin metal wires electrically connected to the plurality of electrodes, the height gradually increases along the direction from the center of the element mounting portion toward the outer periphery on the plurality of electrodes of the circuit board. A semiconductor device in which a conductive protrusion is formed. 導電性突起物はさらに、回路基板の端辺の中央から両端のそれぞれに向かう方向に沿って次第に高くなるように形成されている請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the conductive protrusion is further formed so as to gradually become higher along a direction from the center of the end side of the circuit board toward each of the both ends. 導電性突起物は、素子搭載部の中央から外周に向かう方向に沿って高くなる段差形状を有している請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the conductive protrusion has a stepped shape that increases in a direction from the center of the element mounting portion toward the outer periphery. 半導体素子を回路基板上に搭載する工程と、前記半導体素子の上面に形成された複数の電極と前記半導体素子の複数の電極に対応して前記回路基板の素子搭載部の周囲に形成された複数の電極とをそれぞれ金属細線で電気的に接続する工程とを有した、半導体装置の製造方法において、
前記回路基板の複数の電極のそれぞれに金属細線を接続するに先立って、前記複数の電極上に所定の方向に沿って次第に高くなるように導電性突起物を形成し、この導電性突起物に対して金属細線を接続する半導体装置の製造方法。 A step of mounting a semiconductor element on a circuit board; a plurality of electrodes formed on an upper surface of the semiconductor element; and a plurality of electrodes formed around the element mounting portion of the circuit board corresponding to the plurality of electrodes of the semiconductor element A step of electrically connecting each of the electrodes with a thin metal wire,
Prior to connecting a thin metal wire to each of the plurality of electrodes of the circuit board, a conductive protrusion is formed on the plurality of electrodes so as to gradually increase along a predetermined direction, and the conductive protrusion is formed on the conductive protrusion. A method of manufacturing a semiconductor device in which a thin metal wire is connected to the semiconductor device. 導電性突起物は、ワイヤボンド法を利用して金属ボールを所望高さまで積み重ねることにより形成する請求項４記載の半導体装置の製造方法。   5. The method of manufacturing a semiconductor device according to claim 4, wherein the conductive protrusion is formed by stacking metal balls to a desired height using a wire bond method. 導電性突起物は、めっき工法によって形成する請求項４記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 4, wherein the conductive protrusion is formed by a plating method. めっき工法によって導電性突起物を形成する際に、回路基板上に電極とその周囲を囲む前記電極よりも厚いソルダーレジストとを形成し、前記電極とその所定方向に隣接したソルダーレジストの一部とをマスク開口より露出させてめっきを施すことにより、前記電極上とソルダーレジスト上とにわたる段差形状の導電性突起物を形成する請求項６記載の半導体装置の製造方法。   When forming conductive protrusions by a plating method, an electrode and a solder resist thicker than the electrode surrounding the electrode are formed on the circuit board, and the electrode and a part of the solder resist adjacent to the electrode in a predetermined direction The method of manufacturing a semiconductor device according to claim 6, wherein a step-shaped conductive protrusion extending over the electrode and the solder resist is formed by performing plating while exposing the substrate from the mask opening.
JP2006144733A 2006-05-25 2006-05-25 Semiconductor device and its manufacturing method Pending JP2007317808A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006144733A JP2007317808A (en) 2006-05-25 2006-05-25 Semiconductor device and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006144733A JP2007317808A (en) 2006-05-25 2006-05-25 Semiconductor device and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2007317808A true JP2007317808A (en) 2007-12-06

Family

ID=38851421

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006144733A Pending JP2007317808A (en) 2006-05-25 2006-05-25 Semiconductor device and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2007317808A (en)

Similar Documents

Publication Publication Date Title
JP4270282B2 (en) Manufacturing method of semiconductor device
JP2007123595A (en) Semiconductor device and its mounting structure
JP2002110898A (en) Semiconductor device
JP5232394B2 (en) Manufacturing method of semiconductor device
US8421199B2 (en) Semiconductor package structure
KR101563911B1 (en) Semiconductor package
JPH11312706A (en) Resin encapsulating semiconductor device and its manufacture, and lead frame
JP2001015679A (en) Semiconductor device and manufacture thereof
KR20060121823A (en) Reversible leadless package and methods of making and using same
JP2009044110A (en) Semiconductor device and its manufacturing method
JP2009099697A (en) Semiconductor apparatus and method of manufacturing the same
JP2009105334A (en) Semiconductor device and manufacturing method therefor
JP2010147070A (en) Semiconductor device
TWI458062B (en) Pad configurations for an electronic package assembly
JP2009099905A (en) Semiconductor device
JP2008085002A (en) Semiconductor device and its manufacturing method
JP2010010269A (en) Semiconductor device, intermediate for manufacturing semiconductor device, and method of manufacturing them
JP2001024133A (en) Lead frame, resin sealed semiconductor device employing it and manufacture thereof
JP5499437B2 (en) Mold package
JP2005116916A (en) Semiconductor device and its manufacturing method
JP2007141947A (en) Semiconductor device and its manufacturing method
JP2007317808A (en) Semiconductor device and its manufacturing method
JP2009016738A (en) Semiconductor apparatus
JP2005116915A (en) Semiconductor device
JP4140012B2 (en) Chip-shaped electronic component, manufacturing method thereof and mounting structure

Legal Events

Date Code Title Description
RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20080430