JP2007312439A - Solid-state image pick-up device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compact solid-state image pick-up device that solves the problem that when increasing the sensitivity of a video camera or the like by vertical pixels addition processing in a solid state image sensing device, conventional processings cause image displacement in the vertical direction, resulting in an increased circuit size. <P>SOLUTION: The solid-state image pick-up device has the solid state image sensing device comprising a plurality of photoelectric conversion elements that are disposed in a two-dimensional matrix shape, and is configured such that a vertical processing circuit has a vertical outline extraction circuit, and the vertical outline extraction circuit outputs vertical outline signals in which outline components of an image in the vertical direction are extracted from signals inputted to the outline processing circuit. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a device that handles a video signal, in particular, a video camera or a camera device, and more particularly to high-sensitivity imaging by pixel addition in a solid-state imaging device.

A three-plate video camera is provided with a solid-state imaging device such as a CCD for each of R (red), G (green), and B (blue), and its sensitivity has been steadily improved as technology advances. Even when such a video camera with improved sensitivity is used, a sensitivity higher than that in the normal shooting mode may be required when shooting at night.
In the case of improving the sensitivity, it is easy to electrically amplify the signal level, but in this case, the noise is also amplified in the same manner as the signal. Therefore, when amplified with a large gain, the image is covered with noise, which is not preferable.
In view of this, there has been a method of increasing the sensitivity by adding pixels between adjacent horizontal or vertical pixels. In particular, in a CCD camera, a large amount of noise is mixed in the output amplifier section of the image sensor, and there is a problem if the output signal from the output amplifier section is amplified. Therefore, if the signal is added in the CCD, it is possible to increase only the signal level with little increase in noise.

As a conventional technique of a solid-state imaging device that achieves high sensitivity by adding pixels in the vertical direction, there is a driving method disclosed in, for example, Japanese Patent Laid-Open No. 3-166875. The technique disclosed in this publication adds, for example, charges for two pixels adjacent in the vertical direction and outputs them from the image pickup device, and can achieve almost twice the sensitivity. FIG. 11 shows a configuration of a solid-state imaging device using this technique.
In the configuration of FIG. 11, a solid-state imaging device 110 such as a CCD converts an optical signal of a captured image into an electrical signal, and the electrical signal is output based on a signal from a CCD drive circuit 111. The output of the solid-state imaging device 110 is subjected to correlated double sampling (CDS) and amplification in the preamplifier 112, and offset adjustment and gain adjustment are performed in the analog process circuit 113. An output signal of the analog process circuit 113 is input to the vertical interpolation circuit 115 via the A / D conversion circuit 114. In the vertical interpolation circuit 115, a lost signal is generated by the vertical pixel addition process. The output signal of the vertical interpolation circuit 115 is supplied to the digital process circuit 117.

  In the digital process circuit 117, first, nonlinear processing such as gamma correction and knee correction is performed by the gamma knee circuit 122, and processing for enhancing the contour of the video signal is performed by the contour enhancement circuit 123. Further, the matrix conversion circuit 124 performs matrix conversion processing from the RGB three primary color signals to luminance color difference signals such as Y, Pb, and Pr, and the digital / analog (D / A) conversion circuit 118 and parallel / serial (P / S). ) Output to the conversion circuit 119. The D / A conversion circuit 118 converts the digital signal into an analog signal and outputs the analog signal to the output terminal 120. The P / S conversion circuit 119 performs parallel / serial conversion on the digital signal to obtain a digital / serial signal. Output to the output terminal 121.

Next, the configuration and operation of the vertical interpolation circuit 115 in the conventional solid-state imaging device will be described with reference to FIGS. FIG. 12 is a block diagram showing the configuration of the vertical interpolation circuit 115 in the conventional solid-state imaging device. FIG. 13 is a signal waveform diagram in the vertical interpolation circuit 115 of FIG.
The vertical interpolation circuit 115 includes, for example, two one horizontal scanning line period delay circuits (hereinafter referred to as 1H delay circuits) 141 and 142, an average circuit 150, and a selector 161. The first 1H delay circuit 141 and the second 1H delay circuit 142 delay the input video signals by one horizontal scanning line period (1H). Accordingly, the first 1H delay circuit 141 outputs a 1H delay signal V1 that is a video signal delayed by 1H with respect to the input signal Vin. The second 1H delay circuit 142 outputs a 2H delay signal V2, which is a video signal delayed by 2H with respect to the input signal Vin. The average circuit 150 receives the input video signal Vin and the 2H delay signal V2, and outputs an averaged signal V11. That is, in the averaging circuit 150, the multipliers 201 and 202 multiply the input video signal Vin and the 2H delay signal V2 by 1/2, and then the respective signals are added by the adder 203. The selector 161 selects and outputs any one signal from the output V11 of the averaging circuit 150 and the 1H delay signal V1 in accordance with the control signal Vsel.

  In the solid-state image sensor 110 described above, since vertical pixels are added, the input signal Vin to the vertical interpolation circuit 115 is present every horizontal scanning line period (1H) as shown in FIG. Similarly, the 1H delay signal V1, 2H delay signal V2, and the output signal V11 of the averaging circuit 150 also have a signal every 1H. Therefore, as shown in FIG. 13, the control signal Vsel of the selector 161 repeats H (high level) and L (low level) with a predetermined width every 1H, thereby outputting the 1H delay signal V1 and the output of the averaging circuit 50. Any one of the signals V11 can be selected. That is, as the output of the vertical interpolation circuit 115, as shown by Vout in FIG. 13, a signal obtained by averaging the preceding and succeeding signals is inserted in place of the signal lost by the vertical pixel addition process, and the high sensitivity of the video signal is obtained. We are trying to make it.

Next, the configuration of the contour emphasis circuit 123 in the digital process circuit 117 will be described with reference to FIG.
The contour emphasis circuit 123 includes, for example, a vertical contour extraction circuit 131, a horizontal contour extraction circuit 132, two multipliers 133 and 134, and an adder 135. The vertical contour extraction circuit 131 has two 1H delay circuits 145 and 146 and a product-sum circuit 155, and the product-sum circuit 155 has three multipliers 207, 208 and 209 and an adder 216. .
The video signal Vin input to the contour enhancement circuit 123 is input to the product-sum circuit 155 through the first 1H delay circuit 145 of the vertical contour extraction circuit 131. The first 1H delay circuit 145 delays the input video signal for 1H period. The 1H delay signal V1 that is the output signal of the first 1H delay circuit 145 is supplied to the product-sum circuit 155, the second 1H delay circuit 146, the horizontal contour extraction circuit 132, and the adder 135. The second 1H delay circuit 146 delays the video signal for 1H period, and outputs a 2H delay signal V2 delayed for 2H period with respect to the input video signal Vin. The 2H delay signal V2 is supplied to the product-sum circuit 155.

In the product-sum circuit 155, the input video signal Vin, the 1H delay signal V1, and the 2H delay signal V2 are input, and each signal is multiplied by a predetermined coefficient and added. That is, in the product-sum circuit 155, the multiplier 207 multiplies the input video signal Vin by the coefficient -1/4, the multiplier 208 multiplies the 1H delay signal V1 by the coefficient 1/2, and the multiplier 209 performs the 2H delay. The signal V2 is multiplied by a coefficient -1/4.
With the above processing, the output signal DV of the vertical contour extraction circuit 131 becomes a signal represented by the following equation (1).

  DV = -1 / 4 * Vin + 1/2 * V1-1 / 4 * V2 (1)

The vertical contour extraction circuit 131 outputs a high frequency component corresponding to the vertical contour component shown in Expression (1). The output signal DV of the vertical contour extraction circuit 131 is multiplied by the vertical contour enhancement gain KV in the multiplier 133 and then input to the adder 135.
Further, the horizontal contour extraction circuit 132 outputs a horizontal contour signal DH in which the input 1H delay signal V1 is only the contour component in the horizontal direction of the image. The horizontal contour signal DH is multiplied by the horizontal contour enhancement gain KH in the multiplier 134 and then input to the adder 135. That is, the adder 135 receives the 1H delay signal V1, the vertical contour signal (KV * DV), and the horizontal contour signal (KH * DH). In the adder 135, the 1H delay signal V1, the vertical contour signal (KV * DV), and the horizontal contour signal (KH * DH) are added and output as a signal in which the contour component is emphasized in both the horizontal and vertical directions. The
Note that the configuration and operation of the horizontal contour extracting circuit 132 in the contour emphasizing circuit 123 are not directly related to the present invention, and thus description thereof is omitted.
Japanese Patent Laid-Open No. 3-166875

  The conventional solid-state imaging device configured as described above has a problem that an image shift occurs in the vertical direction in the high-sensitivity shooting mode such as night shooting as compared with the sensitivity processing in the normal shooting mode. That is, the video signal L1 output as the first line in the high sensitivity processing is a signal obtained by mixing the video signals of the first line and the second line in the normal sensitivity processing, and the vertical position of the image by the video signal L1 is This corresponds to an intermediate position between the first line and the second line of normal sensitivity processing. The video signal (L1 + L3) / 2 output as the second line in the high sensitivity processing is an average signal of the video signals of the first line to the fourth line in the normal sensitivity processing, and the vertical position of the image is This corresponds to an intermediate position between the second line and the third line of normal sensitivity processing. Therefore, in the above-described conventional solid-state imaging device, the video shot in the high-sensitivity shooting mode is an image of 1/2 line in the vertical direction compared to the normal shooting mode in which the vertical pixel addition process is not performed. There is a gap.

  Further, in the conventional solid-state imaging device, it is necessary to provide a vertical interpolation circuit 115 as shown in FIG. 12 in order to restore the video signal lost by the vertical pixel addition process. Since the 1H delay circuit in the vertical interpolation circuit 115 requires a large memory capacity, the solid-state imaging device has a problem that the circuit scale becomes large and the power consumption increases.

  The present invention solves the above-described problems in the conventional solid-state imaging device, and an object thereof is to eliminate a vertical shift of an image in high sensitivity by vertical pixel addition processing in a solid-state imaging device. It is another object of the present invention to provide a small individual imaging device by reducing the circuit scale and suppressing the increase in power consumption in the vertical interpolation processing accompanying the increase in sensitivity of the solid-state imaging device.

In order to achieve the above object, a solid-state imaging device according to the present invention includes:
In a solid-state imaging device including a solid-state imaging device composed of a plurality of photoelectric conversion elements arranged in a two-dimensional matrix,
Vertical pixel addition command means for adding signal charges of a plurality of pixels in the vertical direction to the solid-state imaging device;
A vertical interpolation circuit for outputting a video signal subjected to addition processing of the solid-state imaging device for each horizontal scanning line period;
A contour processing circuit having a vertical contour extraction circuit and an arithmetic circuit,
The vertical interpolation circuit outputs one horizontal scanning line period delay signal obtained by delaying a video signal subjected to vertical pixel addition processing by one horizontal scanning line period;
A selector that receives the video signal and the one horizontal scanning line period delay signal and selects and outputs one of the signals based on a control signal that is switched every horizontal scanning line period;
The vertical contour extraction circuit is configured to output a vertical contour signal obtained by extracting a contour component of a vertical image from an input signal to the contour processing circuit,
The arithmetic circuit is configured to subtract an output signal of the vertical contour extraction circuit from an input signal of the contour processing circuit when performing vertical pixel addition processing in the solid-state image sensor, and performs vertical pixel addition processing in the solid-state image sensor. When not performed, the output signal of the vertical contour extraction circuit is added to the input signal of the contour processing circuit.

A solid-state imaging device according to another aspect of the invention includes:
In a solid-state imaging device including a solid-state imaging device composed of a plurality of photoelectric conversion elements arranged in a two-dimensional matrix,
Vertical pixel addition command means for adding signal charges of a plurality of pixels in the vertical direction to the solid-state imaging device;
A vertical interpolation circuit for outputting a video signal subjected to addition processing of the solid-state imaging device for each horizontal scanning line period;
A contour processing circuit having a vertical contour extraction circuit, a sign inversion circuit, and an addition circuit;
The vertical interpolation circuit outputs one horizontal scanning line period delay signal obtained by delaying a video signal subjected to vertical pixel addition processing by one horizontal scanning line period;
A selector that receives the video signal and the one horizontal scanning line period delay signal and selects and outputs one of the signals based on a control signal that is switched every horizontal scanning line period;
The vertical contour extraction circuit is configured to output a vertical contour signal obtained by extracting a contour component of a vertical image from an input signal to the contour processing circuit,
The sign inversion circuit is configured to invert the sign of the output signal of the vertical contour extraction circuit when performing vertical pixel addition processing in a solid-state imaging device,
The adder circuit is configured to add the output signal of the sign inverting circuit to the input signal to the contour processing circuit.

  The solid-state imaging device of the present invention configured as described above can eliminate a vertical shift of an image in increasing sensitivity by vertical pixel addition in the solid-state imaging device. In addition, according to the present invention, it is possible to suppress an increase in circuit scale and power consumption in the vertical interpolation processing accompanying the increase in sensitivity of the solid-state imaging device. Furthermore, the solid-state imaging device of the present invention can reduce the one horizontal scanning line delay circuit having a large circuit scale by providing a contour processing circuit as a vertical smoothing means at the time of high-sensitivity imaging, and can achieve a compact solid-state imaging. An apparatus can be provided.

  Embodiments 1 to 4 which are preferred embodiments of a solid-state imaging device according to the present invention will be described below with reference to the accompanying drawings.

Embodiment 1
FIG. 1 is a block diagram showing the configuration of the solid-state imaging device according to Embodiment 1 of the present invention. As shown in FIG. 1, in the solid-state imaging device of the first embodiment, an optical signal of an image captured by a solid-state imaging device 10 such as a CCD is converted into an electrical signal, and the electrical signal is used as vertical pixel addition command means. Is output to the preamplifier 12 based on the signal from the CCD driving circuit 11. The signal from the solid-state imaging device 10 is subjected to correlated double sampling (CDS) and amplification in the preamplifier 12 and is output to the analog process circuit 13. In the analog process circuit 13, offset adjustment and gain adjustment are performed. The output signal of the analog process circuit 13 is converted into a digital signal by the A / D conversion circuit 14 and input to the vertical interpolation circuit 15. In the vertical interpolation circuit 15, interpolation processing is performed on signals that have disappeared due to vertical pixel addition processing. The output signal of the vertical interpolation circuit 15 is output to the digital process circuit 17.

  The digital process circuit 17 includes a gamma knee circuit 22, an outline enhancement circuit 23, and a matrix conversion circuit 24. The gamma knee circuit 22 performs non-linear processing such as gamma correction and knee correction. In the contour emphasizing circuit 23, processing for enhancing the contour of the video signal is performed. The matrix conversion circuit 24 performs matrix conversion processing for converting the RGB primary color signals into luminance color difference signals such as Y, Pb, and Pr. An output from the matrix conversion circuit 24 is output to a digital / analog conversion circuit (abbreviated as D / A conversion circuit) 18 and a parallel / serial conversion circuit (abbreviated as P / S conversion circuit) 19. The D / A conversion circuit 18 converts the digital signal into an analog signal and outputs it to the output terminal 20. The P / S conversion circuit 19 performs parallel / serial conversion on the digital signal and outputs it to the output terminal 21 as a digital / serial signal.

  FIG. 2 is a block diagram illustrating a configuration of the vertical interpolation circuit 15 according to the first embodiment. As shown in FIG. 2, the vertical interpolation circuit 15 includes a 1 horizontal scanning line period delay circuit (hereinafter abbreviated as 1H delay circuit) 41 and a selector 61. The 1H delay circuit 41 outputs a 1H delay signal V1 obtained by delaying the video signal Vin subjected to the vertical pixel addition processing by one horizontal scanning line period (1H). The selector 61 is configured to receive the video signal Vin and the 1H delay signal V1 from the 1H delay circuit 41 and output (Vout) one of the signals based on the control signal Vsel.

With respect to the solid-state imaging device of Embodiment 1 configured as described above, the operation of the vertical interpolation circuit 15 will be described with reference to FIG. FIG. 3 is a waveform diagram showing signals formed in the vertical interpolation circuit 15.
In increasing the sensitivity of the solid-state imaging device of the first embodiment, the solid-state imaging device 10 adds two adjacent pixels in the vertical direction. Since the vertical pixel addition processing is performed in this way, the input signal Vin to the vertical interpolation circuit 15 has a signal for each horizontal scanning line (1H) as shown in FIG. In FIG. 3, a waveform indicated by a broken line indicates a waveform disappeared by the vertical pixel addition process.

  As shown in FIG. 3, the 1H delayed signal V1 obtained by delaying the input signal Vin, which is a video signal, by 1H also has a signal every 1H, like the input signal Vin. As shown in FIG. 3, the control signal Vsel input to the selector 61 has a pulse waveform that repeats “H” (high level) and “L” (low level) every 1H. This control signal Vsel is input to the selector 61, and the selector 61 selects the signal having the signal among the input signal Vin and the 1H delay signal V1. As a result, the output signal Vout from the vertical interpolation circuit 15 has a video signal in any line as shown in FIG.

Next, the output signal Vout from the vertical interpolation circuit 15 in the first embodiment has a line position of the high sensitivity processing in the high sensitivity shooting mode ½ in the vertical direction compared to the line position of the sensitivity processing in the normal shooting mode. Explain that there is no misalignment of lines.
The first line signal L1 of the video signal subjected to the vertical pixel addition processing is a mixture of the original video signals of the first line and the second line, and the vertical position of the image is the middle, that is, the first line signal. Corresponds to the position of 1.5 lines. Similarly, the third line signal L3 is originally a mixture of the video signals of the third line and the fourth line, and the vertical position of the image corresponds to the middle, that is, the position of the 3.5th line.

The solid-state imaging device according to the first embodiment is configured to output, for example, the first line signal L1 subjected to sensitivity processing in the normal photographing mode on each of the first line and the second line in high sensitivity processing in the high sensitivity photographing mode. ing. Therefore, in the solid-state imaging device according to the first embodiment, the signal subjected to the vertical pixel addition process is interpolated, and the video signal is substantially output in each line.
As described above, according to the solid-state imaging device of the first embodiment, the same video signal is continuously output twice by the vertical interpolation circuit 15 for the signal subjected to the vertical pixel addition processing in the solid-state imaging device 10. Since it is configured, it is possible to prevent a vertical image shift equivalent to 1/2 line due to the vertical pixel addition processing with a simple configuration.

  In the above description of the embodiment, the case of the vertical pixel addition process in which two pixels in the vertical direction are added in the solid-state imaging device 10 is described. However, in the vertical pixel addition process in which three or more pixels in the vertical direction are added. Also, the same effect can be obtained by using the output of the 1H delay circuit a plurality of times with a configuration substantially similar to the configuration of the first embodiment.

<< Embodiment 2 >>
Next, a solid-state imaging device according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 4 is a block diagram showing the configuration of the solid-state imaging device according to Embodiment 2 of the present invention. In FIG. 4, components having substantially the same functions and configurations as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted. The solid-state imaging device of the second embodiment is a device in which a vertical LPF circuit 16 is added to the solid-state imaging device of the first embodiment. The vertical LPF circuit 16 is configured to receive a signal from the vertical interpolation circuit 15 described in the second embodiment.

  FIG. 5 is a block diagram showing a configuration of the vertical LPF circuit 16 in the second embodiment. As shown in FIG. 5, the vertical LPF circuit 16 has two 1H delay circuits 42 and 43 and a product-sum circuit 53. The product-sum circuit 53 includes three multipliers 103, 104, and 105 and an adder 113. In the vertical LPF circuit 16 of the second embodiment, the input signal Vin from the vertical interpolation circuit 15 is input to the product-sum circuit 53 and the first 1H delay circuit 42, and the first 1H delay circuit 42 is only 1H. The delayed 1H delay signal V1 is output to the product-sum circuit 53 and the second 1H delay circuit 43. The second 1H delay circuit 43 outputs a 2H delay signal V2 further delayed by 1H with respect to the input 1H delay signal V1 to the product-sum circuit 53. The product-sum circuit 53 is configured to multiply each of the input signal Vin, the 1H delay signal V1 and the 2H delay signal V2 by a coefficient, and add the multiplied values to output.

Next, the operation of the vertical LPF circuit 16 in the solid-state imaging device of Embodiment 2 configured as described above will be described with reference to FIG. FIG. 6 is a waveform diagram showing each signal in the vertical LPF circuit 16 of the second embodiment.
The video signal Vin input to the vertical LPF circuit 15 shown in FIG. 6 is the signal described as the output signal Vout from the vertical interpolation circuit 15 in FIG. Therefore, the 1H delay signal V1 from the first 1H delay circuit 42 is a signal obtained by delaying the video signal Vin shown in FIG. 6 by 1H, and the 2H delay signal V2 from the second 1H delay circuit 43 is the video signal. This is a signal obtained by delaying Vin by 2H.

The product-sum circuit 53 receives the video signal Vin, the 1H delay signal V1, and the 2H delay signal V2. The video signal Vin input to the product-sum circuit 53 is multiplied by ¼ in the multiplier 103 and output to the adder 113. Similarly, the 1H delay signal V1 input to the product-sum circuit 53 is multiplied by 1/2 in the multiplier 104 and output to the adder 113, and the 2H delay signal V2 is multiplied by 1/4 in the multiplier 105. To the adder 113.
The adder 113 in the product-sum circuit 53 adds the outputs of the multipliers 103, 104, and 105 and outputs the result as an output signal Vout. That is, the output signal Vout of the vertical LPF circuit 16 is expressed by the following equation (2).

  Vout = 1/4 * Vin + 1/2 * V1 + 1/4 * V2 (2)

  That is, the vertical LPF circuit 15 in the second embodiment is a 3-tap vertical LPF (vertical low-pass filter) having coefficients (1/4, 1/2, 1/4).

  As described above, the product-sum circuit 53 multiplies the input video signal Vin, 1H delay signal V1, and 2H delay signal V2 by 1/4, 1/2, and 1/4, respectively, as shown in Expression (2). Are added. Therefore, for example, in the horizontal scanning line period shown in (1) of FIG. 6, the input video signal Vin is the third line L3, the 1H delay signal V1 is the first line L1, and the 2H delay signal V2 is the first line L3. One line L1. For this reason, the output signal Vout in the horizontal scanning line period shown in (1) becomes 3/4 * L1 + 1/4 * L3 by the equation (2).

  Further, in the horizontal scanning line period shown in (2) of FIG. 6, the video signal Vin is the third line L3, the 1H delay signal V1 is the third line L3, and the 2H delay signal V2 is the first line L1. is there. Therefore, the output signal Vout in the horizontal scanning line period shown in (2) is 1/4 * L1 + 3/4 * L3. That is, the output signal Vout of the vertical LPF circuit 16 is averaged for each line, the change for each line is smoothed, and the discontinuity in the vertical direction is removed.

  As described above, according to the solid-state imaging device of the second embodiment, the same video signal is continuously output twice by the vertical interpolation circuit 15 with respect to the signal subjected to the vertical pixel addition processing in the solid-state imaging device 10. Therefore, it is possible to prevent the vertical image shift corresponding to 1/2 line due to the vertical pixel addition processing and to obtain the vertical LPF characteristic that the vertical LPF circuit 16 obtains a smooth image in the vertical direction.

  In the second embodiment, the configuration in which the vertical LPF circuit 16 uses a multiplier and an adder has been described. However, the present invention is not limited to this configuration, and is generally replaced with a multiplier. It goes without saying that the circuit configuration used is also included in the present invention. In particular, if the coefficient is fixed, the vertical LPF circuit can be configured by a bit shifter and an adder. In addition, the vertical LPF circuit of the second embodiment is configured by a 3-tap (coefficient: 1/4, 1/2, 1/4) FIR filter circuit, but the coefficient and the number of taps depend on the configuration of the apparatus used. Accordingly, a desired numerical value is set.

<< Embodiment 3 >>
Next, a solid-state imaging device according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 7 is a block diagram showing a configuration of a vertical LPF circuit in the solid-state imaging device according to the third embodiment of the present invention. The solid-state imaging device according to the third embodiment is a device in which the vertical LPF circuit 160 is added to the solid-state imaging device according to the first embodiment described above. The vertical LPF circuit 160 is replaced with the vertical LPF circuit 16 according to the second embodiment described above. It is what was used. Therefore, in the solid-state imaging device according to the third embodiment, the configuration other than the vertical LPF circuit 160 is the same as the configuration shown in FIGS. 1 and 4 described above. In FIG. 7, components having substantially the same functions and configurations as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 7, the vertical LPF circuit 160 according to the third embodiment includes a selector 62, a 1H delay circuit 44, and a product-sum circuit 53. The product-sum circuit 53 includes three multipliers 103, 104, and 105 and an adder 113, as in the second embodiment. In the vertical LPF circuit 160 of the third embodiment, the input signal Vin from the vertical interpolation circuit 15 is input to the product-sum circuit 53 and the selector 62. The output signal of the selector 62 is input to the product-sum circuit 53 and the first 1H delay circuit 44, and the output signal of the 1H delay circuit 44 is input to the product-sum circuit 53 and the selector 62.

Next, the operation of the vertical LPF circuit 160 in the solid-state imaging device of Embodiment 3 configured as described above will be described with reference to FIG. FIG. 8 is a waveform diagram showing signals formed in the vertical LPF circuit 160 of the third embodiment.
The selector 62 in the vertical LPF circuit 160 selects and outputs either the input signal Vin from the vertical interpolation circuit 15 or the output signal V2 from the 1H delay circuit 44 in accordance with the control signal Vsel. By providing the selector 62 in this way, the selector 62 can output the 1H delay signal V1 delayed by one horizontal scanning line period (1H) with respect to the input signal Vin. The 1H delay circuit 44 connected to the selector 62 delays the input video signal by one horizontal scanning line period, and is a 2H delay signal further delayed by 1H with respect to the 1H delay signal V1 from the selector 62. V2 is output.
The product-sum circuit 53 of the third embodiment receives the input signal Vin, the 1H delay signal V1, and the 2H delay signal V2 as in the second embodiment, and performs multiplication and addition processing.

Next, an operation for generating the 1H delay signal V1 by the selector 62 in the third embodiment will be described.
The selector 62 is configured to select and output one of the two input signals according to the control signal Vsel. When the control signal Vsel is “H” (high level), the signal of the input terminal a is output. When the control signal Vsel is “L” (low level), the signal at the input terminal b is output. As shown in FIG. 8, the control signal Vsel is a signal that repeats “H” and “L” every horizontal scanning line period (1H). For example, in the horizontal scanning period (1) shown in FIG. 8, since the control signal Vsel is “H”, the input signal Vin is selected, and the selector 62 outputs the first line L1 to the product-sum circuit 53 as the output signal V1. Output. Since the output signal V1 of the selector 62 is also input to the 1H delay circuit 44, the output of the 1H delay circuit 44 is output after one horizontal scanning line period (1H), that is, in the horizontal scanning period (2) shown in FIG. The signal V2 becomes the first line L1.

  Since the control signal Vsel is “L” in the horizontal scanning period (2) shown in FIG. 8, the selector 62 selects the first line L1 that is the output signal of the 1H delay circuit 44 that is the signal of the input terminal b, and performs the product. Output to the sum circuit 53. At this time, since the output signal V1 of the selector 62 is also input to the 1H delay circuit 44, after one horizontal scanning line period (1H), that is, in the horizontal scanning period (3) shown in FIG. The signal V2 becomes the first line L1.

By repeating the above operation, as shown in FIG. 8, the output signal V1 from the selector 62 becomes a signal obtained by delaying the input signal Vin by one horizontal scanning line period as in the second embodiment.
Therefore, according to the third embodiment, by using one 1H delay circuit 44 and the selector 62 in the vertical LPF circuit 160, it is possible to realize the same operation as that of the vertical LPF circuit 16 of the above-described second embodiment. It becomes.

As described above, according to the solid-state imaging device of the third embodiment, the vertical direction corresponding to the 1/2 line accompanying the vertical pixel addition processing by the vertical interpolation circuit 15 with respect to the signal subjected to the vertical pixel addition processing in the solid-state imaging device. The vertical LPF circuit 160 can obtain a smooth image in the vertical direction, and can suppress an increase in circuit scale even when the sensitivity is increased.
In Embodiment 3 described above, the vertical LPF circuit 160 is described as having a multiplier and an adder. However, the present invention is not limited to this configuration, and is generally replaced with a multiplier. It goes without saying that the circuit configuration used is also included in the present invention. In particular, if the coefficient is fixed, the vertical LPF circuit can be configured by a bit shifter and an adder. Further, although the vertical LPF circuit 160 of the third embodiment is configured by an FIR filter circuit having three taps (coefficients: 1/4, 1/2, 1/4), the coefficients and the number of taps are the configuration of the apparatus used. Depending on the desired value.

<< Embodiment 4 >>
Next, a solid-state imaging device according to Embodiment 4 of the present invention will be described with reference to the drawings. FIG. 9 is a block diagram showing the configuration of the solid-state imaging device according to Embodiment 4 of the present invention. In FIG. 9, components having substantially the same functions and configurations as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted. The solid-state imaging device according to the fourth embodiment is a device in which a contour processing circuit 25 is provided instead of the contour enhancement circuit 23 in the solid-state imaging device according to the first embodiment.

FIG. 10 is a block diagram showing the configuration of the contour processing circuit 25 in the fourth embodiment.
The contour processing circuit 25 includes a vertical contour extraction circuit 31, a horizontal contour extraction circuit 32, two multipliers 33 and 34, an adder 35, and a sign inverter 36. The vertical contour extraction circuit 31 has two 1H delay circuits 45 and 46 and a product-sum circuit 55, and the product-sum circuit 55 has three multipliers 107, 108, 109 and an adder 116.

  The video signal Vin input to the contour processing circuit 25 is input to the product-sum circuit 55 via the first 1H delay circuit 45 of the vertical contour extraction circuit 31. The first 1H delay circuit 45 delays the input video signal by one horizontal scanning line period (1H). The 1H delay signal V1 that is the output signal of the first 1H delay circuit 45 is supplied to the product-sum circuit 55, the second 1H delay circuit 46, the horizontal contour extraction circuit 32, and the adder 35. The second 1H delay circuit 46 delays the input 1H delay signal V1 by 1H, and outputs a 2H delay signal V2 delayed by 2H with respect to the video signal Vin. The 2H delay signal V2 is supplied to the product-sum circuit 55.

As shown in FIG. 10, in the product-sum circuit 55, an input signal Vin, a 1H delay signal V1, and a 2H delay signal V2 are input, and each signal is multiplied by a predetermined coefficient and added. That is, in the product-sum circuit 55, the multiplier 107 multiplies the input signal Vin by the coefficient -1/4, the multiplier 108 multiplies the 1H delay signal V1 by the coefficient 1/2, and the multiplier 109 multiplies the 2H delay signal. V2 is multiplied by a coefficient -1/4. The signals thus multiplied are input to the adder 116 and added.
With the above processing, the output signal DV of the vertical contour extraction circuit 31 becomes a signal represented by the following equation (3).

  DV = -1 / 4 * Vin + 1/2 * V1-1 / 4 * V2 (3)

  The vertical contour extraction circuit 31 outputs a high frequency component corresponding to the vertical contour component shown in Expression (3). The output signal DV of the vertical contour extraction circuit 31 is multiplied by a vertical contour emphasis gain KV in a multiplier 33 and then input to a sign inverter (Sign) 36. The sign inverter 36 inverts the sign of the input signal according to the shooting mode at that time. The output signal from the sign inverter 36 is input to the adder 35.

The 1H delay signal V1 from the first 1H delay circuit 45 is input to the adder 35 and also to the horizontal contour extraction circuit 32. The horizontal contour extraction circuit 32 extracts only the horizontal contour component and outputs a horizontal contour signal DH to the multiplier 34. The multiplier 34 multiplies the horizontal contour signal DH by the horizontal contour enhancement gain KH and outputs the result to the adder 35.
As described above, the vertical contour signal (KV * DV), the 1H delay signal V1, and the horizontal contour signal (KH * DH) are input to the adder 35, added, and output.

Next, the operation of the solid-state imaging device according to Embodiment 4 configured as described above will be described.
As shown in FIG. 9, in the solid-state imaging device according to the fourth embodiment, the optical signal of the captured image from the solid-state imaging device 10 such as a CCD is transmitted via the preamplifier 12, the analog process circuit 13, and the A / D conversion circuit 14. And input to the vertical interpolation circuit 15. When the vertical pixel addition process is performed in the solid-state imaging device 10, as described above, the video signal output at that time has a video signal only for each horizontal scanning line period (1H). Therefore, as described in the previous embodiments, the vertical interpolation circuit 15 is also provided in the fourth embodiment, and the same video signal is output twice in succession so that the video signal exists in each line. Has been.

  The output of the vertical interpolation circuit 15 is supplied to the digital process circuit 17, nonlinear processing such as gamma correction and knee correction is performed by the gamma knee circuit 22, and is input to the contour processing circuit 25. In the vertical contour extraction circuit 31 of the contour processing circuit 25, only the vertical contour component of the input video signal is extracted to form a vertical contour signal DV, and the vertical contour multiplied by the vertical contour emphasis gain KV in the multiplier 33. A signal (KV * DV) is formed.

  The vertical contour signal is input to the sign inverter 36, and the sign is inverted during the high-sensitivity imaging operation that is the high-sensitivity processing of the solid-state imaging device. That is, when the solid-state imaging device is operating in the high-sensitivity imaging mode using the vertical pixel addition process, the sign inversion instruction signal Vsign is input from the microcomputer (not shown) to the sign inverter 36. When the sign inversion instruction signal Vsign is input to the sign inverter 36, the sign of the vertical contour signal (KV * DV) is inverted and output to the adder 35. On the contrary, when the solid-state imaging device is in the normal photographing mode that is the normal sensitivity processing, that is, when the vertical pixel addition processing is not performed, the sign inversion instruction signal Vsign is not input to the sign inverter 36, and the sign inversion is not performed. Not done.

  As described above, in the solid-state imaging device according to the fourth embodiment, in the high-sensitivity imaging mode, the sign of the vertical contour signal (KV * DV) is inverted, and therefore the vertical contour signal (−KV *) is added to the adder 35. DV), 1H delay signal V1, and horizontal contour signal (KH * DH) are input and added. When attention is paid only to the vertical direction in the addition processing at this time, the output signal Vout of the adder 35 is expressed by the following equation (4).

Vout = V1-KV * DV
= V1-KV * (-1/4 * Vin + 1/2 * V1-1 / 4 * V2) (4)

  Here, for example, when considering the case of vertical contour emphasis gain KV = 1, equation (4) becomes the following equation (5).

Vout = V1-(-1/4 * Vin + 1/2 * V1-1 / 4 * V2)
= 1/4 * Vin + 1/2 * V1 + 1/4 * V2 (5)

  Therefore, the solid-state imaging device of the fourth embodiment has a vertical LPF characteristic of obtaining a smooth image in the vertical direction, like the solid-state imaging device of the second embodiment. That is, by subtracting the vertical contour signal (KV * DV) obtained by multiplying the output of the vertical contour extraction circuit 31 by a coefficient from the 1H delay signal V1, the solid-state imaging device of the fourth embodiment forms a smooth image in the vertical direction. The LPF effect is achieved.

  As described above, according to the solid-state imaging device of the fourth embodiment, the vertical direction corresponding to 1/2 line accompanying the vertical pixel addition processing by the vertical interpolation circuit 15 with respect to the signal subjected to the vertical pixel addition processing in the solid-state imaging device. Can be prevented, and the contour processing circuit 25 can obtain a smooth image in the vertical direction. In the fourth embodiment, the contour processing circuit 25 having both the functions of the vertical LPF circuit 16 and the contour emphasizing circuit 23 used in the second embodiment is provided, so that the 1H delay circuit having a large circuit scale can be reduced. The size of the apparatus can be reduced even when the sensitivity of the apparatus is increased.

In the fourth embodiment, the configuration using the multiplier in the vertical contour extraction circuit 31 has been described. However, the present invention is not limited to this configuration, and a circuit generally used in place of the multiplier. It goes without saying that the configuration is also included in the present invention. In particular, in the case of a fixed coefficient, the vertical contour extraction circuit can be configured using a bit shifter and an adder.
In addition, the vertical contour extraction circuit 31 of the fourth embodiment has been described with an example in which the FIR filter circuit has three taps (coefficients: 1/4, 1/2, 1/4). It can be set to a desired value depending on the configuration of the device used. In the high sensitivity shooting mode, the filter coefficient can be changed to a value different from that in the normal shooting mode.

Further, in the fourth embodiment, the example using the sign inverter 36 has been described. However, the same effect can be obtained by giving a negative numerical value as the vertical contour emphasis gain by the multiplier 33 instead of the sign inverter 36. Play. Furthermore, although the (-1- / 4, 1/2, -1/4) 3-tap FIR circuit is configured as the vertical contour extraction circuit 31, the coefficient and the number of taps may be other numerical values.
In the fourth embodiment, an example in which a vertical filter circuit is configured by the vertical contour extraction circuit 31 and the multiplier 33 has been described. However, a vertical filter circuit including these circuits as one circuit can be used. In this case, in the high-sensitivity imaging mode, the same effect as in the fourth embodiment can be obtained even if the filter coefficient is changed to operate as a vertical LPF (vertical low-pass filter).

As described above, the solid-state imaging device according to the present invention has the following effects as is apparent from the detailed description of the embodiment.
According to the present invention, in the high-sensitivity shooting mode by the vertical pixel addition process, it is possible to prevent a vertical image shift due to the vertical pixel addition process with a simple configuration compared to the conventional solid-state imaging device. A solid-state imaging device having an effect can be provided.
In addition, according to the solid-state imaging device of the present invention, it is possible to provide a smooth image in the vertical signal component.
In the solid-state imaging device of the present invention, vertical smoothing can be achieved without increasing the circuit scale.
Furthermore, in the solid-state imaging device according to the present invention, by providing the contour processing circuit as the vertical smoothing means in the high-sensitivity photographing mode, it is possible to reduce the one horizontal scanning line period delay circuit having a large circuit scale. It is possible to provide a small solid-state imaging device that does not require a memory capacity.

  The present invention is useful in equipment that handles video signals, particularly in video cameras and camera devices.

It is a block diagram which shows the structure of the solid-state imaging device of Embodiment 1 which concerns on this invention. 2 is a block diagram illustrating a configuration of a vertical interpolation circuit in the solid-state imaging device according to Embodiment 1. FIG. It is a wave form diagram which shows the signal produced | generated in the vertical interpolation circuit of FIG. It is a block diagram which shows the structure of the solid-state imaging device of Embodiment 2 which concerns on this invention. 6 is a block diagram illustrating a configuration of a vertical LPF circuit in the solid-state imaging device according to Embodiment 2. FIG. FIG. 6 is a waveform diagram showing signals generated in the vertical LPF circuit of FIG. 5. It is a block diagram which shows the structure of the vertical LPF circuit in the solid-state imaging device of Embodiment 3 which concerns on this invention. It is a wave form diagram which shows the signal produced | generated in the vertical LPF circuit of FIG. It is a block diagram which shows the structure of the solid-state imaging device of Embodiment 4 which concerns on this invention. FIG. 10 is a block diagram illustrating a configuration of a contour processing circuit in a solid-state imaging device according to a fourth embodiment. It is a block diagram which shows the structure of the conventional solid-state imaging device. It is a block diagram which shows the structure of the vertical interpolation circuit in the conventional solid-state imaging device. It is a wave form diagram which shows the signal produced | generated in the vertical interpolation circuit in the conventional solid-state imaging device. It is a block diagram which shows the structure of the outline emphasis circuit in the conventional solid-state imaging device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Solid-state image sensor 11 CCD drive circuit 12 Preamplifier 13 Analog process circuit 14 A / D conversion circuit 15 Vertical interpolation circuit 16 Vertical LPF circuit 17 Digital process circuit 18 D / A conversion circuit 19 P / S conversion circuit 22 Gamma knee circuit 23 Outline emphasis Circuit 24 Matrix conversion circuit 31 Vertical contour extraction circuit 32 Horizontal contour extraction circuit 36 Sign inverter 41, 42, 43, 44, 45, 46 1 Horizontal scanning line period delay circuit 53 Multiply-add circuit 61, 62 Selector

Claims (2)

In a solid-state imaging device including a solid-state imaging device composed of a plurality of photoelectric conversion elements arranged in a two-dimensional matrix,
Vertical pixel addition command means for adding signal charges of a plurality of pixels in the vertical direction to the solid-state imaging device;
A vertical interpolation circuit for outputting a video signal subjected to addition processing of the solid-state imaging device for each horizontal scanning line period;
A contour processing circuit having a vertical contour extraction circuit and an arithmetic circuit,
The vertical interpolation circuit outputs one horizontal scanning line period delay signal obtained by delaying a video signal subjected to vertical pixel addition processing by one horizontal scanning line period;
A selector that receives the video signal and the one horizontal scanning line period delay signal and selects and outputs one of the signals based on a control signal that is switched every horizontal scanning line period;
The vertical contour extraction circuit is configured to output a vertical contour signal obtained by extracting a contour component of a vertical image from an input signal to the contour processing circuit,
The arithmetic circuit is configured to subtract an output signal of the vertical contour extraction circuit from an input signal of the contour processing circuit when performing vertical pixel addition processing in the solid-state image sensor, and performs vertical pixel addition processing in the solid-state image sensor. A solid-state imaging device configured to add an output signal of the vertical contour extraction circuit to an input signal of the contour processing circuit when not performed. In a solid-state imaging device including a solid-state imaging device composed of a plurality of photoelectric conversion elements arranged in a two-dimensional matrix,
Vertical pixel addition command means for adding signal charges of a plurality of pixels in the vertical direction to the solid-state imaging device;
A vertical interpolation circuit for outputting a video signal subjected to addition processing of the solid-state imaging device for each horizontal scanning line period;
A contour processing circuit having a vertical contour extraction circuit, a sign inversion circuit, and an addition circuit;
The vertical interpolation circuit outputs one horizontal scanning line period delay signal obtained by delaying a video signal subjected to vertical pixel addition processing by one horizontal scanning line period;
A selector that receives the video signal and the one horizontal scanning line period delay signal and selects and outputs one of the signals based on a control signal that is switched every horizontal scanning line period;
The vertical contour extraction circuit is configured to output a vertical contour signal obtained by extracting a contour component of a vertical image from an input signal to the contour processing circuit,
The sign inversion circuit is configured to invert the sign of the output signal of the vertical contour extraction circuit when performing vertical pixel addition processing in a solid-state imaging device,
The solid-state imaging device configured to add the output signal of the sign inverting circuit to the input signal to the contour processing circuit.

Images