JP2007312370A - Block noise removal device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a block noise removing device that permits removal of noise at the block boundary portion without degrading the image quality. <P>SOLUTION: The block noise removing device accumulates an interpixel differential values to obtain a result of the accumulation as a block noise value. Then the block noise removing device discriminates a largest block noise value from each of the block noise values, generates a block boundary position signal for representing a pixel position in a pixel group corresponding to the largest block noise value as a block boundary position, and discriminates a block noise value which is greater between block noise values respectively corresponding to pixels adjacent to both sides of the pixel corresponding to the largest block noise value as a phase error block noise value. Further, the block noise removing device generates a phase error signal on the basis of a ratio of a concerned phase error block noise to the largest block noise value and executes a block noise removing process on the basis of phase correction pixel sample value for applying a phase correction process based on the phase error signal to a decoded video signal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a block noise removing apparatus that removes block noise generated when information data compression-coded for a plurality of blocks is decoded.

  Currently, in order to reduce the amount of information when a video or audio signal is transmitted or recorded, compression coding employing an MPEG (Moving Picture Expert Group) system is being implemented. In such MPEG encoding processing, a discrete cosine transformation (hereinafter referred to as DCT) is performed on a video signal for each two-dimensional unit block to convert it into DCT coefficients for each frequency domain, and then quantization processing is performed. By doing so, the amount of information is reduced. At this time, the larger the quantization step used in the quantization process is, the larger the compression ratio is, but a part of the values are discarded, and quantization noise is generated. A typical example of such quantization noise is block noise. That is, in the MPEG encoding process, various processes are performed for each two-dimensional unit block as described above, and therefore, when this is decoded, a block boundary appears. As a video signal, a luminance signal and a color difference signal are usually compressed, but various signal formats such as an RGB signal are conceivable.

  Therefore, a method has been proposed in which such block noise is detected and removed from the video signal after MPEG decoding (see Patent Document 1). In such a block noise elimination method, first, a difference is obtained between pixels adjacent in the horizontal direction to a video signal after MPEG decoding, and when the difference value is larger than a predetermined threshold, the location is a block boundary. (Refer to FIG. 3A to FIG. 3C of Patent Document 1). Then, by applying a filtering process to the block boundary portion, a steep level change between adjacent blocks causing block noise is smoothed, and block noise reduction is realized.

  However, as shown in FIG. 1, the difference between adjacent pixels is always other than 0 for a video signal representing a picture in which the level of the video signal gradually increases (or decreases) in the horizontal direction within one block. Therefore, there is a risk that this portion is erroneously determined to be a block boundary.

In addition, there is a problem in that the block boundary cannot be detected correctly because the block boundary is blurred in the video signal whose resolution has been resized or analogized after MPEG decoding. .
JP 2000-50275 A

  The present invention has been made to solve such a problem. Image quality can be improved even for a video signal that has been analogized or resized after being compression-encoded and decoded in units of two-dimensional pixel blocks. It is an object of the present invention to provide a block noise removing device capable of removing noise at a block boundary without lowering.

  The block noise removing apparatus according to claim 1 is a block noise removing apparatus for removing block noise from a decoded video signal encoded and decoded for each pixel block composed of a plurality of pixels. Inter-pixel difference value calculating means for obtaining a difference value between adjacent pixels in the video signal as an inter-pixel difference value, and a block size N (N is an integer) of the block of the decoded video signal or an integer multiple of the block size N The inter-pixel difference value is divided for each pixel group in units of M, and the pixels corresponding to the first to Nth pixels or the first to Mth pixels respectively arranged in each of the pixel groups. The results obtained by accumulating the inter-pixel difference values among the n-th (n: 1 to N or 1 to M) arranged in each of the pixel groups are respectively the first to Nth blocks. Accumulating means for obtaining noise values or first to Mth block noise values, and determining a maximum block noise value from each of the first to Nth block noise values or the first to Mth block noise values. A block boundary position signal indicating a pixel position in the pixel group corresponding to the maximum block noise value as a block boundary position is generated, and corresponding to pixels adjacent to both sides of the pixel corresponding to the maximum block noise value. A block boundary detecting means for determining a larger one of the block noise values as a phase error block noise value and generating a phase error signal based on a ratio between the phase error block noise value and the maximum block noise value; A phase correction pixel sample value obtained by performing phase correction processing on the decoded video signal based on the phase error signal is detected. A correction means, and means for generating a noise removal image signal by performing block noise removal processing based on the phase correction pixel sample value.

  5. The block noise removing apparatus according to claim 4, wherein the block noise removing apparatus removes block noise from a decoded video signal encoded and decoded for each pixel block including a plurality of pixels. An inter-pixel difference value calculating means for obtaining a difference value between adjacent pixels in a video signal as an inter-pixel difference value, a block size N (N is an integer) of a block of the decoded video signal, and an estimation in the decoded video signal The difference value between pixels is divided for each pixel group in units of M, which is a common multiple of the resized block size L, and corresponds to each of the first to Mth pixels arranged in each of the pixel groups. The results of accumulating the inter-pixel difference values in the n-th (n: 1 to M) arranged in each of the pixel groups are respectively the first to M-th blocks. Accumulating means for obtaining a noise value, period determining means for determining whether the period of the first to M-th block noise values is N or L, and the first to N-th block noise values or the first A maximum block noise value is determined from each of the Mth block noise values, and a block boundary position signal indicating a pixel position in the pixel group corresponding to the maximum block noise value as a block boundary position is generated. A larger one of the block noise values corresponding to pixels adjacent to both sides of the pixel corresponding to the maximum block noise value is determined as a phase error block noise value, and the phase error block noise value and the maximum block noise value are determined. Block boundary detecting means for generating a phase error signal based on the ratio of the phase error signal to the decoded video signal based on the phase error signal. A phase correction unit that detects a phase correction pixel sample value that has been subjected to phase correction processing, and noise removal by performing block noise removal processing based on the phase correction pixel sample value and the period detected by the period determination unit And a means for generating a video signal.

  The block noise removing apparatus according to claim 7 is a decoded video signal including N (horizontal direction) × N (vertical direction) pixels encoded and decoded for each pixel block including a plurality of pixels. A block noise removing apparatus that removes block noise from a resized decoded video signal obtained by resizing the resolution of the decoded video signal by a factor of Q, the pixels adjacent to each other in the decoded video signal or the resized decoded video signal The inter-pixel difference value calculating means for obtaining the difference value between the pixels as a difference value between the pixels, and M pixels (M: N · Q and N) arranged adjacent to each other in the horizontal direction or the vertical direction. The unit block noise value corresponding to each of the first to Mth pixels arranged in each pixel group is divided into pixel groups each having a common multiple) pixel. Accumulating means for accumulating the n-th (n: 1 to M) elements arranged in the pixel groups as first to M-th block noise values, respectively; The result of accumulating the block noise values among those assigned with the same label to each of the first to M-th block noise values periodically and repeatedly assigned to each of the first to M-th block noise values. Respectively, and a maximum convolution block noise value is determined from each of the first to Nth convolution block noise values, and the maximum convolution block noise is determined. Generating a first block boundary position signal indicating a pixel position corresponding to the value as a block boundary position, and the tatami mat corresponding to pixels adjacent to both sides of the pixel corresponding to the maximum convolution block noise value. The larger one of the block noise values is determined as a phase error convolution block noise value, and a first phase error signal is generated based on the ratio between the phase error convolution block noise value and the maximum convolution block noise value. First block boundary detecting means for determining a maximum block noise value from each of the first to Mth block noise values and indicating a pixel position corresponding to the maximum block noise value as a block boundary position A position signal is generated, and a larger one of the block noise values corresponding to pixels adjacent to both sides of the pixel corresponding to the maximum block noise value is determined as a phase error block noise value, and the phase error block Second block boundary detecting means for generating a second phase error signal based on a ratio between a noise value and the maximum block noise value; , One of the first phase error signal and the second phase error signal is selected and output as a phase error signal, and one of the first block boundary position signal and the second block boundary position signal is output. Selecting means for selecting one and outputting it as a block boundary position signal; and applying the phase correction processing based on the phase error signal to the decoded video signal or the resized decoded video signal, and then the block boundary position Means for generating a noise-removed video signal by performing block noise removal processing based on the signal.

  In the present invention, first, the inter-pixel difference value is divided for each pixel group in units of M, which is a block size N (N is an integer) of the block of the decoded video signal or an integer multiple of the block size N. The inter-pixel difference value corresponding to each of the 1st to Nth or 1st to Mth pixels arranged in the nth (n: 1 to N or 1 to M) in each pixel group. ) Are accumulated as the first to Nth block noise values or the first to Mth block noise values, respectively. Next, the maximum block noise value is determined from each of the first to Nth block noise values or the first to Mth block noise values, and the pixel position in the pixel group corresponding to the maximum block noise value is determined as a block boundary. A block boundary position signal indicated as a position is generated, and the larger one of the block noise values corresponding to the pixels adjacent to both sides of the pixel corresponding to the maximum block noise value is determined as the phase error block noise value. Then, a phase correction pixel sample value obtained by generating a phase error signal based on a ratio between the phase error block noise value and the maximum block noise value and performing a phase correction process based on the phase error signal on the decoded video signal Block noise removal processing is performed based on the above.

  According to such a configuration, even for a video signal in which the level difference between adjacent blocks becomes large or a video signal whose resolution has been resized after decoding, block noise is reliably generated without degrading the display image quality. It can be removed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 2 is a diagram showing a configuration of a block noise removing apparatus according to the present invention.

  As shown in FIG. 2, the block noise removing apparatus removes block noise generated in the input video signal according to a detection unit 100 that detects block noise from the input video signal and the block noise detection result. And removal unit 200.

  The detection unit 100 includes a primary differentiation circuit 1, a median filter 2, a difference absolute value calculation circuit 3, a 32-pixel cycle accumulation circuit 4, an 8-pixel cycle convolution circuit 5, a first block boundary detection circuit 7, a selector 8, a second It comprises a block boundary detection circuit 9 and a comparator 10.

  The primary differentiating circuit 1 obtains a difference value between adjacent pixels as a difference value between pixels with respect to a signal level corresponding to each pixel in an input video signal, and a pixel composed of a series of inter-pixel difference values for each pixel. The inter-difference value series DFT is supplied to the median filter 2 and the difference absolute value calculation circuit 3.

  The input video signal is a signal obtained by MPEG decoding a video signal compression-coded for each two-dimensional pixel block of 8 pixels (horizontal direction) × 8 pixels (vertical direction) by an MPEG encoder. It is. At this time, the luminance signal is compressed and encoded for each pixel block of 8 pixels (horizontal direction) × 8 pixels (vertical direction), and decoded into a decoded signal of 8 pixels (horizontal direction) × 8 pixels (vertical direction). Is done. However, since the color difference signal is handled as a signal amount that is ¼ of the luminance signal, it is compressed and encoded for each pixel block of 8 pixels (horizontal direction) × 8 pixels (vertical direction), and 16 pixels (horizontal direction) × It is decoded into a decoded signal of 16 pixels (vertical direction). Here, there are various resolutions of the input video signal such as [720 × 480 pixels], [1440 × 1080 pixels], [1920 × 1080 pixels], etc., but after MPEG decoding, the tuner converts the resolution according to the resolution of the display device There are things to do. This is called resizing. In this specification, the input video signal is resized to [1920 × 1080 pixels] whose resolution after MPEG decoding is [1440 × 1080 pixels] or whose horizontal resolution is 1.33 times after MPEG decoding. A resized video signal will be described as an example. There are various actual resolutions of the input video signal as described above, and various resizing may be considered in the future.

  The median filter 2 performs a statistical process for obtaining a median value for each of three consecutive inter-pixel difference values (or every third consecutive inter-pixel difference value) in the inter-pixel difference value series DFT. The median value M2 obtained by the operation is supplied to the difference absolute value calculation circuit 3.

  The difference absolute value calculation circuit 3 supplies the absolute value of the difference between each pixel difference value in the inter-pixel difference value series DFT and the median value M2 to the 32-pixel cycle accumulation circuit 4 as a unit block noise value ABS. .

  The operations of the primary differentiation circuit 1, the median filter 2, and the difference absolute value calculation circuit 3 will be described below with reference to FIGS. 3 (a) to 3 (c).

  FIG. 3A is a diagram showing an example of an input video signal before and after a block boundary when a block boundary exists, and an inter-pixel difference value series DFT, a median value M2, and a unit block noise value ABS obtained at this time. It is.

  According to the input video signal shown in FIG. 3A, the inter-pixel difference value series DFT becomes a value other than 0 at only one point in the block boundary, and becomes 0 in all other parts. The median value M2 of three consecutive inter-pixel difference values in the inter-difference value series DFT series is always 0. Therefore, at this time, the absolute value of the difference between the inter-pixel difference value and the median value M2 in the inter-pixel difference value series DFT, that is, the unit block noise value ABS has a value other than 0 only at the block boundary portion.

  On the other hand, FIG. 3B shows an example of an input video signal in which the block boundary does not exist and the signal level gradually increases, and the inter-pixel difference value series DFT, median value M2, and unit block noise obtained at this time. It is a figure showing value ABS.

According to the input video signal whose level changes in a slope shape as shown in FIG. 3B, the inter-pixel difference value series DFT is always a value other than 0. During this time, the inter-pixel difference value series DFT series is continuous. The median value among the three inter-pixel difference values is the same as the inter-pixel difference value in the inter-pixel difference value series DFT. Therefore, at this time, the absolute value of the difference between the inter-pixel difference value series DFT and the median value M2 _n , that is, the unit block noise value ABS is zero. Therefore, even when an input video signal whose level changes in a slope shape is supplied, a unit block noise value ABS that does not erroneously determine the slope portion as a block boundary portion is obtained.

  FIG. 3C shows an input video signal that has been analogized or resized before and after the block boundary when a block boundary exists, and the inter-pixel difference value series DFT, median value M2, and unit block noise value ABS obtained at this time. FIG.

  As shown in FIG. 3C, the analog or resized input video signal may have a smooth block boundary, that is, a blurred state. For such an input video signal, the median filter 2 should extract every third consecutive inter-pixel difference value from the inter-pixel difference value series DFT, and obtain the median value from the three inter-pixel difference values. The median value M2 obtained by performing the statistical processing is supplied to the difference absolute value calculation circuit 3. Therefore, even for an input video signal in which the block boundary is blurred due to analogization or resizing, as shown in FIG. 3C, the unit becomes a value other than 0 only at the block boundary. A block noise value ABS can be generated.

  Based on the unit block noise value ABS, the 32-pixel cycle accumulation circuit 4 performs the following accumulation addition calculation process.

  First, the 32 pixel period accumulating circuit 4 includes 32 pixels G, each of which is adjacent to each other in the horizontal direction (or vertical direction), as shown in FIG. The pixel position labels L1 to L32 are assigned to the pixel groups corresponding to the pixel positions in the pixel group. Next, for each pixel position label L, the 32-pixel cycle accumulation circuit 4 performs the unit block noise value corresponding to the pixel arranged at the pixel position in the pixel group indicated by the pixel position label L. Accumulate the ABS value over one screen. Then, the 32-pixel cycle accumulation circuit 4 generates the accumulation results obtained for the pixel position labels L1 to L32 as the block noise values SUM1 to SUM32.

  That is, in the input video signal obtained by compressing and decoding each block composed of 8 pixels (horizontal direction) × 8 pixels (vertical direction), block noise appears every 8 pixel periods. On the other hand, in the input video signal resized to a resolution [1920 pixels] of 1.33 times the resolution in the horizontal direction of the video signal having the resolution [1440 × 1080 pixels] obtained by compression coding and decoding for each block, Block noise appears every (8 × 1.33) pixel period, that is, approximately every 10.67 pixel periods.

  Therefore, the 32-pixel cycle accumulation circuit 4 can detect the block boundary position that causes block noise for both the unsized video signal and the resized video signal whose resolution is resized 1.33 times. Therefore, the block noise values SUM1 to SUM32 are obtained by accumulating the unit block noise value ABS every 32 pixel periods, which is the least common multiple of 8 pixels and (8 pixels × 1.33) pixels. In short, in the 32-pixel cycle accumulation circuit 4, both the video signal obtained by encoding and decoding for each two-dimensional pixel block composed of N × N pixels and the resized video signal whose resolution is resized Q times. Thus, the unit block noise values are accumulated every M pixel periods, which is the least common multiple of N and (N · Q), to obtain the first to Mth block noise values (SUM1 to SUM32).

  The 8-pixel periodic convolution circuit 5 periodically assigns each of these TL1 to TL8 to each of the block noise values SUM1 to SUM32 as shown in FIG. 5 in the order of the pixel position labels TL1 to TL8. Then, for each pixel position label TL, the 8-pixel periodic convolution circuit 5 accumulates each block noise value SUM to which the pixel position label TL is assigned, and accumulates each of these pixel position labels TL1 to TL8. The calculation result is supplied to the first block boundary detection circuit 7 as new block noise values SUME1 to SUME8.

The first block boundary detection circuit 7, first, to determine what the maximum among the block noise values SUME1~SUME8 each and this is the maximum block noise value SUME _MAX. Next, the first block boundary detection circuit 7 has a large block noise value SUME corresponding to each pixel position label TL adjacent to both sides of the pixel position label TL assigned to this maximum block noise value SUME _MAX. Is the phase error block noise value SUME _FE . Next, the first block boundary detection circuit 7 is the largest among the block noise values SUME 1 to 8 except those corresponding to the maximum block noise value SUME _MAX and the phase error block noise value SUME _FE. And the difference from the maximum block noise value SUME _MAX is obtained and supplied to the comparator 10 as a non-resized boundary determination value BD1. Next, the first block boundary detection circuit 7 determines whether or not the non-resized boundary determination value BD1 is larger than a predetermined threshold value S1. Here, if it is determined that the pixel value is large, the first block boundary detection circuit 7 uses the pixel position indicated by the pixel position label TL in the maximum block noise value SUMAX _MAX as a reference for each pixel position for every eight pixel periods. Is a block boundary position, and a block boundary position signal BL1 indicating the block boundary position is supplied to the selector 8. Next, the first block boundary detection circuit 7 has a polarity corresponding to the direction of the pixel position label TL in the phase error block noise value SUME _{FE with} respect to the pixel position label TL in the maximum block noise value SUME _MAX , and A phase error signal P 1 having a value corresponding to the ratio of the phase error block noise value SUME _{FE to} the noise value SUME _MAX is generated and supplied to the selector 8.

The pixel position at the maximum block noise value SUME _MAX is TL _MAX and the pixel position at the phase error block noise value SUME _FE is TL _FE . Adjacent pixel positions change by one unit. Here, when the pixel position TL _MAX is located on the left side of the pixel position TL _FE and when the pixel position TL _MAX is located on the right side of the pixel position TL _FE , the operation in each case will be described with reference to FIGS. This will be described with reference to (b).

(A) When the pixel position TL _MAX is located on the left side of the pixel position TL _FE When the pixel position TL _MAX is located on the “−” side of the pixel position TL _FE , that is, on the left side as shown in FIG. The position BL1 is set as a pixel position TL _MAX . At this time, the block noise position TL _BL is a position where the pixel positions TL _MAX and TL _FE are proportionally distributed according to the ratio between the maximum block noise value SUME _MAX and the phase error block noise value SUME _FE . Therefore, the distance shifted from the block boundary position BL1 to the “+” side, that is, the right side as shown in FIG. 6A is the phase difference error signal P1 representing the phase error. That is, the phase difference error signal P1 is
P1 = SUME _FE / (SUME _MAX + SUME _FE ) …… Formula (1)
It is obtained by.

  At this time, 0 ≦ P <0.5.

This is because, when P is 0.5 or more, SUME _MAX <SUME _FE from equation (1), which is contrary to the definition.

(B) When the pixel position TL _MAX is positioned on the right side of the pixel position TL _FE When the pixel position TL _MAX is positioned on the “+” side of the pixel position TL _FE , that is, on the right side as shown in FIG. the position BL1 and the pixel position TL _FE. At this time, the block noise position TL _BL is a position where the pixel positions TL _MAX and TL _FE are proportionally distributed according to the ratio between the maximum block noise value SUME _MAX and the phase error block noise value SUME _FE . Therefore, the distance shifted from the block boundary position BL1 to the “+” side, that is, the right side as shown in FIG. 6B is the phase difference error signal P1 representing the phase error. That is, the phase difference error signal P1 is
P1 = SUME _MAX / (SUME _MAX + SUME _FE ) ...... Formula (2)
It is obtained by.

  At this time, 0.5 <P1 <1.

This is because, when P1 is 0.5 or less, SUME _MAX <SUME _FE from the above equation (2), which is contrary to the definition.

Note that the block boundary position BL1, which is the reference for the phase error signal P1, is set to the position on the “−” side of the pixel position TL _MAX and the pixel position TL _FE , that is, the position on the left side for mere calculation convenience. is there. The block noise position TL _BL in consideration of the phase error signal P1 is obtained by the following calculation.

TL _BL = (TL _MAX · SUME _MAX + TL _FE · SUME _FE ) / (SUME _MAX + SUME _FE ) …… Formula (3)
If it is determined that the non-resized boundary determination value BD1 is smaller than the predetermined threshold S1, the first block boundary detection circuit 7 determines that there is no block boundary and sets BD1 to “0”. This is supplied to the comparator 10.

Second block boundary detection circuit 9 first determines the maximum block noise value SUM from among the block noise values SUM1~32 each this is the maximum block noise value SUM _MAX. Next, the second block boundary detection circuit 9 increases the block noise value SUM corresponding to each pixel position label L adjacent to both sides of the pixel position label L assigned to the maximum block noise value SUM _MAX. This is the phase error block noise value SUM _FE . In addition, the second block boundary detection circuit 9 is one block size resized from the position of the maximum block noise value SUM _MAX , that is, 10 pixels or 11 pixels away, and 2 block sizes, ie 21 pixels or 22 pixels away. detecting the maximum block noise value to the maximum block noise value and the third to the second respective position, they each second maximum block noise value SUM _MAX2, and third maximum block noise value SUM _MAX3. At this time, the larger one of the block noise values SUM corresponding to the pixel position labels L adjacent to both sides of the pixel position label L assigned to the second maximum block noise value and the third block noise value, respectively. The second phase error block noise value SUM _FE2 and the third phase error block noise value SUM _{FE3 are} assumed. Next, the second block boundary detection circuit 9, the maximum block noise value SUM _MAX among the block noise values SUM1～32, second maximum block noise value SUM _MAX2, third maximum block noise value SUM _MAX3 and a phase error block The maximum value of the noise value SUM _FE , the second phase error block noise value SUM _FE2 , and the third phase error block noise value SUM _FE3 are omitted, and the maximum block noise value SUM _MAX The difference is obtained and supplied to the comparator 10 as a resizing boundary judgment value BD2. Next, the second block boundary detection circuit 9 determines whether or not the resizing boundary determination value BD2 is larger than the predetermined threshold value S2. Here, if it is determined that the pixel value is large, the second block boundary detection circuit 9 uses the pixel position indicated by the pixel position label L in the maximum block noise value SUM _MAX as a reference for each pixel position for each 10.67 pixel period. Is a block boundary position, and a block boundary position signal BL2 indicating the block boundary position is supplied to the selector 8. Next, the second block boundary detection circuit 9 has a polarity corresponding to the direction of the pixel position label L in the phase error block noise value SUM _{FE with} respect to the pixel position label L in the maximum block noise value SUM _MAX , and A phase error signal P 2 having a value corresponding to the ratio of the phase error block noise value SUM _{FE to} the noise value SUM _MAX is generated and supplied to the selector 8. A specific calculation method of the block boundary position signal BL2 is as follows, similarly to the above-described block boundary position signal BL1.

The pixel position in the maximum block noise value SUM _MAX T _MAX, the pixel position in the phase error block noise value SUM _FE and T _FE. When the pixel position T _MAX is located on the “−” side of the pixel position T _FE , that is, on the left side, the block boundary position BL 2 is the pixel position T _MAX . At this time, the block noise position T _BL is a position where the pixel position T _MAX and the pixel position TL _FE are proportionally distributed according to the ratio of the maximum block noise value SUM _MAX and the phase error block noise value SUM _FE . Accordingly, the distance from the block boundary position BL2 to the “+” side, that is, the right side is obtained as follows and is used as the phase difference error signal P2.

P2 = SUM _FE / (SUM _MAX + SUM _FE ) (4)
On the other hand, when the pixel position T _MAX is located on the “+” side of the pixel position T _FE , that is, on the right side, the block boundary position BL 2 is the pixel position T _FE . At this time, the block noise position T _BL is a position where the pixel position T _MAX and the pixel position T _FE are proportionally distributed according to the ratio of the maximum block noise value SUM _MAX and the phase error block noise value SUM _FE . Accordingly, the distance from the block boundary position BL2 to the “+” side, that is, the right side is obtained as follows and is used as the phase difference error signal P2.

P2 = SUM _MAX / (SUM _MAX + SUM _FE ) (5)
Phase error signal P2 block noise position considering T _BL is determined by the following calculation.

T _BL = (T _MAX · SUM _MAX + T _FE · SUM _FE ) / (SUM _MAX + SUM _FE ) …… Equation (6)
Similarly, from the second maximum block noise value SUM _MAX2 , the second phase error block noise value SUM _FE2 , and the third maximum block noise value SUM _MAX2 , the third phase error block noise value SUM _FE2 , the block boundary position BL2 and the phase difference error are respectively obtained. The signal P2 is calculated. That is, the second block boundary detection circuit 9 detects three block boundaries arranged in a 10.67 pixel cycle from the block noise values SUM1 to 32, and calculates three block boundary positions BL2 and three phase difference error signals P2, respectively. To do. Also, one resized boundary determination value BD2 is calculated. At this time, when BD2 is smaller than S2, BD2 = 0 is supplied to the comparator 10.

  The comparator 10 compares the boundary determination value BD1 without resizing with the boundary determination value BD2 with resizing. As a result, when BD1 is larger than BD2, the comparator 10 supplies the boundary determination value BD1 with the first block boundary detection circuit 7. The selector 8 is supplied with a selection signal S for selecting the block boundary position signal BL1 and the phase error signal P1. On the other hand, when BD2 is larger than BD1, the comparator 10 generates a selection signal S for selecting the block boundary position signal BL2 and the phase error signal P2 supplied from the second block boundary detection circuit 9. This is supplied to the selector 8. When both BD1 and BD2 are “0”, it is determined that there is no block noise, and the removal unit 200 outputs a noise-removed video signal without removing the block noise.

  The selector 8 selects one of the block boundary position signals BL1 and BL2 according to the selection signal S, and supplies this to the removing unit 200 as a block boundary position signal BL representing the final block boundary position. . The selector 8 selects one of the phase error signals P1 and P2 according to the selection signal S and supplies it to the removing unit 200 as a phase error signal P representing the final phase error. However, if both the first block boundary detection circuit 7 and the second block boundary detection circuit 9 determine that there is no block boundary (that is, the boundary determination value BD1 is smaller than the predetermined threshold S1 and the boundary determination value BD2 is lower than the predetermined threshold S2). When it is small, the removal unit 200 outputs the input video signal as a noise-removed video signal without performing a block noise removal operation.

Hereinafter, with respect to the operation of the detection unit 100 configured as described above, an input video signal is a signal that has not been resized (digital or analog) and a signal that has undergone resizing processing (digital or analog). Explain each one.
(1) When the input video signal is a signal not subjected to resizing processing At this time, block noise is present in the input video signal obtained by decoding the video signal that has been compression-coded for each block of 8 × 8 pixels. If it exists, the noise peak appears every 8 pixel periods as shown in FIG. Therefore, first, the inter-pixel difference value (ABS) for each pixel is obtained by the primary differentiation circuit 1, the median filter 2, and the difference absolute value calculation circuit 3. Then, in the horizontal direction (or vertical direction) by the 32-pixel cycle accumulation circuit 4 and the 8-pixel cycle convolution circuit 5,
Pixels arranged in the (8n-7) th,
The (8n-6) th pixel arranged;
The (8n-5) th pixel arranged;
Pixels arranged in the (8n-4) th,
The (8n-3) th pixel arranged;
Pixels arranged in the (8n-2) th,
The (8n-1) th pixel arranged;
Pixels arranged in the (8n) th,
n: Natural number Block noise values SUME1 to SUME8 are generated by accumulating the inter-pixel difference values corresponding to the respective pixels over one screen. Here, the first block boundary detection circuit 7 determines the maximum value (SUME _MAX ) from among the block noise values SUME1 to 8, and corresponds to each pixel adjacent to both sides of the pixel corresponding to the SUME _MAX . The larger one of the block noise values SUME is a value (SUME _FE ) due to the influence of the phase error. For example, when the block noise values SUME1 to SUME8 for each of the (8n-7) th to (8n) th pixels are in the state shown in FIG. 7B, the block noise value SUME5 becomes SUME _MAX . The block noise value SUME4 becomes SUME _FE . At this time, if block noise is present, as shown in FIG. 7B, the SUME5 as the SUME _MAX is set to a predetermined threshold value with respect to any of the other block noise values SUME excluding the SUME4 as the SUME _FE. Increased by the amount exceeding S1. Therefore, the first block boundary detection circuit 7 calculates the difference between the largest SUME among the block noise values SUME 1 to 8 except for those corresponding to SUME _MAX and SUME _FE , and the SUME _MAX. This is obtained and used as a non-resized boundary judgment value (BD1). When the non-resizing boundary determination value BD1 is larger than the predetermined threshold S1, the first block boundary detection circuit 7 determines that a block boundary exists. Then, the first block boundary detection circuit 7 generates a block boundary position signal BL1 indicating the pixel position for every eight pixel periods with reference to the pixel position corresponding to SUME _MAX as the block boundary position. For example, in the case of FIG. 7B, the first block boundary detection circuit 7 indicates that the pixel corresponding to the block noise value SUME5, that is, the (8n-3) th pixel position is the block boundary position. A boundary position signal BL1 is generated.

Here, if the input video signal is an analog signal, the transition of the signal level at the block boundary becomes smooth and the block boundary position is blurred. Therefore, there may be a phase error when detecting the block boundary position. At this time, for example, as shown in FIG. 7B, the pixels adjacent to the pixel corresponding to the SUME _MAX are affected by the phase error, whereby each of the pixels adjacent to both sides of the pixel corresponding to the SUME _MAX The block noise value SUME corresponding to is a large value.

Therefore, as described above, the first block boundary detection circuit 7 determines the larger one of the block noise values SUME corresponding to the pixels adjacent to both sides of the pixel corresponding to the maximum block noise value SUME _MAX as the phase error block noise. Value (SUME _FE ). The pixel position at the maximum block noise value SUME _MAX is TL _MAX and the pixel position at the phase error block noise value SUME _FE is TL _FE. Based on the ratio of SUME _MAX and SUME _FE , the block noise position TL _BL is expressed by the above formula ( As shown in 3),
TL _BL = (TL _MAX / SUME _MAX + TL _FE / SUME _FE ) / (SUME _MAX + SUME _FE )
It is obtained at.

If there is no phase error, the pixel position TL _MAX corresponding to SUME _MAX is the block boundary position signal BL1 as described above, but if there is a phase error, the pixel position on the left side of the pixel position TL _MAX and the pixel position TL _FE Is generated as a block boundary position. For example, in the case of FIG. 7B, the first block boundary detection circuit 7 indicates that the pixel corresponding to the block noise value SUME4, that is, the (8n-4) th pixel position is the block boundary position. A boundary position signal BL1 is generated. The block noise position TL _BL is shifted to the “+” side, that is, the right side by a phase error signal P1 with reference to the boundary position signal BL1. The phase error signal P1 is represented by a distance when the shift of one pixel is “1”. The phase error signal P1 is as shown in the above equations (1), (2), FIGS. 6 (a), and 6 (b).
(2) When the input video signal is a resized signal In other words, the resolution of the compression signal and the decoded video signal for each 8 × 8 pixel block is changed from [1440 × 1080 pixels] to [1920 × 1080 pixels]. When block noise exists in the resized input video signal, a noise peak appears every [(8 × 1920) / 1440 pixels] period, that is, every 10.67 pixel periods as shown in FIG. Therefore, the second block boundary detection circuit 9 in the horizontal direction (or vertical direction)
The (32n-31) th pixel,
The (32n-30) -th arranged pixel,
The (32n-29) th pixel,
・
・
・
The (32n-1) th pixel arranged;
The (32n) th pixel,
n: Natural number For each, the following processing is executed based on block noise values SUM1 to SUM32 obtained by accumulating unit block noise values ABS corresponding to the pixels over one screen. First, the second block boundary detection circuit 9 determines the maximum value (SUM _MAX ) from the block noise values SUM1 to SUM32, and blocks corresponding to the pixels adjacent to both sides of the pixel corresponding to the SUM _MAX. The larger of the noise values SUM is defined as a phase error block noise value (SUM _FE ). Similarly, the second largest block noise value and the third largest block noise value SUM are determined from each of the block noise values SUM1 to SUM32, and these are determined as the second largest block noise value _SUMMAX2 , The maximum block noise value is SUM _MAX3 . The larger one of the block noise values SUM corresponding to the pixel position labels L adjacent to both sides of the pixel position label L assigned to the second maximum block noise value and the third block noise value is the second phase. The error block noise value SUM _FE2 and the third phase error block noise value SUM _{FE3 are} assumed. For example, in the case of FIG. 7C, the block noise value SUM5 becomes SUM _MAX , and the block noise value SUM4 becomes SUME _FE . Similarly, block noise value SUM26 is SUM _MAX2, block noise value SUM27 is SUME _FE2, block noise value SUM15 is SUM _MAX3, block noise value SUM16 is SUME _FE3. At this time, when the block noise is present, the maximum block noise value SUM _MAX among the block noise values SUM1～32, second maximum block noise value SUM _MAX2, third maximum block noise value SUM _MAX3 and a phase error block The maximum value of the noise value SUM _FE , the second phase error block noise value SUM _FE2 , and the third phase error block noise value SUM _FE3 are omitted, and the maximum block noise value SUM _MAX The difference is obtained and supplied to the comparator 10 as a resizing boundary judgment value BD2. As shown in FIG. 7 (c), SUM5 as SUM _MAX is, SUM SUM26 as _MAX2, SUM SUM15 as _MAX3, SUM SUM4 as _FE, SUM SUM27 as _FE2, other blocks except SUM16 as SUM _FE3 For any of the noise values SUM, the noise value SUM increases by the amount exceeding the predetermined threshold S2. Therefore, the second block boundary detection circuit 9 determines that the block boundary exists when the resizing boundary determination value BD2 is larger than the predetermined threshold value S2. Then, the second block boundary detection circuit 9 generates a block boundary position signal BL2 that indicates the pixel position for each 10.67 pixel period with the pixel position corresponding to SUM _MAX as the reference. That is, even if the video signal is compressed and decoded for each block of 8 × 8 pixels, if the resolution is resized from [1440 × 1080 pixels] to [1920 × 1080 pixels],
10.67 ≒ (8 × 1920) / 1440
From this formula, it is estimated that a block boundary appears every 10.67 pixel periods. Therefore, each pixel position for each 10.67 pixel period with the pixel position corresponding to the maximum value (SUM _MAXM ) as a reference is determined as the block boundary position.

  For example, in the case of FIG. 7 (c), the second block boundary detection circuit 9 detects the pixel corresponding to the block noise value SUM5, that is, each 10.67 pixel period based on the (32n−27) th pixel position. The block boundary position signal BL2 indicating the pixel position as the block boundary position is generated.

However, regardless of whether the input video signal is an analog signal or a digital signal, if the block period does not become an integer due to resizing, the block boundary position may be blurred, and thus there may be a phase error when detecting the block boundary position. At this time, for example, as shown in FIG. 7C, the pixel adjacent to the pixel corresponding to SUM _MAX is affected by the phase error, and accordingly, the pixels adjacent to both sides of the pixel corresponding to SUM _MAX The block noise value SUM corresponding to is a large value. Therefore, as described above, the second block boundary detection circuit 9 receives the larger one of the block noise values SUM corresponding to the pixels adjacent to both sides of the pixel corresponding to the maximum value SUM _MAX , due to the influence of the phase error. and the value (SUM _FE), it was so as to obtain a phase error component and (P2) based on the ratio of SUM _FE for such SUM _MAX. When there is a phase error, the pixel position on the left side of the pixel position TL _MAX and the pixel position TL _FE is set as the block boundary position signal BL1 as in the case where the input video signal is an analog signal that has not been resized. As described above, the block noise position TL _BL when there is a phase error is expressed by Expression (3). The phase error signal P2 at this time is also expressed by equations (4) and (5) as described above.

  As described above, the detection unit 100 includes the first block boundary detection circuit 7 that obtains the block boundary position (BL1) and the phase error value (P1) for the input video signal that has not been subjected to the resizing process, and the resizing process. The second block boundary detection circuit 9 for obtaining the block boundary position (BL2) and the phase error value (P2) for the input video signal subjected to is individually mounted. At this time, the non-resized boundary determination value (BD1) calculated by the first block boundary detection circuit 7 is compared with the resize boundary determination value (BD2) calculated by the second block boundary detection circuit 9, The block boundary position and the phase error value generated by the circuit (7 or 9) having the larger value are set as the final block boundary position (BL) and the phase error value (P).

That is, in both the first block boundary detection circuit 7 and the second block boundary detection circuit 9, the block noise value (SUME _MAX , SUM _MAX ) at the block boundary position and the block noise value at other pixel positions are calculated. The difference is calculated as a boundary judgment value (BD1, BD2). At this time, if BD1 is larger, it is determined that the input video signal has not been resized, and the block boundary position (BL1) and phase generated by the first block boundary detection circuit 7 are determined. The error value (P1) is supplied to the removal unit 200. On the other hand, when BD2 is larger, it is determined that the input video signal has been resized, and the block boundary position (BL2) generated by the second block boundary detection circuit 9 and the phase error are determined. The value (P2) is supplied to the removal unit 200.

  Therefore, according to the detection unit 100, even if a signal for identifying whether or not the input video signal is resized or analogized is not supplied, the form of the input video signal (with resizing or Block noise is detected by an optimum processing method corresponding to (no resizing). Further, the detection unit 100 detects the phase error in the input video signal because the input video signal is resized or analogized.

  The removal unit 200 performs block noise removal processing on the input video signal based on the block boundary position signal BL and the phase error signal P supplied from the detection unit 100 to generate a noise-removed video signal.

  FIG. 8 is a diagram illustrating an internal configuration of the removing unit 200.

  In FIG. 8, the flip-flop DF1 sequentially captures the input video signal for each pixel, and delays the input video signal by a period corresponding to one pixel and supplies it to the flip-flop DF2 and the mixers 201 and 202 as the pixel sample value D1. To do. The flip-flop DF2 supplies the pixel sample value D1 delayed by the period of one pixel to the flip-flop DF3 and the mixers 202 and 203 as the pixel sample value D2. The flip-flop DF3 supplies the pixel sample value D2 delayed by one pixel period to the flip-flop DF4 and the mixers 203 and 204 as the pixel sample value D3. The flip-flop DF4 supplies the pixel sample value D3 delayed by one pixel period to the flip-flop DF5 and the mixers 204 and 205 as the pixel sample value D4. The flip-flop DF5 supplies the pixel sample value D4 delayed by one pixel period to the flip-flop DF6 and the mixers 205 and 206 as the pixel sample value D5. The flip-flop DF6 supplies the pixel sample value D5 delayed by one pixel period to the flip-flop DF7 and the mixers 206 and 207 as the pixel sample value D6. The flip-flop DF7 supplies the pixel sample value D6 delayed by one pixel period to the flip-flop DF8 and the mixers 207 and 208 as the pixel sample value D7. The flip-flop DF8 supplies the pixel sample value D7 delayed by the period of one pixel to the mixer 208 as the pixel sample value D8.

  The configuration shown in FIG. 8 is based on the premise that a block boundary position exists between the pixel corresponding to the flip-flop DF4 and the pixel corresponding to the flip-flop DF5, or at the position of the pixel corresponding to the flip-flop DF4. . When there is a sampling phase error, the phase error is obtained from the surrounding difference values. This calculation method is described below.

The mixer 201 converts the pixel sample value D1 and the pixel sample value in the input video signal one pixel period before the pixel sample value D1 (hereinafter referred to as the pixel sample value D0) into the following based on the phase error signal P: The phase correction pixel sample value M1 whose phase is corrected by mixing at such a mixing ratio is supplied to the subtractor 209.
(A) When the pixel position TL _MAX is located on the left side of the pixel position TL _FE (0 ≦ P <0.5)
M1 = D1 · (P−1) + D0 · P
(B) When the pixel position TL _MAX is located on the right side of the pixel position TL _FE (0.5 <P <1)
M1 = D0
When obtaining M1 as shown in FIG. 9B1, since it is shifted to the right side of the block boundary and away from the block boundary (right side), it is not affected by block distortion. Therefore, M1 = D0. The same applies to the following.

The mixer 202 supplies the phase correction pixel sample value M2 whose phase is corrected by mixing the pixel sample values D1 and D2 with the following mixing ratio based on the phase error signal P to the subtracter 209.
(A) When the pixel position TL _MAX is located on the left side of the pixel position TL _FE (0 ≦ P <0.5)
M2 = D2 · (P−1) + D1 · P
(B) When the pixel position TL _MAX is located on the right side of the pixel position TL _FE (0.5 <P <1)
M2 = D1
The subtractor 209 shares the subtraction result obtained by subtracting the phase correction pixel sample value M1 from the phase correction pixel sample value M2 as the boundary peripheral difference value SB1 to the estimated boundary difference value calculation circuit 210.

The mixer 203 supplies, to the subtractor 211, the phase correction pixel sample value M3 whose phase is corrected by mixing the pixel sample values D2 and D3 with the following mixing ratio based on the phase error signal P.
(A) When the pixel position TL _MAX is located on the left side of the pixel position TL _FE (0 ≦ P <0.5)
M3 = D3 · (P−1) + D2 · P
(B) When the pixel position TL _MAX is located on the right side of the pixel position TL _FE (0.5 <P <1)
M3 = D2
The mixer 204 mixes the pixel sample values D3 and D4 with the following mixing ratio based on the phase error signal P to subtract the phase corrected pixel sample value M4 by the subtractor 211 and the averaging circuit 212, In addition, the boundary correction value calculation circuit 215 is supplied.
(A) When the pixel position TL _MAX is located on the left side of the pixel position TL _FE (0 ≦ P <0.5)
M4 = D4. (P-1) + D3.P
(B) When the pixel position TL _MAX is located on the right side of the pixel position TL _FE (0.5 <P <1)
M4 = D3
The subtractor 211 shares the subtraction result obtained by subtracting the phase correction pixel sample value M3 from the phase correction pixel sample value M4 as the boundary peripheral difference value SB2 to the estimated boundary difference value calculation circuit 210.

The mixer 205 mixes the pixel sample values D4 and D5 with the following mixing ratio based on the phase error signal P, and outputs the phase corrected pixel sample value M5 to the averaging circuit 212 and the subtractor 213. Supply.
(A) When the pixel position TL _MAX is located on the left side of the pixel position TL _FE (0 ≦ P <0.5)
M5 = D5
When obtaining M5 as shown in FIG. 9A1, since it is shifted to the left side of the block boundary and away from the block boundary (left side), it is not affected by block distortion. Therefore, M5 = D5. The same applies to the following.
(B) When the pixel position TL _MAX is located on the right side of the pixel position TL _FE (0.5 <P <1)
M5 = D5 · P + D4 · (P−1)
The mixer 206 supplies the phase-corrected pixel sample value M6, which is phase-corrected by mixing the pixel sample values D5 and D6 with the following mixing ratio based on the phase error signal P, to the subtractor 213.
(A) When the pixel position TL _MAX is located on the left side of the pixel position TL _FE (0 ≦ P <0.5)
M6 = D6
(B) When the pixel position TL _MAX is located on the right side of the pixel position TL _FE (0.5 <P <1)
M6 = D6 · P + D5 · (P-1)
The subtractor 213 shares the subtraction result obtained by subtracting the phase correction pixel sample value M5 from the phase correction pixel sample value M6 as the boundary peripheral difference value SB3 to the estimated boundary difference value calculation circuit 210.

The mixer 207 supplies the phase correction pixel sample value M7 whose phase is corrected by mixing the pixel sample values D6 and D7 with the following mixing ratio based on the phase error signal P to the subtractor 214.
(A) When the pixel position TL _MAX is located on the left side of the pixel position TL _FE (0 ≦ P <0.5)
M7 = D7
(B) When the pixel position TL _MAX is located on the right side of the pixel position TL _FE (0.5 <P <1)
M7 = D7 · P + D6 · (P-1)
The mixer 208 supplies the phase-corrected pixel sample value M8, which has been phase-corrected by mixing the pixel sample values D7 and D8 with the following mixing ratio based on the phase error signal P, to the subtracter 214.
(A) When the pixel position TL _MAX is located on the left side of the pixel position TL _FE (0 ≦ P <0.5)
M8 = D8
(B) When the pixel position TL _MAX is located on the right side of the pixel position TL _FE (0.5 <P <1)
M8 = D8 · P + D7 · (P-1)

The subtractor 214 shares the subtraction result obtained by subtracting the phase correction pixel sample value M7 from the phase correction pixel sample value M8 as the boundary peripheral difference value SB4 to the estimated boundary difference value calculation circuit 210.

  The estimated boundary difference value calculation circuit 210 performs the following interpolation calculation on the basis of the boundary peripheral difference values SB1 to SB4, and the block boundary portion that can be taken as a difference value between adjacent pixels in the block boundary portion after the block noise removal processing. The inter-pixel difference value is obtained and supplied to the boundary correction value calculation circuit 215 as the block boundary portion estimated difference value PRED.

PRED = {3 · (SB2 + SB3)-(SB1 + SB4)} / 4
The averaging circuit 212 is obtained by mixing the phase correction pixel sample value M4 obtained by mixing the pixel sample values D4 and D3 immediately after the block boundary position and the pixel sample values D5 and D6 immediately before the block boundary position. An average value of the obtained phase correction pixel sample value M5 is obtained. The average circuit 212 supplies the average value to the boundary correction value calculation circuit 215 as the midpoint value dCNT at the block boundary.

  The boundary correction value calculation circuit 215 calculates the block boundary correction value dCORR2 for the pixel sample value immediately after the block boundary position by the following calculation based on the phase correction pixel sample value M4, the block boundary portion estimated difference value PRED, and the midpoint value dCNT. , And a block boundary correction value dCORR1 for the immediately preceding pixel sample value is generated and supplied to the inter-boundary correction value interpolation circuit 216.

dCORR1 = {dCNT− (PRED / 2)} − M5
dCORR2 =-[dCNT + (PRED / 2)} + M4
However, the calculation of the block boundary correction values dCORR1 and dCORR2 is performed at the block boundary position between the pixel corresponding to the flip-flop DF4 and the pixel corresponding to the flip-flop DF5 in FIG. Is assumed to exist. Therefore, the block boundary position signal BL is input to the boundary correction value calculation circuit 215, and the block boundary position is set to the middle of the pixel corresponding to the flip-flop DF4 and the pixel corresponding to the flip-flop DF5, or the position of the pixel corresponding to the flip-flop DF4. The boundary correction value calculation circuit 215 outputs the block boundary correction values dCORR1 and dCORR2 to the inter-border correction value interpolation circuit 216 at the timing when.

  The inter-boundary correction value interpolation circuit 216 corresponds to the inter-block boundary, that is, each pixel position in the block by linear interpolation based on the block boundary correction values dCORR1 and dCORR2 generated at each block boundary portion of the continuous block. A block correction signal BZ indicating the level correction amount is generated and supplied to the adder 217. That is, the inter-boundary correction value interpolation circuit 216, for each block, generates a block boundary correction value dCORR2 (or dCORR1) generated at the left boundary portion of the block and a block boundary correction value dCORR1 (generated at the right boundary portion). Alternatively, a block correction signal BZ indicating a level correction amount corresponding to each pixel position in the block is generated by linear interpolation with dCORR2). The inter-boundary correction value interpolation circuit 216 receives the block correction signal BZ indicating the correction value 0 to the adder 217 when the block boundary position signal BL having a constant 0 level indicating that no block boundary exists is supplied. Supply.

  The delay circuit 218 includes the flip-flops DF1 to DF8, the mixers 201 to 208, the subtractors 209, 211, 213, and 214, the estimated boundary difference value calculation circuit 210, the average circuit 212, the boundary correction value calculation circuit 215, and the boundary The input video signal is supplied to the adder 217 after being delayed by a time corresponding to the total processing time by each of the correction value interpolation circuits 216.

  The adder 217 adds the block correction signal BZ to the level of the input video signal delayed by the delay circuit 218, thereby suppressing noise (steep level transition) at the block boundary portion. Generate and output a signal.

Hereinafter, the operation of the removing unit 200 will be described by taking as an example the case where an input video signal as shown in FIGS. 9A1 and 9B1 is supplied. In this case, FIG. 9 (A1) and FIG. 9 (A2), when the pixel position TL _MAX is positioned on the left side of the pixel position _{TL FE (0 ≦ P <0.5} ), FIG. 9 (B1) and FIG. 9 (B2) These are diagrams respectively corresponding to cases where the pixel position TL _MAX is located on the right side of the pixel position TL _FE (0.5 <P <1).

  FIGS. 9A1 and 9B1 show input video signals for nine consecutive pixels at the block boundary. At this time, each of the flip-flops DF1 to DF8 shown in FIG. 8 outputs pixel sample values D1 to D8 indicated by white circles in FIGS. 9A1 and 9B1, respectively. Therefore, the value of the input video signal supplied to the flip-flop DF1 at this time becomes the pixel sample value D0 shown in FIGS. 9A1 and 9B1.

  Here, first, among the pixel sample values D0 to D8, pixel sample values adjacent to each other are mixed at a mixing ratio corresponding to the phase error signal P supplied from the detection unit 100, thereby correcting the phase. The phase correction pixel sample values M1 to M8 series as shown in FIGS. 9A2 and 9B2 are generated.

  Next, as shown in FIGS. 9 (A2) and 9 (B2), the difference between the phase correction pixel sample values M5 and M6 immediately before the block boundary position is obtained as the boundary peripheral difference value SB3, and immediately after the block boundary position. A difference between the phase correction pixel sample values M3 and M4 is obtained as a boundary peripheral difference value SB2. Further, as shown in FIG. 9A2 and FIG. 9B2, the difference between the phase correction pixel sample values M1 and M2 immediately after the phase correction pixel sample values M3 and M4 is obtained as the boundary peripheral difference value SB1, and the phase correction is performed. A difference between the phase correction pixel sample values M7 and M8 immediately before the pixel sample values M5 and M6 is obtained as a boundary peripheral difference value SB4.

  Here, the estimated boundary difference value calculation circuit 210 performs the phase correction pixel sample value at the block boundary as shown in FIGS. 9A2 and 9B2 by the above interpolation calculation based on the boundary peripheral difference values SB1 to SB4. The difference value between the pixel sample value Q1 after the block noise removal process of M4 and the pixel sample value Q2 after the block noise removal process of the phase correction pixel sample value M5 is obtained as the block boundary portion estimated difference value PRED.

  First, the boundary correction value calculation circuit 215 is based on the midpoint value dCNT in the phase correction pixel sample values M4 and M5 at the block boundary portion and the block boundary portion estimated difference value PRED, as shown in FIGS. One of the pixel sample values Q1 and Q2 as shown in (B2), for example, Q1, is obtained as follows.

Q1 = {dCNT− (PRED / 2)}
Then, the boundary correction value calculation circuit 215 blocks the phase correction pixel sample value M5 by subtracting the phase correction pixel sample value M5 from the pixel sample value Q1, as shown in FIGS. 9A2 and 9B2. A boundary correction value dCORR1 is generated. Further, the boundary correction value calculation circuit 215 converts the block boundary correction value dCORR1 having the inverted polarity into a block boundary correction value for the phase correction pixel sample value M4 as shown in FIGS. 9A2 and 9B2. Generate as dCORR2.

  Here, the inter-boundary correction value interpolation circuit 216 performs linear interpolation for each block using the block boundary correction value dCORR generated at the left boundary portion of the block and the block boundary correction value dCORR generated at the right boundary portion. Thus, a block correction signal BZ indicating a level correction amount corresponding to each pixel position in the block is generated. For example, when an input video signal having a level transition as shown by a thick solid line in FIG. 10A is supplied, the inter-border correction value interpolation circuit 216 generates a block boundary correction generated at the boundary between the blocks 1 and 2. By linear interpolation based on the value dCORR2 and the block boundary correction value dCORR1 generated at the boundary between the blocks 2 and 3, it corresponds to each pixel position in the block 2 as shown by the thick solid line in FIG. A block correction signal BZ indicating the level correction amount is generated.

  Therefore, by applying level correction based on the block correction signal BZ to the input video signal, for example, a video signal as shown by a thick solid line in FIG. 10A in which the level difference between adjacent blocks becomes large. Thus, a noise-removed video signal as indicated by a thick broken line from which block noise has been removed without degrading the image quality is obtained.

It is a figure which shows an example of the video signal showing the design which the level of a video signal increases (or decreases) gradually in the horizontal direction within 1 block. It is a figure which shows the structure of the block noise removal apparatus by this invention. FIG. 5 is a diagram for explaining operations of a primary differentiating circuit 1, a median filter 2, and a difference absolute value calculation circuit 3. It is a figure which shows an example of the pixel position labels L1-L32 allocated corresponding to each pixel position for every 32 pixels arrange | positioned continuously. It is a figure which shows an example of pixel position label TL1-TL8 newly allocated to each of block noise value SUME1-32. 5 is a diagram for explaining an operation when obtaining a phase error signal P. FIG. FIG. 6 is a diagram for explaining the operation of a detection unit 100. It is a figure which shows the internal structure of the removal part 200 shown by FIG. It is a figure for demonstrating operation | movement of the mixers 201-208, the subtractors 209, 211, 213, and 214 shown in FIG. 8, the estimated boundary difference value calculation circuit 210, the average circuit 212, and the boundary correction value calculation circuit 215. FIG. 9 is a diagram for explaining the operation of the inter-border correction value interpolation circuit 216 shown in FIG. 8.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Primary differentiation circuit 2 Median filter 3 Difference absolute value circuit 4 32 pixel period accumulation circuit 5 8 pixel period convolution circuit 7 1st block boundary detection circuit 8 Selector 9 2nd block boundary detection circuit
10 Comparator
201-208 mixer
209,211,213,214 Subtractor
210 Estimated boundary difference calculation circuit
212 Average circuit
215 Boundary correction value calculation circuit
216 Interpolated correction value interpolation circuit
217 Adder

Claims (8)

A block noise removing apparatus for removing block noise from a decoded video signal encoded and decoded for each pixel block composed of a plurality of pixels,
An inter-pixel difference value calculating means for obtaining a difference value between adjacent pixels in the decoded video signal as an inter-pixel difference value;
The inter-pixel difference value is divided for each pixel group in units of M, which is a block size N (N is an integer) of the block of the decoded video signal or an integer multiple of the block size N, and a first in each pixel group. To the Nth (n: 1 to N or 1 to M) of the inter-pixel difference value corresponding to each of the Nth or 1st to Mth pixels. Accumulating means for obtaining the results of accumulation between the arranged ones as first to Nth block noise values or first to Mth block noise values, respectively;
A maximum block noise value is determined from each of the first to Nth block noise values or each of the first to Mth block noise values, and a pixel position in the pixel group corresponding to the maximum block noise value is determined as a block boundary. A block boundary position signal indicating a position is generated, and a larger one of the block noise values corresponding to pixels adjacent to both sides of the pixel corresponding to the maximum block noise value is determined as a phase error block noise value. Block boundary detection means for generating a phase error signal based on a ratio between the phase error block noise value and the maximum block noise value;
Phase correction means for detecting a phase correction pixel sample value obtained by performing phase correction processing based on the phase error signal for the decoded video signal;
And a means for generating a noise-removed video signal by performing a block noise removal process based on the phase correction pixel sample value.   The block noise correction position is a position in which the position of the maximum block noise value and the position of the phase error block noise value are distributed by a ratio of the phase error block noise value and the maximum block noise value. The block noise removing device according to claim 1.   A unit for detecting a median value of each of the m consecutive inter-pixel difference values, and detecting a difference between the median value and the corresponding inter-pixel difference value as a unit block noise value; The block noise removing apparatus according to claim 1, wherein the accumulation unit is executed using a block noise value as a new inter-pixel difference value. A block noise removing apparatus for removing block noise from a decoded video signal encoded and decoded for each pixel block composed of a plurality of pixels,
An inter-pixel difference value calculating means for obtaining a difference value between adjacent pixels in the decoded video signal as an inter-pixel difference value;
The inter-pixel difference value is divided for each pixel group in units of M, which is a common multiple of the block size N (N is an integer) of the block of the decoded video signal and the resized block size L estimated in the decoded video signal. The inter-pixel difference value corresponding to each of the first to Mth pixels arranged in each of the pixel groups is arranged in the nth (n: 1 to M) in each of the pixel groups. Accumulating means for accumulating the results of accumulating them as first to Mth block noise values,
Period determining means for determining whether the period of the first to M-th block noise values that are consecutive is N or L;
A maximum block noise value is determined from each of the first to Nth block noise values or each of the first to Mth block noise values, and a pixel position in the pixel group corresponding to the maximum block noise value is determined as a block boundary. A block boundary position signal indicating a position is generated, and a larger one of the block noise values corresponding to pixels adjacent to both sides of the pixel corresponding to the maximum block noise value is determined as a phase error block noise value. Block boundary detection means for generating a phase error signal based on a ratio between the phase error block noise value and the maximum block noise value;
Phase correction means for detecting a phase correction pixel sample value obtained by performing phase correction processing based on the phase error signal for the decoded video signal;
A block noise removing apparatus comprising: means for generating a noise-removed video signal by performing a block noise removing process based on the phase correction pixel sample value and the period detected by the period determining means.   The block noise correction position is a position in which the position of the maximum block noise value and the position of the phase error block noise value are distributed by a ratio of the phase error block noise value and the maximum block noise value. The block noise removing device according to claim 4.   A unit for detecting a median value of each of the m consecutive inter-pixel difference values, and detecting a difference between the median value and the corresponding inter-pixel difference value as a unit block noise value; 6. The block noise removing apparatus according to claim 4, wherein the accumulation means is executed with a block noise value as a new inter-pixel difference value. Resizing the decoded video signal consisting of N (horizontal direction) × N (vertical direction) pixels encoded or decoded for each pixel block composed of a plurality of pixels or the resolution of the decoded video signal by Q times A block noise removing apparatus for removing block noise from the resized decoded video signal,
An inter-pixel difference value calculating means for obtaining a difference value between adjacent pixels in the decoded video signal or the resized decoded video signal as an inter-pixel difference value;
Each pixel in one screen is divided into pixel groups each composed of M pixels (M: a common multiple of N · Q and N) arranged adjacent to each other in the horizontal direction or the vertical direction. The unit block noise value corresponding to each of the first to Mth pixels arranged in the pixel group is accumulated among the nth (n: 1 to M) arranged pixels in each of the pixel groups. Accumulation means for obtaining the obtained results as first to Mth block noise values, respectively;
The first to Nth block noise values are periodically assigned to the first to Mth block noise values in order of the first to Mth block noise values, and the same label is assigned to each block noise value. Convolution means for obtaining the first to Nth convolution block noise values respectively as a result of accumulating
A first block boundary position signal indicating a maximum convolution block noise value from each of the first to Nth convolution block noise values and indicating a pixel position corresponding to the maximum convolution block noise value as a block boundary position. And generating a larger one of the convolution block noise values respectively corresponding to pixels adjacent to both sides of the pixel corresponding to the maximum convolution block noise value as a phase error convolution block noise value. First block boundary detecting means for generating a first phase error signal based on a ratio between a phase error convolution block noise value and the maximum convolution block noise value;
A maximum block noise value is determined from each of the first to Mth block noise values, and a second block boundary position signal indicating a pixel position corresponding to the maximum block noise value as a block boundary position is generated. A larger one of the block noise values corresponding to pixels adjacent to both sides of the pixel corresponding to the block noise value is determined as a phase error block noise value, and the phase error block noise value and the maximum block noise value are determined. Second block boundary detection means for generating a second phase error signal based on the ratio of:
One of the first phase error signal and the second phase error signal is selected and output as a phase error signal, and one of the first block boundary position signal and the second block boundary position signal is output. Selecting means for selecting and outputting this as a block boundary position signal;
The decoded video signal or the resized decoded video signal is subjected to a phase correction process based on the phase error signal and then subjected to a block noise removal process based on the block boundary position signal to generate a noise-removed video signal. And a block noise removing device. The selection means has a maximum value in each of the convolution block noise values excluding the maximum convolution block noise value and the phase error convolution block noise value from each of the first to Nth convolution block noise values. Means for generating a difference between the convolution block noise value and the maximum convolution block noise value as a first boundary determination value;
The maximum block noise value and the phase error block noise value from each of the first to M-th block noise values, and each maximum quasi-block noise value arranged at each resizing period from the position of the maximum block noise value, Each block noise value excluding each quasi-phase error block noise value, which is the larger of the block noise values respectively corresponding to pixels adjacent to both sides of the pixel corresponding to each quasi-maximum block noise value. A means for generating a difference between the maximum block noise value and the maximum block noise value as a second boundary determination value;
When the first boundary determination value is larger than the second boundary determination value, the first phase error signal and the first phase error signal are selected, respectively, and the phase error signal and the block boundary position signal are selected. When the second boundary judgment value is larger than the first boundary judgment value, the second phase error signal and the second phase error signal are selected and the phase error signal and The block noise removing apparatus according to claim 7, further comprising: a unit that outputs the block boundary position signal.

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