JP2007311647A - Solid state imaging element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid state imaging element capable of performing a good imaging even with a low bias voltage in the solid state imaging element having a photoelectric conversion device constituted by sandwiching an organic photoelectric conversion layer between a pair of electrodes. <P>SOLUTION: The solid state imaging element is equipped with: the photoelectric conversion device having a lower electrode formed in an upper part of a semiconductor substrate, an upper electrode formed in an upper part of the lower electrode, and an interlayer including the organic photoelectric conversion layer formed between the lower electrode and the upper electrode; and a signal reader which outwardly reads out a signal corresponding to a signal charge occurring in the photoelectric conversion device. When a bias voltage of 0.1 V or more and 3 V or less is applied between the lower electrode and the upper electrode to perform the imaging, an external quantum efficiency becomes 1% or more in a wavelength region of a light absorbed in the organic photoelectric conversion layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention includes a lower electrode formed above a semiconductor substrate, an upper electrode formed above the lower electrode, and an intermediate layer including an organic photoelectric conversion layer formed between the lower electrode and the upper electrode. The present invention relates to a solid-state imaging device including a photoelectric conversion element having a signal read-out unit that reads a signal corresponding to a signal charge generated by the photoelectric conversion element to the outside.

  A conventional optical sensor is generally an element formed by forming a photodiode (PD) in a semiconductor substrate such as silicon (Si). As a solid-state image sensor, a PD is two-dimensionally formed in a semiconductor substrate. 2. Description of the Related Art Flat-type solid-state imaging devices that are arranged and read out a signal corresponding to a signal charge generated by photoelectric conversion in each PD by a CCD or CMOS circuit are widely used. As a method for realizing a color solid-state imaging device, a structure in which a color filter that transmits only light of a specific wavelength for color separation is generally arranged on the light incident surface side of the flat-type solid-state imaging device. As a method widely used in digital cameras and the like at present, color filters that respectively transmit blue (B) light, green (G) light, and red (R) light are regularly arranged on the two-dimensionally arranged PDs. A single-plate type solid-state imaging device arranged in is well known.

  However, in the single-plate solid-state imaging device, the color filter transmits only light of a limited wavelength, so that the light that does not pass through the color filter is not used and the light use efficiency is poor. Further, with the high integration, the size of the PD becomes about the same as the wavelength of light, and the light is less likely to be guided to the PD. In addition, since blue light, green light, and red light are color-reproduced by detecting them with separate PDs that are close to each other, false colors may be generated. In order to avoid this false color An optical low-pass filter is required, and optical loss due to this filter also occurs.

  Conventionally, as a device for solving these drawbacks, three PDs are stacked in a silicon substrate by utilizing the wavelength dependence of the absorption coefficient of silicon, and color separation is performed by the difference in the depth of the pn junction surface of each PD. A color sensor that performs the above has been reported (see Patent Documents 1, 2, and 3). However, this method has a problem that the wavelength dependence of spectral sensitivity in the stacked PD is broad and color separation is insufficient. In particular, blue and green color separation is insufficient.

  In order to solve this problem, an organic photoelectric conversion element that detects green light and generates a signal charge corresponding thereto is provided above the silicon substrate, and blue light and red light are formed by two PDs stacked in the silicon substrate. Has been proposed (see Patent Document 4). The organic photoelectric conversion element provided above the silicon substrate includes a lower electrode stacked on the silicon substrate, a photoelectric conversion layer made of an organic material stacked on the lower electrode, and an upper electrode stacked on the photoelectric conversion layer. By applying a bias voltage between the lower electrode and the upper electrode, the charge generated in the photoelectric conversion layer moves to the lower electrode and the upper electrode, and the charge moved to one of the electrodes A corresponding signal is read out by a CCD, a CMOS circuit or the like provided in the silicon substrate. In this specification, the photoelectric conversion layer refers to a layer that absorbs light having a specific wavelength incident thereon and generates charges (electrons and holes) according to the absorbed light quantity.

US Pat. No. 5,965,875 US Pat. No. 6,632,701 Japanese Patent Laid-Open No. 7-38136 JP 2003-332551 A

  As an organic photoelectric conversion element, it is possible to divert the conventional organic photoelectric conversion element used for an organic thin-film solar cell etc. Since it is necessary to take out electric charges without applying an external bias, the organic photoelectric conversion layer is generally designed to be thin. Therefore, when an image sensor is assumed, the following problems occur.

  In order to configure the imaging device, unlike the conventional organic photoelectric conversion device, it is necessary to use a highly light-transmitting electrode as at least the upper electrode among the electrodes sandwiching the organic photoelectric conversion layer. At this time, the upper transparent electrode is directly formed on the organic film. A transparent conductive oxide is suitable as a highly transparent electrode, and an ITO (indium oxide doped with Sn) electrode or the like is a candidate from the viewpoint of process suitability and smoothness. However, since these transparent conductive oxides are generally formed by sputtering, when the film is formed as the upper electrode, sputtered particles may sink into the gaps of the photoelectric conversion layer or the photoelectric conversion layer may be damaged by plasma. For this reason, the device is easily short-circuited. Therefore, for example, when both the upper and lower electrodes of a conventional organic photoelectric conversion element used in an organic thin film solar cell are to be transparent electrodes, the photoelectric conversion layer is as thin as about 100 nm, so shorts frequently occur and the yield is large. Serious problems such as degradation occur. Shortening can be gradually reduced by increasing the thickness of the photoelectric conversion layer. However, when the photoelectric conversion layer is thick, carriers generated in the photoelectric conversion layer cannot be sufficiently extracted to the electrode unless an external bias voltage is applied. .

  On the other hand, a problem also occurs when a large external bias voltage is applied. Since the organic photoelectric conversion layer is formed by a vacuum heating deposition method or the like, there are not a few irregularities on the surface of the organic photoelectric conversion layer. For this reason, when a large external bias voltage is applied, a portion where a strong electric field is applied locally occurs, and many pixel defects occur. Even for pixels that do not become defective, since the local electric field varies from pixel to pixel, the output signal varies, resulting in a noticeable imaging result.

  The present invention has been made in view of the above circumstances, and in a solid-state imaging device having a photoelectric conversion element having a configuration in which an organic photoelectric conversion layer is sandwiched between a pair of electrodes, it is possible to perform good imaging even with a low bias voltage. An object of the present invention is to provide a solid-state imaging device.

(1) A lower electrode formed above a semiconductor substrate, an upper electrode formed above the lower electrode, and an intermediate layer including an organic photoelectric conversion layer formed between the lower electrode and the upper electrode. A solid-state imaging device comprising: a photoelectric conversion element having a signal reading unit that reads a signal corresponding to a signal charge generated by the photoelectric conversion element;
When imaging is performed by applying a bias voltage of 0.1 V or more and 3 V or less between the lower electrode and the upper electrode, the external quantum efficiency in the wavelength region of light absorbed by the organic photoelectric conversion layer is 1% or more A solid-state imaging device.

(2) The solid-state imaging device according to (1), wherein the upper electrode is a transparent electrode.

(3) The solid-state imaging device according to (2), wherein the lower electrode is a transparent electrode.

(4) The solid-state imaging device according to (2) or (3), wherein the material of the transparent electrode is a transparent conductive oxide.

(5) The solid-state imaging device according to (4), wherein the transparent conductive oxide is ITO.

(6) The solid-state imaging device according to any one of (1) to (5), wherein the organic photoelectric conversion layer includes a material of any one of a quinacridone skeleton, a phthalocyanine skeleton, and an anthraquinone skeleton. .

(7) The solid-state imaging device according to any one of (1) to (6), wherein an average surface roughness Ra of the surface of the intermediate layer on the upper electrode side is 1 nm or less.

(8) The solid-state imaging device according to any one of (1) to (7), wherein the intermediate layer has a thickness of 150 nm or more.

(9) The solid-state imaging device according to any one of (1) to (8), wherein an electrode for extracting electrons generated in the organic photoelectric conversion layer out of the upper electrode and the lower electrode. A solid-state imaging device having a work function of 4.5 eV or less.

(10) The solid-state imaging device according to (9), wherein the electrode for extracting electrons has a two-layer structure of a transparent electrode and a metal thin film having a work function of 4.5 eV or less,
The metal thin film is a solid-state imaging device positioned between the intermediate layer and the transparent electrode.

(11) The solid-state imaging device according to (10), wherein the metal thin film is made of In.

(12) The solid-state imaging device according to (11), wherein the In thickness is 0.5 to 10 nm.

(13) The solid-state imaging device according to any one of (1) to (12), comprising a sealing film that is formed on the photoelectric conversion device and seals the photoelectric conversion device. .

(14) The solid-state imaging device according to (13), wherein the sealing film is formed by an atomic layer deposition (ALD) method.

(15) The solid-state imaging device according to (13) or (14), wherein the material of the sealing film includes a metal oxide.

(16) The solid-state imaging device according to (15), wherein the metal oxide is Al ₂ O ₃ .

(17) The solid-state imaging device according to (15) or (16), wherein the sealing film includes a film made of the metal oxide and a polymer compound formed on the film made of the metal oxide. A solid-state imaging device having a two-layer structure with a film.

(18) The solid-state imaging device according to (17), wherein the polymer compound is a paraxylylene resin.

(19) The solid-state image sensor according to any one of (1) to (18), wherein the photoelectric conversion element is glass-sealed in a package body in an inert gas atmosphere.

(20) The solid-state imaging device according to (19), wherein the concentration of oxygen contained in the inert gas is 0.05% or less.

(21) The solid-state imaging device according to (19) or (20), wherein a dew point of the inert gas is −75 ° C. or lower.

(22) The solid-state imaging device according to any one of (1) to (21), wherein the signal readout unit is a CMOS circuit.

(23) The solid-state imaging device according to any one of (1) to (22), wherein the semiconductor substrate absorbs light transmitted through the organic photoelectric conversion layer of the photoelectric conversion device, and A solid-state imaging device including an in-substrate photoelectric conversion unit that generates and accumulates charges according to light.

(24) The solid-state imaging device according to (23), wherein the in-substrate photoelectric conversion unit is two photodiodes that absorb light of different colors stacked in the semiconductor substrate.

(25) The solid-state imaging device according to (23), wherein the in-substrate photoelectric conversion unit absorbs light of different colors arranged in a direction perpendicular to an incident direction of incident light in the semiconductor substrate. A solid-state imaging device that is two photodiodes.

(26) The solid-state imaging device according to (24) or (25), wherein each of the two photodiodes absorbs light in a wavelength region of red, blue, or green.

(27) The solid-state imaging device according to any one of (1) to (22), wherein a plurality of the photoelectric conversion elements are stacked above the semiconductor substrate.

  According to the present invention, in a solid-state imaging device having a photoelectric conversion element having a configuration in which an organic photoelectric conversion layer is sandwiched between a pair of electrodes, it is possible to provide a solid-state imaging element capable of performing good imaging even with a low bias voltage. it can.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic cross-sectional view showing a schematic configuration of a solid-state imaging device package for explaining an embodiment of the present invention.
The solid-state imaging device package shown in FIG. 1 has a concave package body 100 having a housing portion 500 for housing the solid-state imaging device chip 200, and the solid-state imaging device package 200 in the housing portion 500 by closing the opening of the package body 100. The peripheral part of the opening of the package body 100 and the glass plate 400 are bonded together via an adhesive such as resin (not shown). .

FIG. 2 is a schematic plan view showing a schematic configuration of the solid-state imaging element chip 200 shown in FIG.
The solid-state imaging device chip 200 includes a large number of pixels 200b arranged two-dimensionally on a semiconductor substrate 1 such as silicon, and a large number of electrode pads 200a formed in a portion other than a region where the large number of pixels 200b are formed. Is provided. A large number of electrode pads 200 a are bonded with wirings 300 for electrical connection between an external device and the solid-state imaging device chip 200.

FIG. 3 is a schematic cross-sectional view showing a schematic configuration of one pixel shown in FIG. FIG. 4 is an enlarged view of the photoelectric conversion element shown in FIG.
As shown in FIG. 3, the pixel 200 b of the solid-state imaging device chip 200 includes a lower electrode 11 formed above the p-type silicon substrate 1 and an intermediate layer 12 including an organic photoelectric conversion layer 122 formed on the lower electrode 11. And a photoelectric conversion element comprising the upper electrode 13 formed on the intermediate layer 12. The lower electrode 11 has a two-layer structure of an electrode 11a and an electrode 11b formed on the electrode 11a. By applying a bias voltage between the lower electrode 11 and the upper electrode 13, the charges generated in the organic photoelectric conversion layer 122 move to the lower electrode 11 and the upper electrode 13, and according to the charges transferred to one of the electrodes The signal is read out by a signal reading unit (not shown) such as a CCD or CMOS circuit provided in the p-type silicon substrate 1.

  In the p-type silicon substrate 1, an n-type high concentration impurity region (hereinafter referred to as an n + region) 6 for accumulating signal charges generated in the photoelectric conversion element is formed. An insulating film 7 is formed on the p-type silicon substrate 1, and the n + region 6 has a lower electrode via a connection portion 9 made of a metal such as aluminum or tungsten formed in an opening opened in the insulating film 7. 11 is electrically connected. In the n + region 6, electrons generated in the organic photoelectric conversion layer 122 and moved to the lower electrode 11 are accumulated through the connection portion 9.

  A light shielding film 16 is formed in the insulating film 7 on the p-type silicon substrate 1, and a signal readout portion is formed below the light shielding film 16. The light shielding film 16 can prevent light from entering the signal readout portion.

  The above-described photoelectric conversion element is formed on the insulating layer 7, and a transparent sealing film 15 for sealing the photoelectric conversion element is formed on the upper electrode 13. The sealing film 15 is for preventing oxygen, moisture, and the like from entering the photoelectric conversion element, particularly the organic photoelectric conversion layer.

  As shown in FIG. 4, the intermediate layer 12 of the photoelectric conversion element included in the solid-state imaging element chip 200 b includes an organic photoelectric conversion layer 122 formed on the lower electrode 11 and an organic layer formed on the organic photoelectric conversion layer 122. And a smoothing layer 123 that relieves unevenness on the surface of the photoelectric conversion layer 122.

  In the photoelectric conversion element shown in FIG. 4, among the charges generated in the organic photoelectric conversion layer 122, holes are moved to the upper electrode 13 and electrons are moved to the lower electrode 11. A bias voltage is applied to.

The lower electrode 11 is an electrode for extracting electrons for extracting electrons generated in the organic photoelectric conversion layer 122. Although the photoelectric conversion element will be described later, it may be necessary to transmit light below the photoelectric conversion element. For this reason, it is preferable that the lower electrode 11 is a transparent transparent electrode. Here, “transparent” means that 80% or more of light in the visible region (about 420 nm to about 660 nm) is transmitted as a whole. A transparent conductive oxide thin film is suitable as the transparent electrode, and it is particularly preferable to use ITO from the viewpoint of process suitability and smoothness. It is also possible to realize a transparent electrode by depositing metal so thin that light in the visible range can be transmitted. The lower electrode 11 may be a hole extraction electrode for extracting holes generated in the organic photoelectric conversion layer 122 by controlling a bias voltage. As the material of the lower electrode 11, ITO, IZO, AZO, ZnO ₂ , SnO ₂ , TiO ₂ , FTO, Al, Ag, Au, and the like can be used. The lower electrode 11 is separated for each pixel 200b because it is necessary to read signals independently for each of the large number of pixels 200b.

The upper electrode 13 is an electrode for collecting holes generated in the organic photoelectric conversion layer 122. Since light needs to be incident on the organic photoelectric conversion layer 122, the upper electrode 13 is preferably a transparent electrode. As a material of the upper electrode 13, ITO, IZO, AZO, ZnO ₂ , SnO ₂ , TiO ₂ , FTO, Al, Ag, Au, or the like can be used. Since the upper electrode 13 can be used in common for all pixels, it may be a single-layer film and does not need to be separated for each pixel.

  The organic photoelectric conversion layer 122 is composed of a photoelectric conversion material that absorbs light of a specific wavelength and generates a charge corresponding to the absorbed light. The organic photoelectric conversion layer 122 may have a single layer structure or a multilayer structure. From the viewpoint of high photoelectric conversion performance, an organic material having high crystallinity is more preferable. Examples of the material constituting the organic photoelectric conversion layer 122 include materials having a quinacridone skeleton, a phthalocyanine skeleton, and an anthraquinone skeleton. When quinacridone represented by the following chemical formula 1 is used as the organic photoelectric conversion layer 122, the organic photoelectric conversion layer 122 can absorb light in the green wavelength region and generate a charge corresponding to the light. Become. In the case where zinc phthalocyanine represented by the following chemical formula 2 is used as the organic photoelectric conversion layer 122, the organic photoelectric conversion layer 122 can absorb light in the red wavelength region and generate a charge corresponding thereto. It becomes. When anthraquinone A represented by the following chemical formula 3 is used as the organic photoelectric conversion layer 122, the organic photoelectric conversion layer 122 can absorb light in the blue wavelength region and generate a charge corresponding to the light. It becomes. Since the organic photoelectric conversion layer 122 can also be used in common for all pixels, it may be a single-layer film and does not need to be separated for each pixel.

  The smooth layer 123 may be any material that has less unevenness on the surface and does not short-circuit the organic photoelectric conversion layer 122, and an organic material or an inorganic material can be used. In particular, an amorphous material is preferably used because there is not much unevenness on the surface. The smooth layer 123 is preferably transparent because it is necessary to make light incident on the organic photoelectric conversion layer 122. In addition, the effect by having introduce | transduced the smooth layer is demonstrated in detail in Japanese Patent Application No. 2006-45955.

  In the photoelectric conversion element shown in FIG. 4, the upper electrode 13 is used as an electrode for extracting holes. For this reason, it is preferable that the material which comprises the smooth layer 123 is a hole transportable material. As a hole transporting material suitable for the smooth layer 123, a triphenylamine-based organic material having a triphenylamine structure can be given. Examples of the triphenylamine-based organic material include a starburstamine-based organic material having a starburstamine structure in which the triphenylamine structure is connected in a star shape. Examples of the triphenylamine-based organic material include m-MTDATA (4,4 ′, 4 ″ -tris (3-methylphenylphenylamino) triphenylamine) represented by the following chemical formula 4, and a material (amine) represented by the following chemical formula 5. A) and the like can be used. As the starburst amine-based organic material, TDATA shown in the following chemical formula 6 or the like can be used.

In the photoelectric conversion element shown in FIG. 4, when the upper electrode 13 is an electrode for extracting electrons and the lower electrode 11 is an electrode for extracting holes, the material constituting the smooth layer 123 is an electron transporting material. Preferably there is. As an electron transporting material suitable for the smooth layer 123, Alq ₃ (Alqtris (8-hydroxyquinolinato) aluminum (III)) represented by the following chemical formula 7 or a derivative thereof can be used.

  Due to the presence of the smooth layer 123, it is possible to prevent the sputtered particles from entering the irregularities on the surface of the organic photoelectric conversion layer 122 even when the upper electrode 13 is formed by the sputtering method. In order to effectively prevent spattering of the sputtered particles, the average surface roughness Ra of the surface of the smooth layer 123 on the upper electrode 13 side is preferably 1 nm or less.

  In addition, the presence of the smooth layer 123 can prevent the organic photoelectric conversion layer 122 from being exposed to plasma during sputtering. Further, since the upper electrode 13 is formed on the smooth layer 123, the upper electrode 13 can be formed flat, and a bias voltage can be applied uniformly within the organic photoelectric conversion layer 122. Thus, by providing the smooth layer 123, it becomes possible to prevent the performance deterioration of a photoelectric conversion element. Note that the surface of the organic photoelectric conversion layer 122 has more irregularities when the organic photoelectric conversion layer 122 is made of a polycrystalline material. For this reason, it is particularly effective to provide the smooth layer 123 in such a configuration. Further, the smooth layer 123 may itself be composed of a photoelectric conversion material. An example of the polycrystalline organic material is quinacridone described above.

  Next, the function of the electrode 11b constituting the lower electrode 11 will be described. The work function of the lower electrode is adjusted by the electrode 11b. The adjustment of the work function of the electrode is described in detail in Japanese Patent Application No. 2005-251745.

In a photoelectric conversion element having a structure in which a photoelectric conversion layer is sandwiched between two electrodes, in particular, when a highly transparent transparent electrode such as ITO is used as an electrode for extracting electrons, the dark current when a bias is applied is when a voltage of 1 V is applied. Is about 10 μA / cm ² .
As one of the causes of dark current, a current flowing from the electrode for extracting electrons into the photoelectric conversion layer when a bias is applied can be considered. When a highly transparent electrode such as an ITO transparent electrode is used as an electrode for extracting electrons, when the holes move from the electrode for extracting electrons to the photoelectric conversion layer because the work function of the electrode is relatively large It was thought that the barrier of the hole would be lowered and hole injection into the photoelectric conversion layer would easily occur. Actually, when examining the work function of a highly transparent metal oxide transparent electrode such as ITO, the work function of the ITO electrode is about 4.8 eV, and the work function of the Al (aluminum) electrode is about 4. It is considerably higher than 3 eV, and other metal oxide-based transparent electrodes other than ITO are about 4. e.g., except for the smallest AZO (Al-doped zinc oxide) of about 4.5 eV. 6 to 5.4 and its work function are known to be relatively large (for example, see J. Vac. Sci. Technol. A17 (4), Jul / Aug 1999 p. 1765-1772, FIG. 1). 12).

  Thus, when the work function of the electrode for extracting electrons is large, the barrier when holes are transferred from the electrode for extracting electrons to the photoelectric conversion layer when a bias is applied is lowered, and photoelectric conversion from the electrode for extracting electrons is performed. It is considered that hole injection tends to occur in the layer, and as a result, dark current increases.

  Therefore, in the photoelectric conversion element shown in FIG. 4, the work function of the lower electrode 11 which is an electrode for extracting electrons is set to 4.5 eV or less. Methods for setting the work function of the lower electrode 11 to 4.5 eV or less are listed below.

(A) As shown in FIG. 4, the lower electrode 11 has a two-layer structure, and an electrode 11 b that adjusts the work function of the electrode 11 a is provided between the electrode 11 a and the organic photoelectric conversion layer 122.
For example, ITO is used as the electrode 11a, and a metal thin film containing In, Ag, or Mg having a work function of 4.5 eV or less is used as the electrode 11b. When In is used, the thickness thereof is preferably 0.5 to 10 nm, as will be shown in Examples described later.
(B) A conductive transparent metal oxide thin film having a work function of 4.5 eV or less is used as the lower electrode 11.
For example, an AZO thin film having a work function of 4.5 eV is used as the conductive transparent metal oxide thin film.
(C) As the lower electrode 11, a transparent electrode doped with metal oxide and having a work function of 4.5 eV or less is used.
For example, an electrode having a work function of 4.5 eV or less by doping Cs into ITO as a conductive metal oxide is used.
(D) As the lower electrode 11, an electrode having a work function of 4.5 eV or less by surface-treating a conductive transparent metal oxide thin film is used.
For example, ITO is used as the lower electrode 11, and an electrode having a work function of 4.5 eV or less is used by immersing the ITO in an alkaline solution and performing surface treatment. Alternatively, an electrode in which ITO is sputtered with Ar ions or Ne ions and surface-treated to have a work function of 4.5 eV or less is used.

In the case where the upper electrode 13 is an electrode for extracting electrons, the work function of the upper electrode 13 may be 4.5 eV or less. Examples of the method of setting the work function of the upper electrode 13 to 4.5 eV or less include the following (E) and those in which the lower electrode 11 is changed to the upper electrode 13 in the description of the above (B) to (D).
(E) In FIG. 4, an electrode for adjusting the work function of the upper electrode 13 is provided between the upper electrode 13 and the smooth layer 123, and the electrode 11b is deleted. For example, ITO is used as the upper electrode 13, and a metal thin film containing In, Ag, or Mg having a work function of 4.5 eV or less is used as an electrode for adjusting the work function.

  Examples of literature relating to work function adjustment of a transparent electrode made of ITO will be given below.

  Moreover, the metal whose work function is 4.5 or less is enumerated below with the characteristic.

  According to the solid-state imaging device having the above-described configuration, as shown in an example described later, imaging is performed by applying a very low bias voltage of 0.5 V to 3 V between the lower electrode 11 and the upper electrode 13. Even when it is performed, an external quantum efficiency of 1% or more can be obtained in the wavelength range of light absorbed by the organic photoelectric conversion layer 122. Since it can be driven with a low bias, pixel defects due to some unevenness on the surface of the smooth layer 123 can be reduced, and high image quality can be realized. In addition, when a CMOS circuit is used as the signal reading unit, the driving voltage of a normal CMOS circuit is about 3 V, so that the same voltage source as that of the CMOS circuit can be used.

  The thickness of the intermediate layer 12 described above is preferably 150 nm or more, as shown in Examples described later, in consideration of the short-circuit preventing effect due to the upper electrode 13 formation step.

  Hereinafter, modifications of the solid-state imaging device in which the photoelectric conversion elements as described above are stacked on a semiconductor substrate will be described.

(First modification)
FIG. 5 is a schematic cross-sectional view illustrating a schematic configuration of one pixel illustrated in FIG. 2, and is a diagram illustrating a first modification.
A pixel 200b illustrated in FIG. 5 includes a photoelectric conversion element having the configuration illustrated in FIG. 4 and two photodiodes formed on the silicon substrate 1 below the photoelectric conversion element. In FIG. 5, the same reference numerals as those in FIG.

  A pixel 200b shown in FIG. 5 includes a p-type silicon substrate 1, an insulating film 7 formed on the p-type silicon substrate 1, and a photoelectric conversion element formed on the insulating film 7. A light shielding film 14 having an opening is formed on the element. A transparent sealing film 15 is formed on the light shielding film 14 and the upper electrode 13.

  In the configuration of FIG. 5, the organic photoelectric conversion layer 122 uses a material that absorbs green light and generates electrons and holes corresponding thereto.

  In the p-type silicon substrate 1, an n-type semiconductor region (hereinafter abbreviated as n region) 4, a p-type semiconductor region (hereinafter abbreviated as p region) 3, and an n region 2 are formed in this order from the shallower side. Has been. A high-concentration n region (referred to as n + region) 6 is formed on the surface portion of the n region 4 that is shielded by the light shielding film 14, and the n + region 6 is surrounded by the p region 5.

  The depth of the pn junction surface between the n region 4 and the p region 3 from the surface of the p-type silicon substrate 1 is a depth that absorbs blue light (about 0.2 μm). Therefore, the n region 4 and the p region 3 absorb blue light, generate electrons corresponding thereto, and form a photodiode (B photodiode) that accumulates the electrons. Electrons generated in the B photodiode are accumulated in the n region 4.

  The depth of the pn junction surface between the n region 2 and the p-type silicon substrate 1 from the surface of the p-type silicon substrate 1 is a depth that absorbs red light (about 2 μm). Therefore, the n region 2 and the p-type silicon substrate 1 absorb red light, generate electrons corresponding thereto, and form a photodiode (R photodiode) that accumulates the electrons. Electrons generated in the R photodiode are accumulated in the n region 2.

  The n + region 6 is electrically connected to the lower electrode 11 via the connection portion 9, and accumulates electrons that have moved to the lower electrode 11 via the connection portion 9. The connecting portion 9 is electrically insulated by the insulating film 8 except for the lower electrode 11 and the n + region 6.

  The electrons accumulated in the n region 2 are converted into a signal corresponding to the amount of charge by a CMOS circuit (not shown) made of an n channel MOS transistor formed in the p-type silicon substrate 1 and accumulated in the n region 4. The electrons are converted into a signal corresponding to the amount of charge by a CMOS circuit (not shown) formed of an n-channel MOS transistor formed in the p region 3, and the electrons accumulated in the n + region 6 The signal is converted into a signal corresponding to the amount of charge by a CMOS circuit (not shown) composed of an n-channel MOS transistor formed in, and output to the outside of the solid-state imaging device 200. Each CMOS circuit is connected to a signal readout pad (not shown) by wiring 10. If extraction electrodes are provided in the n region 2 and the n region 4 and a predetermined reset potential is applied, each region is depleted, and the capacitance of each pn junction becomes an extremely small value. Thereby, the capacity | capacitance produced in a joint surface can be made very small.

  With such a configuration, G light can be photoelectrically converted by the organic photoelectric conversion layer 122, and B light and R light can be photoelectrically converted by the B photodiode and the R photodiode in the p-type silicon substrate 1. In addition, since G light is first absorbed at the top, color separation between BG and GR is excellent. This is a great advantage over a solid-state imaging device in which three PDs are stacked in a silicon substrate and all BGR light is separated in the silicon substrate. In the following description, the part (B photodiode and R photodiode) that performs photoelectric conversion made of an inorganic material formed in the p-type silicon substrate 1 of the pixel 200b is also referred to as an inorganic layer.

  Note that light transmitted through the organic photoelectric conversion layer 122 is absorbed between the p-type silicon substrate 1 and the lower electrode film 11 (for example, between the insulating film 7 and the p-type silicon substrate 1), and in response to the light. It is also possible to form an inorganic photoelectric conversion portion made of an inorganic material that generates and accumulates the charges. In this case, a MOS circuit for reading a signal corresponding to the charge accumulated in the charge accumulation region of the inorganic photoelectric conversion unit is provided in the p-type silicon substrate 1, and the wiring 10 is also connected to this CMOS circuit. It ’s fine.

(Inorganic layer)
As the inorganic layer, a pn junction or a pin junction of a compound semiconductor such as crystalline silicon, amorphous silicon, or GaAs is generally used. In this case, since color separation is performed based on the light penetration depth of silicon, the spectral range detected by each stacked light receiving unit is broad. However, the color separation is remarkably improved by using the intermediate layer 12 as an upper layer as shown in FIG. 5, that is, by detecting the light transmitted through the intermediate layer 12 in the depth direction of silicon. In particular, as shown in FIG. 5, when G light is detected in the intermediate layer 12, the light transmitted through the intermediate layer 12 becomes B light and R light, so that the light separation in the depth direction in silicon is only BR light. The color separation is improved. Even when the intermediate layer 12 detects B light or R light, the color separation is remarkably improved by appropriately selecting the depth of the pn junction surface of silicon.

  The structure of the inorganic layer is preferably npn or pnpn from the light incident side. In particular, by providing a p layer on the surface and increasing the surface potential, holes generated in the vicinity of the surface and dark current can be trapped and dark current can be reduced. preferable.

  5 shows a configuration in which one photoelectric conversion element having the configuration shown in FIG. 4 is stacked above the p-type silicon substrate 1, the photoelectric conversion having the configuration shown in FIG. A structure in which a plurality of elements are stacked is also possible. A configuration in which a plurality of photoelectric conversion elements having the configuration shown in FIG. 4 are stacked will be described in a third modification later. In this case, the light detected by the inorganic layer may be one color, and preferable color separation can be achieved. Further, when detecting four colors of light in the pixel 200b, for example, a configuration in which one color is detected by the photoelectric conversion element and three colors are detected by the inorganic layer, and two photoelectric conversion elements are stacked. Thus, a configuration in which two colors are detected and two colors are detected in the inorganic layer, a configuration in which three photoelectric conversion elements are stacked and three colors are detected, and one color is detected in the inorganic layer can be considered.

  The inorganic layer will be described in more detail. As a preferable configuration of the inorganic layer, a photoconductive type, a pn junction type, a Schottky junction type, a PIN junction type, an MSM (metal-semiconductor-metal) type light receiving element or a phototransistor type light receiving element can be given. In particular, as shown in FIG. 5, a plurality of first conductivity type regions and second conductivity type regions, which are opposite to the first conductivity type, are alternately stacked in a single semiconductor substrate. It is preferable to use an inorganic layer formed by forming each bonding surface of the first conductivity type region and the second conductivity type region to a depth suitable for mainly photoelectrically converting light in a plurality of different wavelength bands. . As the single semiconductor substrate, single crystal silicon is preferable, and color separation can be performed using absorption wavelength characteristics depending on the depth direction of the silicon substrate.

As the inorganic semiconductor, an InGaN-based, InAlN-based, InAlP-based, or InGaAlP-based inorganic semiconductor can also be used. The nGaN-based inorganic semiconductor is adjusted so as to have a maximum absorption value in the blue wavelength range by appropriately changing the composition of In. That is, the composition is In _x Ga _1-x N (0 ≦ X <1). Such a compound semiconductor is manufactured using a metal organic chemical vapor deposition method (MOCVD method). A nitride semiconductor InAlN system using Al, which is the same group 13 raw material as Ga, can also be used as a short wavelength light receiving section in the same manner as the InGaN system. InAlP or InGaAlP lattice-matched to the GaAs substrate can also be used.

  The inorganic semiconductor may have a buried structure. The embedded structure means a structure in which both ends of the short wavelength light receiving part are covered with a semiconductor different from the short wavelength light receiving part. The semiconductor covering both ends is preferably a semiconductor having a band gap wavelength shorter than or equivalent to the band gap wavelength of the short wavelength light receiving part.

(Second modification)
In the second modification, the inorganic layer having the structure shown in FIG. 5 described in the first modification is not laminated with two photodiodes in a p-type silicon substrate, but in the incident direction of incident light. Two photodiodes are arranged in a vertical direction to detect light of two colors in a p-type silicon substrate.

FIG. 6 is a schematic cross-sectional view illustrating a schematic configuration of one pixel illustrated in FIG. 2, and is a diagram illustrating a second modification. In FIG. 6, the same components as those in FIG.
A pixel 200b illustrated in FIG. 6 includes a p-type silicon substrate 17 and the photoelectric conversion element having the configuration illustrated in FIG. 4 formed above the p-type silicon substrate 17, and an opening is formed on the photoelectric conversion element. A provided light shielding film 34 is formed. A transparent sealing film 33 is formed on the light shielding film 34 and the upper electrode 13.

  On the surface of the p-type silicon substrate 17 below the opening of the light shielding film 34, a photodiode composed of the p region 19 and the n region 18 and a photodiode composed of the p region 21 and the n region 20 are formed on the surface of the p-type silicon substrate 17. It is formed side by side. An arbitrary direction on the surface of the p-type silicon substrate 17 is a direction perpendicular to the incident direction of incident light.

  Above the photodiode composed of the p region 19 and the n region 18, a color filter 28 that transmits B light is formed through a transparent insulating film 24, and the lower electrode 11 is formed thereon. Above the photodiode composed of the p region 21 and the n region 20, a color filter 29 that transmits R light is formed through a transparent insulating film 24, and the lower electrode 11 is formed thereon. The periphery of the color filters 28 and 29 is covered with a transparent insulating film 25.

  The photodiode including the p region 19 and the n region 18 absorbs the B light transmitted through the color filter 28 and generates electrons corresponding thereto, and accumulates the generated electrons in the n region 18. The photodiode composed of the p region 21 and the n region 20 absorbs the R light transmitted through the color filter 29 and generates electrons corresponding thereto, and accumulates the generated electrons in the n region 20.

  An n + region 23 is formed in a portion of the surface of the p-type silicon substrate 17 that is shielded by the light shielding film 34, and the n + region 23 is surrounded by the p region 22.

  The n + region 23 is electrically connected to the lower electrode 11 through a connection portion 27 made of a metal such as aluminum or tungsten formed in an opening formed in the insulating films 24 and 25. Thus, the moved electrons are accumulated in the lower electrode 11. The connecting portion 27 is electrically insulated by the insulating film 26 except for the lower electrode 11 and the n + region 23.

The electrons accumulated in the n region 18 are converted into a signal corresponding to the amount of charge by a CMOS circuit (not shown) made of an n channel MOS transistor formed in the p-type silicon substrate 17 and accumulated in the n region 20. The electrons are converted into a signal corresponding to the amount of charge by a CMOS circuit (not shown) formed of an n-channel MOS transistor formed in the p-type silicon substrate 17, and the electrons accumulated in the n + region 23 are converted into the p region. The signal is converted into a signal corresponding to the amount of charge by a CMOS circuit (not shown) formed of an n-channel MOS transistor formed in 22 and output to the outside of the solid-state imaging device 300. Each CMOS circuit is connected to a signal readout pad (not shown) by wiring 35.
The signal reading unit may be constituted by a CCD and an amplifier instead of the CMOS circuit. That is, the electrons accumulated in the n region 18, the n region 20, and the n + region 23 are read out to the charge transfer channel formed in the p-type silicon substrate 17, and transferred to the amplifier. A signal reading unit that outputs a signal may be used.

  As described above, the signal reading unit includes a CCD and a CMOS structure, but CMOS is preferable in terms of power consumption, high-speed reading, pixel addition, partial reading, and the like. In addition, in the case of CMOS, signal charges that can be handled are either electrons or holes, but from the viewpoints of high-speed signal readout derived from charge mobility, completeness of process conditions in manufacturing, etc. Since electrons are superior, it is preferable to connect an electron extraction electrode to the n + region.

  In FIG. 6, color separation of the R light and B light is performed by the color filters 28 and 29, but the color filters 28 and 29 are not provided, and the depths of the pn junction surfaces of the n region 20 and the p region 21 are The depths of the pn junction surfaces of the n region 18 and the p region 19 may be adjusted to absorb the R light and the B light by the respective photodiodes. In this case, the light transmitted through the organic photoelectric conversion layer 122 is absorbed between the p-type silicon substrate 17 and the lower electrode 11 (for example, between the insulating film 24 and the p-type silicon substrate 17), and according to the light. It is also possible to form an inorganic photoelectric conversion portion made of an inorganic material that generates and accumulates the charges. In this case, a CMOS circuit for reading a signal corresponding to the charge accumulated in the charge accumulation region of the inorganic photoelectric conversion unit is provided in the p-type silicon substrate 17, and the wiring 35 is also connected to the CMOS circuit. It ’s fine.

  Alternatively, a single photodiode may be provided in the p-type silicon substrate 17 and a plurality of photoelectric conversion elements may be stacked above the p-type silicon substrate 17. Further, a plurality of photodiodes provided in the p-type silicon substrate 17 may be provided, and a plurality of photoelectric conversion elements may be stacked above the p-type silicon substrate 17. If there is no need to produce a color image, a single photodiode provided in the p-type silicon substrate 17 and only one photoelectric conversion element may be stacked.

(Third modification)
In the third modification, the inorganic layer having the structure shown in FIG. 5 described in the first modification is not provided, and a plurality (three in this case) of photoelectric conversion elements having the structure shown in FIG. 4 are stacked above the silicon substrate. This is the configuration.
FIG. 7 is a schematic cross-sectional view illustrating a schematic configuration of one pixel illustrated in FIG. 2, and is a diagram illustrating a third modification. FIG. 7 illustrates a configuration example in which a photoelectric conversion element that detects G light, a photoelectric conversion element that detects R light, and a photoelectric conversion element that detects B light are stacked as photoelectric conversion elements. Each photoelectric conversion element has the same configuration as that shown in FIG. In FIG. 7, in order to distinguish the three photoelectric conversion elements, the reference numerals are changed from those in FIG.

  The pixel 200b shown in FIG. 7 includes a lower electrode 56, an intermediate layer 57 including an organic photoelectric conversion layer formed on the lower electrode 56, and an upper electrode 58 formed on the intermediate layer 57 above the silicon substrate 41. B photoelectric conversion element comprising a photoelectric conversion element, a lower electrode 60, an intermediate layer 61 including an organic photoelectric conversion layer formed on the lower electrode 60, an upper electrode 62 formed on the intermediate layer 61, a lower electrode 64, The G photoelectric conversion element including the intermediate layer 65 including the organic photoelectric conversion layer formed on the lower electrode 64 and the upper electrode 66 formed on the intermediate layer 65 has the lower electrode included in the silicon substrate 41 side. In this state, the layers are stacked in this order.

  A transparent insulating film 48 is formed on the silicon substrate 41, an R photoelectric conversion element is formed thereon, a transparent insulating film 59 is formed thereon, and a B photoelectric conversion element is formed thereon, A transparent insulating film 63 is formed thereon, a G photoelectric conversion element is formed thereon, a light shielding film 68 having an opening is formed thereon, and a transparent sealing film 67 is formed thereon. Yes.

  The lower electrode 64, the intermediate layer 65, and the upper electrode 66 included in the G photoelectric conversion element have the same configuration as the lower electrode 11, the intermediate layer 12, and the upper electrode 13 shown in FIG. However, the organic photoelectric conversion layer included in the intermediate layer 65 uses a material that absorbs green light and generates electrons and holes corresponding thereto.

  The lower electrode 60, the intermediate layer 61, and the upper electrode 62 included in the B photoelectric conversion element have the same configuration as the lower electrode 11, the intermediate layer 12, and the upper electrode 13 shown in FIG. However, the organic photoelectric conversion layer included in the intermediate layer 61 uses a material that absorbs blue light and generates electrons and holes according to the blue light.

  The lower electrode 56, the intermediate layer 57, and the upper electrode 58 included in the R photoelectric conversion element have the same configurations as the lower electrode 11, the intermediate layer 12, and the upper electrode 13 shown in FIG. However, the organic photoelectric conversion layer included in the intermediate layer 57 uses a material that absorbs red light and generates electrons and holes corresponding thereto.

  N + regions 43, 45, and 47 are formed in portions of the surface of the silicon substrate 41 that are shielded by the light-shielding film 68, and each is surrounded by p regions 42, 44, and 46.

  The n + region 43 is electrically connected to the lower electrode 56 through a connection portion 54 made of a metal such as aluminum or tungsten formed in an opening opened in the insulating film 48, and through the connection portion 54, The moved electrons are accumulated in the lower electrode 56. The connecting portion 54 is electrically insulated by the insulating film 51 except for the lower electrode 56 and the n + region 43.

  The n + region 45 is electrically connected to the lower electrode 60 via a connecting portion 53 made of a metal such as aluminum or tungsten formed in an opening formed in the insulating film 48, the R photoelectric conversion element, and the insulating film 59. The moved electrons are accumulated in the lower electrode 60 through the connection portion 53. The connection portion 53 is electrically insulated by the insulating film 50 except for the lower electrode 60 and the n + region 45.

  The n + region 47 is connected to the insulating film 48, the R photoelectric conversion element, the insulating film 59, the B photoelectric conversion element, and the connection part 52 made of a metal such as aluminum or tungsten formed in the opening opened in the insulating film 63. The electrons are electrically connected to the lower electrode 64, and the moved electrons are accumulated in the lower electrode 64 through the connection part 52. The connection portion 52 is electrically insulated by the insulating film 49 except for the lower electrode 64 and the n + region 47.

  The electrons accumulated in the n + region 43 are converted into a signal corresponding to the amount of charge by a CMOS circuit (not shown) formed of an n-channel MOS transistor formed in the p region 42, and accumulated in the n + region 45. Is converted into a signal corresponding to the amount of charge by a CMOS circuit (not shown) formed of an n-channel MOS transistor formed in the p region 44, and the electrons accumulated in the n + region 47 are formed in the p region 46. The signal is converted into a signal corresponding to the amount of electric charge by a CMOS circuit (not shown) composed of the n-channel MOS transistors and output to the outside of the solid-state imaging device chip. Each CMOS circuit is connected to a signal readout pad (not shown) by wiring 55. The signal reading unit may be constituted by a CCD and an amplifier instead of the CMOS circuit. That is, a signal that reads electrons stored in the n + regions 43, 45, and 47 to a charge transfer channel formed in the silicon substrate 41, transfers this to the amplifier, and outputs a signal corresponding to the electrons from the amplifier. It may be a reading unit.

  The light transmitted through the intermediate layers 65, 61, and 57 is absorbed between the silicon substrate 41 and the lower electrode 56 (for example, between the insulating film 48 and the silicon substrate 41), and a charge corresponding to the light is absorbed. It is also possible to form an inorganic photoelectric conversion part made of an inorganic material that generates and accumulates the above. In this case, a CMOS circuit for reading a signal corresponding to the charge stored in the charge storage region of the inorganic photoelectric conversion unit is provided in the silicon substrate 41, and the wiring 55 may be connected to the CMOS circuit. .

  As described above, the configuration in which a plurality of photoelectric conversion elements having the configuration shown in FIG. 4 are stacked on the silicon substrate can be realized by the configuration as shown in FIG.

  In the above description, the organic photoelectric conversion layer that absorbs B light can absorb light of at least 400 to 500 nm, and preferably has a peak wavelength absorptance of 50% or more in that wavelength region. Means things. The organic photoelectric conversion layer that absorbs G light can absorb light of at least 500 to 600 nm, and preferably means that the absorption rate of the peak wavelength in that wavelength region is 50% or more. The organic photoelectric conversion layer that absorbs R light can absorb light of at least 600 to 700 nm, and preferably means that the absorption rate of the peak wavelength in the wavelength region is 50% or more.

  In the case of the configuration as in the first modification example or the third modification example, a pattern in which colors are detected in the order of BGR, BRG, GBR, GRB, RBG, and RGB from the upper layer can be considered. Preferably, the uppermost layer is G. In the case of the second modification, when the upper layer is the R layer, the lower layer is the same BG layer, and when the upper layer is the B layer, the lower layer is the same plane and the upper layer is the G layer. A combination of the lower layer and the BR layer on the same plane is possible. Preferably, the upper layer is the G layer and the lower layer is the same plane as shown in FIG.

  Examples will be described below.

Example 1
A solid-state imaging device package having the configuration shown in FIGS. An insulating film 7 made of silicon oxide is formed on a p-type silicon substrate 1 on which a CMOS circuit and a high concentration impurity region are formed, and a lower electrode 11a having a 15.6 μm square and a thickness of 100 nm is formed thereon using a magnetron sputtering method and a photo A lateral 160 × longitudinal 120 pieces were formed by a lithography method. As shown in FIG. 8, the distance between the lower electrodes 11a was 4.4 μm. FIG. 8 is a partial cross-sectional schematic diagram of the solid-state imaging device chip manufactured in Example 1, and the same components as those in FIG.

  Next, a 2 nm film of In was formed on the lower electrode 11a by vacuum heating vapor deposition to form an electrode 11b. Next, 100 nm of quinacridone was formed by vacuum heating deposition to form an organic photoelectric conversion layer 122, and m-MTDATA was deposited to 100 nm by vacuum heating evaporation to form a smooth layer 123 on quinacridone. Next, ITO was deposited to a thickness of 10 nm on the m-MTDATA by RF magnetron sputtering to form the upper electrode 13. Next, wiring was formed so that a bias voltage could be applied to the upper electrode 13, and a solid-state imaging device chip was produced.

  The solid-state imaging device chip thus manufactured is accommodated in a package body 100 made of ceramic, and after wire bonding, the opening of the package body 100 is closed with a glass plate to seal the solid-state imaging device chip. . Sealing with a glass plate was performed using an ultraviolet curable resin in an inert gas atmosphere. Nitrogen gas was used as the inert gas, the oxygen concentration was 0.03%, and the dew point was -75 ° C. This completed the production of the solid-state imaging device chip sealed with the glass plate.

  Imaging was performed using the manufactured solid-state imaging device package. In imaging, a bias voltage was applied so that the lower electrode side was positively biased with respect to the upper electrode.

  9 to 11 are diagrams illustrating imaging results when the bias voltage applied to the upper electrode is 0.5 V, 2.5 V, and 4.0 V. FIG. FIG. 9A is a diagram showing an output result in the dark when the bias voltage is 4.0 V. Similarly, FIG. 9B shows the bias voltage when the bias voltage is 2.5 V, and FIG. 9C shows the bias voltage. It is a figure which shows the output result at the time of dark when is 0.5V. FIG. 10 (a) is a diagram showing the imaging result of the logo mark of Fuji Photo Film Co., Ltd. when the bias voltage is 4.0V. Similarly, FIG. 10 (b) is a diagram when the bias voltage is 2.5V. 10 (c) is a diagram showing an imaging result when the bias voltage is 0.5V. FIG. 11 (a) is a diagram showing a result of imaging in a Japanese form when the bias voltage is 4.0V. Similarly, FIG. 11 (b) shows a bias voltage of 2.5V, and FIG. 11 (c) shows a bias voltage. It is a figure which shows the imaging result when is 0.5V.

  As can be seen from the results shown in FIG. 9, it can be seen that as the bias voltage decreases from 4 V to 0.5 V, the white spots indicating pixel leakage decrease. It can also be seen that output variations between pixels are reduced. In particular, it can be seen that when the bias voltage exceeds about 3V, the white spot and output variation increase, and when the bias voltage is less than 3V, the white point and output variation decrease.

  The imaging results shown in FIGS. 10 and 11 are obtained by subtracting the dark output signal from the output signal at the time of imaging, and in the leaked defective pixel, both the output at the time of imaging and the output at the time of darkness reach saturation. Therefore, the imaging result is a black spot. As can be seen from the results shown in FIGS. 10 and 11, as the bias voltage is lowered from 4V to 0.5V, it can be seen that the black spots indicating pixel leakage decrease. It can also be seen that output variations between pixels are reduced. In particular, it can be seen that when the bias voltage exceeds about 3V, the black spot and output variation increase, and when it is below 3V, the black spot and output variation decrease.

  Although not shown in FIGS. 10 and 11, when the bias voltage was set to 0 V, an image could not be obtained in either case of the logo mark or the Japanese type.

  From the above results, it can be seen that the solid-state imaging device chip of Example 1 can capture a good image by setting the bias voltage to about 0.5 V to 3 V.

(Example 2)
In Example 1, a solid-state image sensor package in which the solid-state image sensor chip was not sealed with a glass plate was produced. Imaging was performed using the manufactured solid-state imaging device package. In imaging, a bias voltage was applied so that the lower electrode side was positively biased with respect to the upper electrode.

  FIG. 12 is a diagram illustrating an imaging result when a grayscale chart is imaged with the bias voltage applied to the upper electrode set to 1.5 V in the solid-state imaging device chip according to the second embodiment. FIG. 13 is a diagram illustrating an imaging result when the gray scale chart is imaged with the bias voltage applied to the upper electrode set to 0.5 V in the solid-state imaging element chip according to the first embodiment. The imaging conditions of the gray scale chart were the same for both the solid-state image sensor chip of Example 1 and the solid-state image sensor chip of Example 2.

  As can be seen from FIGS. 12 and 13, the solid-state imaging device chip of Example 1 has less image roughness, and a favorable image can be obtained with a lower bias voltage than the solid-state imaging device chip of Example 2. It was. In the solid-state imaging device chip of Example 2, when imaging was performed with a bias voltage of 0.5 V, an image could not be obtained. This is presumably because oxygen and moisture entered the organic photoelectric conversion layer and charge traps were formed in the organic photoelectric conversion layer. However, even in the solid-state imaging device chip of Example 2, when the bias voltage is set to 1.5 V, an image can be obtained as shown in FIG. It is considered that glass sealing is necessary to enable good imaging with voltage.

  Further, in order to quantitatively investigate the effect of glass sealing, a photoelectric conversion element (ITO (100 nm) / In () having the same configuration as that used in the solid-state imaging device chip of Example 2 and Example 1 was formed on a quartz substrate. 2 nm) / quinacridone (100 nm) / m-MTDATA (100 nm) / ITO (10 nm)) was prepared with an element area of 2 mm × 2 mm and evaluated. A photoelectric conversion element that was not sealed with a glass plate was compared as element A, and a photoelectric conversion element that was sealed with glass was compared as element B.

A voltage was applied to each of the upper electrodes of the elements A and B so that the lower electrode side had a positive bias, and the photoelectric conversion performance was examined. The measurement results of the photocurrent and dark current output from the element A and the element B are shown in FIG. As for the photocurrent, the current value when 550 nm G light is irradiated at an intensity of 50 μW / cm ² is shown. FIG. 15 shows the action spectrum (relation between the wavelength of the irradiated light and the external quantum efficiency) measured by irradiating with 50 μW / cm ² monochromatic light at a bias voltage of 0.5V. FIG. 14 and FIG. 15 show that the glass sealing can respond to the G light even with a bias voltage as low as 0.5V. It is considered that the formation of charge traps in the organic photoelectric conversion layer could be suppressed by preventing the entry of oxygen and moisture into the organic photoelectric conversion layer. Thus, by sealing the glass, it was possible to respond to the G light even under a bias condition as low as 0.5 V, and a high-quality image could be taken.

  The external quantum efficiency when a bias of 0.5 V is applied to the element A is about 0.4% with respect to the G light from FIG. 15, and the solid-state imaging element of Example 2 using the element A is It did not function as an image sensor at a bias voltage of 0.5V. From this result and the results of Example 1 and Example 2, it can be seen that the external quantum efficiency in the wavelength region of light absorbed by the organic photoelectric conversion layer is required to be about 1% in order to function as an imaging device. The external quantum efficiency is preferably 10% or more, more preferably 20% or more, further preferably 50% or more, and ideally 80% or more. Since the solid-state imaging device chip of Example 1 can obtain an image with a bias voltage of 0.5 to 3 V, as can be seen from the results of FIGS. 9 to 11, a bias voltage of 0.5 to 3 V is applied. Thus, the external quantum efficiency when imaging is 1% or more.

  Further, as the solid-state imaging device chip and the device A of Example 2 were used in the atmosphere, the device performance deteriorated, and particularly the dark current was significantly increased. Further, in the solid-state imaging device chip of Example 2, the time until the afterimage disappeared was significantly increased. In particular, when the bias voltage between the upper and lower electrodes was increased and measured, the deterioration became severe, and when a bias of about 10 V was applied in the atmosphere, the device did not operate even when the bias voltage was lowered thereafter. On the other hand, in the solid-state imaging device chip and the device B of Example 1, no device deterioration was observed even after one month. This shows that the deterioration of the organic photoelectric conversion layer over time or in use was suppressed by preventing the oxygen and moisture in the atmosphere from touching the organic photoelectric conversion layer. When a bias voltage of 10 V or higher is applied, the dark current is remarkably increased. However, when the bias voltage is lowered thereafter, the imaging performance equivalent to that before the bias voltage is increased is shown. Thus, it turned out that imaging performance improves and durability improves by sealing a photoelectric conversion element with a glass plate.

(Example 3)
On the upper electrode of the solid-state imaging device chip of Example 1, 100 nm of Al ₂ O ₃ which is an example of a metal oxide was laminated by an atomic layer deposition (ALD) method as a sealing film for sealing the photoelectric conversion element. . In the formation of the Al ₂ O ₃ film by the ALD method, trimethylaluminum gas and ozone gas were used. By repeating the procedures of introduction of trimethylaluminum gas, introduction of nitrogen gas for purging, introduction of ozone gas, introduction of nitrogen gas for purging, deposition of one atomic layer is possible. Al ₂ O ₃ was deposited to a thickness of 100 nm under the conditions of a substrate temperature of 100 ° C. and a deposition rate of 0.8 kg / s.

Subsequently, in order to further strengthen the sealing and suppress corrosion of the Al ₂ O ₃ film due to moisture, the structural formula shown in the following chemical formula 4 as an example of a polymer compound is formed on the Al ₂ O ₃ film. A para-xylylene-based resin (poly-monochloro-paraxylylene) was formed to a thickness of 2.0 μm. After heating the paraxylylene dimer, a high-temperature pyrolyzate is used as a radical monomer, which is polymerized on Al ₂ O ₃ to form a paraxylylene resin film with extremely low moisture permeability. The solid-state imaging element chip in which the photoelectric conversion element was sealed with these sealing films was further sealed with a glass plate in the same manner as in Example 1. As a result, by providing the sealing film, the durability could be further improved as compared with the solid-state imaging device of Example 1.

  In Example 3, the sealing film has a two-layer structure of a metal oxide film and a paraxylylene resin film. However, even if only one of the structures is used, the durability can be improved. .

Next, the dark current suppression effect by setting the work function of the electrode for extracting electrons described in the above embodiment to 4.5 eV or less will be proved.
(Comparative Example 1)
A glass substrate (commercially available) on which an ITO lower electrode having a thickness of 250 nm is laminated (work function 4.8 eV obtained by an atmospheric photoelectron spectrometer AC-2 manufactured by Riken Keiki Co., Ltd .; visible light transmittance of about 90%) On top of this, quinacridone with a thickness of 100 nm and an Al upper electrode with a thickness of 100 nm (work function 4.3 eV; visible light transmittance 0%) are sequentially stacked by vacuum deposition, and electrons are collected on the ITO lower electrode side. Take the case as an example. As a result of actual device fabrication and measurement with an element area of 2 mm × 2 mm, the dark current was 9.3 μA / cm ² when a voltage of 1 V was applied (electron collection with the lower electrode as a positive bias, and so on).
In this case, since the work function of the ITO lower electrode, which is an electrode for extracting electrons, is large, holes are likely to be injected from the ITO lower electrode to quinacridone when a bias voltage is applied, and the dark current is considered to increase.

Example 4
On the other hand, an element similar to that of Comparative Example 1 was prepared except that In having a small work function of 4.3 eV was formed between the ITO lower electrode and quinacridone by 2 nm vacuum deposition (the visible light transmittance of 2 nm In was about 98%). As a result, the dark current when a voltage of 1 V was applied was greatly suppressed by 1.8 nA / cm ² and about 4 digits. This indicates that hole injection from the electrode for extracting electrons is greatly suppressed by reducing the work function of the lower electrode, which is an electrode for extracting electrons. Similarly, when light of 550 nm was incident from the lower ITO side at an irradiation intensity of 50 μW / cm ² under the 1 V bias application condition, the external quantum efficiency (measured charge number relative to the number of incident photons) was 12%. When a bias voltage of 2 V was applied, the dark current was about 100 nA / cm ² and the external quantum efficiency was 19%.

  In Comparative Example 1 and Example 4, the smooth layer is not provided, but the same effect can be obtained when the smooth layer is provided.

1 is a schematic cross-sectional view showing a schematic configuration of a solid-state imaging device package for explaining an embodiment of the present invention. 1 is a schematic plan view showing a schematic configuration of the solid-state imaging device chip shown in FIG. FIG. 2 is a schematic cross-sectional view showing a schematic configuration of one pixel shown in FIG. Enlarged view of the photoelectric conversion element shown in FIG. FIG. 3 is a schematic cross-sectional view illustrating a schematic configuration of one pixel illustrated in FIG. 2 and illustrates a first modification example. It is a cross-sectional schematic diagram which shows schematic structure of one pixel shown in FIG. 2, and is a figure which shows a 2nd modification. FIG. 5 is a schematic cross-sectional view illustrating a schematic configuration of one pixel illustrated in FIG. 2 and illustrates a third modification example. Partial cross-sectional schematic diagram of the solid-state imaging device chip fabricated in Example 1 The figure which shows the output result at the time of dark when the bias voltage applied to the upper electrode of the solid-state image sensor chip | tip of Example 1 is 0.5V, 2.5V, and 4.0V. The figure which shows an imaging result when the bias voltage applied to the upper electrode of the solid-state image sensor chip of Example 1 is 0.5V, 2.5V, and 4.0V. The figure which shows an imaging result when the bias voltage applied to the upper electrode of the solid-state image sensor chip of Example 1 is 0.5V, 2.5V, and 4.0V. The figure which shows the image pick-up result when the bias voltage applied to an upper electrode is 1.5V in the solid-state image sensor chip | tip of Example 2, and it imaged a gray scale chart. The figure which shows the imaging result when the bias voltage applied to an upper electrode is 0.5V in the solid-state image sensor chip | tip of Example 1, and imaged a gray scale chart. The figure which shows the measurement result of the photocurrent and dark current which are each output from the photoelectric conversion element which carried out glass sealing, and the photoelectric conversion element which does not carry out glass sealing The figure which shows the action | operation spectrum of the photoelectric conversion element which carried out glass sealing, and the photoelectric conversion element which does not carry out glass sealing

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Package main body 200 Solid-state image sensor chip 400 Glass plate 200b Pixel 1 Silicon substrate 6 High concentration impurity region 7 Insulating layer 9 Connection part 11a, 11b Lower electrode 12 Middle layer 13 Upper electrode 15 Sealing film 122 Organic photoelectric conversion layer 123 Smooth layer

Claims (27)

A photoelectric conversion comprising a lower electrode formed above a semiconductor substrate, an upper electrode formed above the lower electrode, and an intermediate layer including an organic photoelectric conversion layer formed between the lower electrode and the upper electrode A solid-state imaging device comprising: an element; and a signal readout unit that reads out a signal corresponding to a signal charge generated in the photoelectric conversion element,
When imaging is performed by applying a bias voltage of 0.1 V or more and 3 V or less between the lower electrode and the upper electrode, the external quantum efficiency in the wavelength region of light absorbed by the organic photoelectric conversion layer is 1% or more A solid-state imaging device. The solid-state imaging device according to claim 1,
A solid-state imaging device in which the upper electrode is a transparent electrode. The solid-state imaging device according to claim 2,
A solid-state imaging device in which the lower electrode is a transparent electrode. The solid-state imaging device according to claim 2 or 3,
The solid-state image sensor whose material of the said transparent electrode is a transparent conductive oxide. The solid-state imaging device according to claim 4,
A solid-state imaging device in which the transparent conductive oxide is ITO. The solid-state imaging device according to any one of claims 1 to 5,
A solid-state imaging device in which the organic photoelectric conversion layer includes a material of any one of a quinacridone skeleton, a phthalocyanine skeleton, and an anthraquinone skeleton. It is a solid-state image sensing device according to any one of claims 1 to 6,
The solid-state image sensor whose average surface roughness Ra of the surface by the side of the said upper electrode of the said intermediate layer is 1 nm or less. The solid-state imaging device according to any one of claims 1 to 7,
A solid-state imaging device having a thickness of the intermediate layer of 150 nm or more. The solid-state imaging device according to any one of claims 1 to 8,
The solid-state image sensor whose work function of the electrode for taking out the electron which generate | occur | produced in the said organic photoelectric converting layer is 4.5 eV or less among the said upper electrode and the said lower electrode. The solid-state imaging device according to claim 9,
The electrode for extracting electrons has a two-layer structure of a transparent electrode and a metal thin film having a work function of 4.5 eV or less,
The metal thin film is a solid-state imaging device positioned between the intermediate layer and the transparent electrode. The solid-state imaging device according to claim 10,
A solid-state imaging device in which the metal thin film is made of In. The solid-state imaging device according to claim 11,
A solid-state imaging device having a thickness of In of 0.5 to 10 nm. The solid-state imaging device according to any one of claims 1 to 12,
A solid-state imaging device comprising a sealing film that is formed on the photoelectric conversion element and seals the photoelectric conversion element. The solid-state imaging device according to claim 13,
A solid-state imaging device in which the sealing film is formed by an atomic layer deposition (ALD) method. The solid-state imaging device according to claim 13 or 14,
A solid-state imaging device in which a material of the sealing film contains a metal oxide. The solid-state imaging device according to claim 15,
The solid-state imaging device wherein the metal oxide is _Al 2 _{O 3.} The solid-state imaging device according to claim 15 or 16,
The solid-state imaging device in which the sealing film has a two-layer structure of a film made of the metal oxide and a film made of a polymer compound formed on the film made of the metal oxide. The solid-state imaging device according to claim 17,
A solid-state imaging device in which the polymer compound is a paraxylylene resin. The solid-state imaging device according to claim 1,
A solid-state imaging device in which the photoelectric conversion device is glass-sealed in a package body in an inert gas atmosphere. The solid-state imaging device according to claim 19,
A solid-state imaging device in which the concentration of oxygen contained in the inert gas is 0.05% or less. The solid-state imaging device according to claim 19 or 20,
The solid-state image sensor whose dew point of the said inert gas is -75 degrees C or less. The solid-state imaging device according to any one of claims 1 to 21,
A solid-state imaging device in which the signal readout unit is a CMOS circuit. It is a solid-state image sensing device according to any one of claims 1 to 22,
A solid-state imaging device including an in-substrate photoelectric conversion unit that absorbs light transmitted through the organic photoelectric conversion layer of the photoelectric conversion element, generates a charge corresponding to the light, and accumulates the charge in the semiconductor substrate. The solid-state imaging device according to claim 23,
The solid-state imaging device, wherein the in-substrate photoelectric conversion unit is two photodiodes that absorb light of different colors stacked in the semiconductor substrate. The solid-state imaging device according to claim 23,
The solid-state image sensor which is two photodiodes in which the said photoelectric conversion part in a board | substrate absorbs the light of a respectively different color arranged in the direction perpendicular | vertical with respect to the incident direction of the incident light in the said semiconductor substrate. The solid-state imaging device according to claim 24 or 25,
A photoelectric conversion element in which the two photodiodes absorb light in a wavelength region of red, blue, or green, respectively. It is a solid-state image sensing device according to any one of claims 1 to 22,
A solid-state imaging device in which a plurality of the photoelectric conversion elements are stacked above the semiconductor substrate.