JP2007310613A - Apparatus and method for determining adequacy of ip, ip, and semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an apparatus or the like for determining the adequacy of an IP capable of efficiently providing support for the selection of an IP for the design of LSI. <P>SOLUTION: The adequacy determining apparatus 10 includes a comparison part 12 which, upon a request from an input part 20, obtains from a second holding part 13 a version allocated to a particular IP, and which upon a request from the input part 20 obtains from a first holding part 11 the matching version of a particular IP incorporated into particular LSI so as to compare both versions; a comparison result management part 14 for managing the result of comparison by the comparison part 12; and an output part 15 for outputting the result of comparison in the comparison result management part 14 to a display part 30. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an IP (Intellectual Property) module suitability determination device.

A system LSI (Large Scale Integration) generally includes a CPU, a memory, and an IP (Intellectual Property) module. There are various types of IP such as an input / output circuit, a data processing circuit, and a DMA (Direct Memory Access) circuit. Various types of IP are assigned to such IPs depending on the development time and development form.
For this reason, in LSI design, an IP having an appropriate version must be selected according to the configuration of the LSI. If an IP having an inappropriate version is mounted on an LSI, the function of the LSI will be hindered.
Under such circumstances, a method for managing versions of a library for LSI design tools in a unified manner has been disclosed (for example, Patent Document 1).

JP 2001-67393 A

However, with the method disclosed in Patent Document 1, the version of the library can be managed in a unified manner, but the suitability of the IP version cannot be automatically determined during LSI design. Therefore, there has been a problem that IP selection in LSI design cannot be performed efficiently.
The present invention has been made to solve the above-described problems, and an object thereof is to efficiently support IP selection in LSI design.

  In order to achieve the above object, the present invention provides an IP suitability judging apparatus for judging suitability of an IP version incorporated in an LSI to be designed in response to a request from an information input unit. A first holding unit that holds a compatible version of the IP to be incorporated, a second holding unit that holds a version assigned to the IP, and a specific IP assigned in response to a request from the input unit The version is acquired from the second holding unit, and in response to a request from the input unit, a compatible version of the specific IP incorporated in the specific LSI is acquired from the first holding unit and acquired. A comparison unit that compares both versions and an output unit that outputs a comparison result of the comparison unit to the outside are included.

  In order to achieve the above object, the present invention is an IP suitability determination method using a computer for judging suitability of an IP version incorporated in an LSI to be designed in response to a request from an information input unit. The computer includes a first holding unit that holds a compatible version of the IP incorporated in the LSI, and a second holding unit that holds a version assigned to the IP. In response to a request from the input unit, the version assigned to the specific IP is acquired from the second holding unit, and the specific IP incorporated in the specific LSI in response to the request from the input unit Acquiring a compatible version from the first holding unit, comparing the acquired versions, and comparing And including the steps of outputting to the outside the results.

  According to the present invention, it is possible to efficiently support IP selection in LSI design.

(Embodiment 1)
FIG. 1 is a diagram illustrating a configuration example of an IP suitability determination apparatus 10 according to Embodiment 1 of the present invention.
In FIG. 1, the suitability determination device 10 includes a first holding unit 11, a comparison unit 12, a second holding unit 13, a comparison result management unit 14, and an output unit 15. An input unit 20 is connected to the suitability determination device 10, and a display unit 30 is connected to the output unit 15. Below, although the suitability determination apparatus 10 demonstrates as a personal computer, for example, it is not restricted to this. For example, the suitability determination device 10 may be realized by an LSI or may be made into one chip. Alternatively, an FPGA (Field Programmable Gate Array) may be applied.

The first holding unit 11 holds in advance a compatible version of the IP incorporated in the LSI to be designed. Specifically, as shown in FIG. 2, the first holding unit 11 holds items of LSI, IP, and version ID (version) in association with each other on the table.
In the LSI item, identification information for specifying the LSI to be designed is held. For example, a design ID or the like is used for the identification information.
The IP item holds identification information for specifying the IP. For example, a module ID or the like is used for the identification information. IP includes, for example, input / output circuits, data processing circuits, DMA (Direct Memory Access) circuits, image processing circuits such as MPEG (Moving Picture Expert Group), and communication circuits such as USB (Universal Serial Bus). .
In the version ID item, an ID for specifying a version conforming to the IP is held. In this way, a version conforming to the IP is defined for each LSI to be designed.

  The second holding unit 13 holds in advance the version assigned to the IP to be incorporated. Specifically, as shown in FIG. 3, the second holding unit 13 holds items of IP and version ID in association with each other on the table. These items are the same as the contents of the IP and version ID items shown in FIG. In this way, at the time of designing an LSI, the version assigned to the IP to be incorporated into the LSI is defined.

The comparison unit 12 compares the IP version ID held in the first holding unit 11 and the IP version ID held in the second holding unit 13 with respect to the LSI requested to be selected from the input unit 20. . The input unit 20 is for inputting information, and corresponds to, for example, a mouse, a keyboard, an operation button, and the like.
Then, the comparison unit 12 registers the comparison result in the comparison result management unit 14. An example of this registration is shown in FIG.
In FIG. 4, items of LSI, IP, and comparison result are associated with each other. The comparison result item holds a comparison result (“◯”) indicating a match or a comparison result (“×”) indicating a mismatch. In the case of the comparison result indicating coincidence, it indicates that the version of the IP to be incorporated is appropriate.
In FIG. 4, the items of LSI and IP are the same as the contents of the items of LSI and IP shown in FIG.

  Returning to FIG. 1, the output unit 15 outputs the comparison result (see FIG. 4) registered in the comparison result management unit 14, that is, the comparison result in the comparison unit 12 to the display unit 30. The display unit 30 is for displaying information, and corresponds to, for example, a computer display.

The first holding unit 11, the second holding unit 12, and the comparison result management unit 14 use storage devices such as a ROM, a RAM, and a hard disk device, for example.
The comparison unit 12 and the output unit 15 operate using a processing device (computer) such as a CPU according to a management program stored in a storage device. The management program may be recorded on a computer-readable recording medium (CD-ROM or the like).

Next, a processing example of the suitability determination apparatus 10 will be described with reference mainly to FIG. Here, in the case of LSI logic / circuit design or layout design, a case where the suitability of the IP version incorporated in a specific LSI is automatically determined in response to a selection request from the input unit 20 will be described as an example.
In this case, the designer first uses the input unit 20 to select an IP to be incorporated into the LSI to be designed. As this selection method, for example, there is a method of directly inputting the identification information of the LSI and the IP incorporated therein. Alternatively, there is a method of clicking on a specific LSI and IP from a list showing a plurality of LSIs and IPs.

Then, the comparison unit 12 of the suitability determination apparatus 10 acquires a version ID compatible with the IP incorporated in the specific LSI from the first holding unit 11 (see FIG. 2) by the selection by the input unit 20. Furthermore, the comparison unit 12 acquires the version ID assigned to the specific IP from the second holding unit 13 (see FIG. 3) by the selection by the input unit 20.
Subsequently, the comparison unit 12 compares the version ID acquired from the first holding unit 11 with the version ID acquired from the second holding unit 13. Then, the comparison unit 12 registers the comparison result indicating whether the version IDs match or do not match with the IP of the LSI in the comparison result management unit 14 (see FIG. 4).

  Next, the output unit 15 outputs the comparison result registered in the comparison result management unit 14 to the display unit 30. Specifically, the output unit 15 acquires the comparison result from the comparison result management unit 14 in association with the IP of the LSI, and outputs it to the display unit 30. As a result, the designer can check the comparison result (version match or mismatch) for each IP through the display unit 30. Note that the output unit 15 may output only a comparison result indicating either a match or a mismatch among all the comparison results. Then, for an IP whose version does not match, the designer may select another IP again using the input unit 20, for example.

As described above, according to the first embodiment, the suitability determination device 10 acquires a version assigned to a specific IP from the second holding unit 13 in response to a request from the input unit 20 and In response to the request, the compatible version ID of the specific IP incorporated in the specific LSI is acquired from the first holding unit 11. Then, the suitability determination device 10 compares both the acquired versions, and outputs the comparison result to the external display unit 30. For this reason, the suitability of the IP version is confirmed through the comparison result.
Therefore, for example, in both logic / circuit design and layout design, the designer can easily select an IP having an appropriate version. Therefore, for example, it is possible to avoid the manufacture of an LSI equipped with an inappropriate version of IP.

(Embodiment 2)
The second embodiment is for designing an LSI including an IP incorporated in a hierarchy. Specifically, the IP in the first embodiment (this is also referred to as “upper layer IP”) is a different IP.
(This is also referred to as “lower layer IP”) and LSI is designed. Therefore, in the second embodiment, the IP in the first embodiment is replaced with the upper layer IP and applied.
FIG. 5 is a diagram showing a configuration example of an IP suitability determination apparatus 10A according to Embodiment 2 of the present invention. Note that the same parts as those of the first embodiment are denoted by the same reference numerals as those of the first embodiment, and redundant description is omitted.
In FIG. 5, the suitability determination device 10 </ b> A further includes a third holding unit 16, a second comparison unit 17, and a fourth holding unit 18. The suitability determination device 10A includes a comparison result management unit 14A instead of the comparison result management unit 14 shown in FIG. Other configurations of the suitability determination device 10A are substantially the same as those of the suitability determination device 10 shown in FIG. Therefore, the following description will mainly focus on the differences from the first embodiment.

  The first holding unit 11 holds in advance a version compatible with the upper layer IP for each LSI to be designed. Specifically, as shown in FIG. 6, the first holding unit 11 holds the items of LSI, upper layer IP, and version ID in association with each other on the table. These items have the same contents as the items shown in FIG. In this way, a version compatible with the upper layer IP is defined for each LSI to be designed.

  The third holding unit 16 holds in advance a version that conforms to the lower layer IP incorporated in the upper layer IP. Specifically, as shown in FIG. 7, the third holding unit 16 holds the items of the upper layer IP, the lower layer IP, and the version ID in association with each other on the table. The version ID here is an ID for specifying the version of the lower layer IP. In this way, the version of the lower layer IP incorporated in the upper layer IP is defined. As described above, in the present embodiment, by combining the first holding unit 11 and the third holding unit 16, a version that conforms to the IP incorporated in each of the upper layer and the lower layer is held for each LSI. .

  The fourth holding unit 18 holds the version of the lower layer IP to be incorporated. Specifically, the second holding unit 13 holds the items of the lower layer IP and its version ID in association with each other on the table (see FIG. 3).

  The second comparison unit 17 relates to the LSI specified by the input unit 20, the lower layer IP version held in the third holding unit 16, and the lower layer IP version held in the fourth holding unit 18. Compare Then, the second comparison unit 17 registers the comparison result in the comparison result management unit 14A. Thereby, in addition to the comparison result in the first comparison unit 12 (similar to the first embodiment), the comparison result in the second comparison unit 17 is also registered in the comparison result management unit 14A. That is, in the comparison result management unit 14A, version comparison results for both the upper layer and lower layer IPs are registered for the LSI to be designed (see FIG. 4).

  Note that the third holding unit 16, the fourth holding unit 18, and the comparison result management unit 14A use storage devices such as a ROM, a RAM, and a hard disk device, for example. The second comparison unit 17 uses a processing device such as a CPU. Similarly to the first comparison unit 12 and the output unit 15, the second comparison unit 17 also operates according to a management program stored in the storage device.

Next, a processing example of the suitability determination device 10A will be described with reference to FIG. Here, the case where the suitability of the version of the IP (both upper layer and lower layer) selected by the input unit 20 in the logic / circuit design or layout design of the LSI is described as an example.
In this case, the designer first uses the input unit 20 to select a specific layer IP (for example, both the upper layer and the lower layer) to be incorporated into the LSI to be designed. As this selection method, for example, a specific LSI and IP can be selected from a list including a plurality of LSIs and IPs (both upper and lower layers) by directly inputting IP identification information of a certain layer. There is a way to click.

Then, in step 101, the second comparison unit 17 of the suitability determination device 10A compares the version of the lower layer IP incorporated in the LSI requested to be selected by the input unit 20. Specifically, the second comparison unit 17 first sets the compatible version ID of the lower layer IP corresponding to the upper layer IP of the LSI requested to be selected by the input unit 20 to the third holding unit 16 (see FIG. 7). ) Subsequently, the second comparison unit 17 acquires the version ID assigned to the lower layer IP requested to be selected by the input unit 20 from the fourth holding unit 13 (see FIG. 3).
Then, the second comparison unit 17 compares the version ID acquired from the third holding unit 16 with the version ID acquired from the fourth holding unit 13.

  In step 102, the second comparison unit 17 registers, in the comparison result management unit 14A, the comparison result indicating the match or mismatch of the version ID of the lower layer IP in association with the lower layer IP of the LSI. (See FIG. 4).

  In step 103, the second comparison unit 17 determines whether comparison has been performed for all lower layer IPs requested to be selected by the input unit 20. As a result, when the comparison is not completed (No in Step 103), the process returns to Step 101. On the other hand, when the comparison is completed (Yes in Step 103), the second comparison unit 17 proceeds to Step 104. In this way, version IDs are compared for all lower layer IPs.

In step 104, the first comparison unit 12 compares versions compatible with the upper layer IP incorporated in the LSI requested to be selected by the input unit 20. Specifically, the first comparison unit 12 first obtains from the first holding unit 11 (see FIG. 6) a version ID that matches the upper layer IP incorporated in the LSI requested to be selected by the input unit 20. Subsequently, the first comparison unit 12 acquires the version ID assigned to the upper layer IP selected by the input unit 20 from the second holding unit 13 (see FIG. 3).
Then, the first comparison unit 12 compares the version ID acquired from the first holding unit 11 with the version ID acquired from the second holding unit 13.

  In step 105, the first comparison unit 12 registers, in the comparison result management unit 14A, the comparison result indicating the match or mismatch of the version ID of the upper layer IP by associating with the upper layer IP of the LSI. (See FIG. 4). As a result, the comparison result regarding both the upper layer and lower layer IPs is registered in the comparison result management unit 14A.

  Thereafter, the output unit 15 outputs the comparison result registered in the comparison result management unit 14 </ b> A to the display unit 30. Specifically, the output unit 15 outputs all the comparison results for the LSI IP (both upper layer and lower layer) requested to be selected by the input unit 20. As a result, the designer can check the comparison result (match or mismatch) for each IP through the display unit 30.

  In FIG. 8, the suitability determination apparatus 10A has been described with respect to the case where the IP version IDs are compared in the order of the lower layer and the upper layer (see steps 101 and 104 in FIG. 8). Not exclusively. For example, the version IDs may be compared in the order of the upper layer and the lower layer.

As described above, according to the second embodiment, the suitability determination device 10A acquires the version assigned to the IP of a specific layer (for example, an upper layer) from the second holding unit 13, and for the specific LSI, A version conforming to the IP of the hierarchy is acquired from the first holding unit 11. Then, the suitability determination device 10 </ b> A compares the two versions and outputs the comparison result to the display unit 30. For this reason, the suitability of the IP version incorporated in the upper layer is also shown through the comparison result.
Furthermore, the suitability determination device 10A obtains a version assigned to a specific layer (for example, lower layer) IP from the fourth holding unit 18, and for a specific LSI, obtains a version that conforms to the IP of the layer. 3 Obtained from the holding unit 16, compares the two versions, and outputs the comparison result to the display unit 30. Therefore, the suitability of the IP version incorporated in the lower layer is also shown through the comparison result.
Therefore, it is possible to confirm the suitability of the IP version incorporated in all layers.

[Modification of Appropriateness Determination Device]
Next, a modified example of the suitability determination device 10A will be described. In the second embodiment, the suitability determination device 10A includes two first comparison units 12 and a second comparison unit 17 (see FIG. 5), and the two comparison units 12 and 17 each provide an IP version ID. Although the case of comparison has been described, for example, the first comparison unit 12 may compare the version IDs of all IPs.
In this case, as shown in FIG. 9, in the suitability determination device 10A, one first holding unit 11 also has the function of the third holding unit 16, and further, one first comparison unit 12 is a second comparison unit. It has 17 functions. Specifically, the first holding unit 11 holds the tables shown in FIG. 6 and FIG. 7, so that version IDs suitable for IP incorporated in a hierarchy (upper layer and lower layer) are provided for each LSI. Hold. And the 1st comparison part 11 performs all the processes from step 101 to 105 shown in FIG. Even if it does in this way, the effect similar to Embodiment 2 can be acquired. In FIG. 8, the second holding unit 13 may have the function of the fourth holding unit 18.

(Embodiment 3)
In the third embodiment, the version ID (see the first and second embodiments) is incorporated into the IP (hardware) actually manufactured by the LSI design.
FIG. 10 is a diagram illustrating a configuration example of the LSI 200 including the IP 210. In FIG. 10, the LSI 200 includes a plurality of IP 201, CPU 202, and memory 203. The IP 201 includes an internal circuit 210 (circuit data) and a recording unit 211 that records a version ID assigned to the internal circuit 210 in advance. The version ID here is also associated with the identification information of the IP (corresponding to the value of the IP item in FIG. 3).
The internal circuit 210 is a circuit necessary for the function of the IP, and corresponds to, for example, a controller. The internal circuit 210 holds circuit data necessary for the internal circuit.
For example, when the IP 200 is a ROM, the version ID of the recording unit 211 may be included in ROM data (including a program). In this way, when the ROM data is read out by the CPU 202, the version ID is also read from the recording unit 211 in association with the identification information of the IP. Then, the same procedure as in the first and second embodiments (for example, the CPU 202 implements the functions of the units 12 and 15 in FIG. 1 and the memory 203 implements the functions of the units 11 and 14 in FIG. 1). Then, the suitability of the version ID is determined (see FIG. 8 and the like). In this case, it is useful because the version of the IP as hardware can be verified.
Further, a semiconductor element (such as an IC chip) may be designed using an IP including the circuit data described above and the version ID of the circuit data.

The present invention is not limited to the above embodiment. In the first and second embodiments, the hardware configuration and data structure (see FIGS. 2 to 4, 6, and 7) of the suitability determination device may be changed without departing from the spirit of the present invention. For example, the suitability determination device may perform distributed processing by combining a plurality of computers.
Furthermore, in the second embodiment, the case has been described in which the IP is incorporated into two layers of an upper layer and a lower layer, but the number of layers may be three or more.

It is a figure which shows the structural example of the IP suitability determination apparatus which concerns on Embodiment 1 of this invention. It is a figure which shows the data holding example of the 1st holding | maintenance part of FIG. It is a figure which shows the data holding example of the 2nd holding | maintenance part of FIG. It is a figure which shows the data registration example of the comparison result management part of FIG. It is a figure which shows the structural example of the IP suitability determination apparatus which concerns on Embodiment 2 of this invention. FIG. 6 is a diagram illustrating a data holding example of a first holding unit in FIG. 5. FIG. 6 is a diagram illustrating a data holding example of a third holding unit in FIG. 5. It is a figure which shows the process example of the suitability determination apparatus of FIG. It is a figure which shows the modification of the suitability determination apparatus of FIG. It is a figure which shows the structural example of LSI including IP.

Explanation of symbols

10, 10A Appropriateness determination device 11 First holding unit 12 Comparison unit 13 Second comparison unit 14 Comparison result management unit 15 Output unit 20 Input unit 30 Display unit 200 LSI
201 IP
210 Internal circuit 211 Recording unit

Claims (9)

In accordance with a request from an information input unit, an IP suitability judging device for judging suitability of an IP (Intellectual property) version incorporated in an LSI to be designed,
A first holding unit for holding a compatible version of the IP incorporated in the LSI;
A second holding unit for holding a version assigned to the IP;
In response to a request from the input unit, a version assigned to a specific IP is acquired from the second holding unit, and in response to a request from the input unit, the specific IP incorporated in a specific LSI A matching unit that obtains a compatible version from the first holding unit and compares the obtained two versions;
An output unit for outputting a comparison result in the comparison unit to the outside;
IP suitability determination device including When the IP is hierarchically incorporated into the LSI,
The first holding unit holds, for each LSI, a version that conforms to the IP incorporated in the hierarchy,
When comparing the two versions, the comparison unit acquires a version assigned to a specific layer IP from the second holding unit, and conforms to the specific layer IP for the specific LSI. Obtaining a version from the first holding unit and comparing both obtained versions;
The IP suitability determination device according to claim 1.   The IP suitability determination apparatus according to claim 1, wherein the comparison result indicates that the version matches or does not match.   4. The IP suitability determination apparatus according to claim 1, wherein the IP is an input / output circuit, a data processing circuit, or a DMA (Direct Memory Access) circuit. An IP suitability determination method using a computer that judges the suitability of a version of an IP (Intellectual property) incorporated in an LSI to be designed in response to a request from an information input unit,
The computer
A first holding unit that holds a compatible version of the IP incorporated in the LSI, and a second holding unit that holds a version assigned to the IP,
In response to a request from the input unit, a version assigned to a specific IP is acquired from the second holding unit, and in response to a request from the input unit, the specific IP incorporated in a specific LSI Obtaining a compatible version from the first holding unit;
Comparing both of the obtained versions;
Outputting the result of the comparison to the outside;
An IP suitability determination method including: When the IP is hierarchically incorporated into the LSI,
The first holding unit holds, for each LSI, a version compatible with the IP incorporated in the hierarchy,
The computer
When comparing the two versions, the version assigned to the IP of a specific layer is acquired from the second holding unit, and the version compatible with the IP of the specific layer is acquired for the specific LSI. Obtain from the holding unit, and compare the obtained both versions,
The IP suitability determination method according to claim 5.   The IP suitability determination method according to claim 5 or 6, wherein the comparison result indicates that the version matches or does not match.   IP including circuit data and a version of the circuit data.   A semiconductor device designed using IP including circuit data and a version of the circuit data.

Images