JP2007306580A - Frequency synthesizer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a frequency synthesizer suitable for a radio system having frequency hopping. <P>SOLUTION: The frequency synthesizer has a multi-phase generating circuit for generating a multi-phase clock signal from an input clock signal, a control circuit 418 for generating a control signal for controlling the multi-phase clock generating circuit 414, and a generating circuit which inputs a plurality of multi-phase clock signals 415 output from the multi-phase clock generating circuit 414 and generates one output clock signal based upon the plurality of multi-phase clock signals 415. The multi-phase clock signal generating circuit 414 includes a plurality of phase interpolating circuits, which each input a first input signal having a first phase and a second input signal having a second phase and generate an output signal having a phase above the first phase and below the second phase in accordance with the first control signal 419 from the control circuit 418. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a frequency synthesizer, and more particularly to a frequency synthesizer used for frequency hopping and capable of switching frequencies at high speed.

  Conventionally, this type of frequency synthesizer is used because it can generate an output clock signal multiplied by the input clock frequency (for example, Non-Patent Document 1).

1998, RL Microelectronics, page 252 Figure 8.8 An example of such a first conventional frequency synthesizer is shown in FIG.

  As shown in FIG. 35, the conventional frequency synthesizer includes a phase comparator 1025, a charge pump circuit 1026, a low-pass filter 1027, a voltage controlled oscillator (VCO) 1028, and a frequency dividing circuit 1029.

  Next, the operation of the frequency synthesizer will be described.

  The phase comparator 1025 and the charge pump circuit 1026 inject or extract charge from the low-pass filter 1027 according to the frequency difference between the input clock signal 1021 and the output signal 1024 of the frequency divider circuit 1029. The input voltage 1022 of the VCO 1028 Feedback control is performed so that the frequency difference between the signal 1021 and the output signal 1024 of the frequency divider 1029 decreases.

  Subsequently, the VCO 1028 changes the frequency of the output clock signal 1023 according to the input voltage 1022. When the frequency difference between the input clock signal 1021 and the output signal 1024 of the divider circuit becomes 0, the circuit operates in a steady state. At this time, the frequency of the output clock signal 1023 is a frequency division ratio times the frequency of the input clock signal 1021.

  The second conventional frequency synthesizer is used by obtaining an output signal having a frequency of ω1 ± ω2 from an input signal having a frequency ω1 and an input signal having a frequency ω2 (for example, Non-Patent Document 2).

1998, RL Microelectronics, page 244 Fig. 7.46 Fig. 36 shows such a conventional second frequency synthesizer.

  As shown in FIG. 36, the conventional second frequency synthesizer includes a mixer 1103 and a band pass filter 1105.

  Next, the operation of the conventional second frequency synthesizer will be described.

  First, a first input signal 1101 having a frequency of ω1 and a second input signal 1102 having a frequency of ω2 are input to the mixer 1103 to obtain a mixer output signal 1104 having a frequency of ω1 ± ω2.

  Next, the mixer output signal 1104 is input to the bandpass filter 1105, and signals other than ω1 + ω2 or ω1-ω2 are removed to obtain an output signal 1106 of a bandpass filter having one spectrum peak.

  Further, as the conventional third frequency synthesizer, the output clock signal frequency is finely adjusted and switched at high speed (for example, Non-Patent Document 3).

1998, RL Microelectronics, pp. 285-289 Fig. 8.47 Fig. 37 shows such a conventional third frequency synthesizer.

  As shown in FIG. 37, the conventional third frequency synthesizer includes a counter circuit 1202 and a DA converter circuit 1204.

  Next, the operation of the conventional third frequency synthesizer will be described. The counter circuit 1202 counts the number of clocks of the input clock signal 1201. Subsequently, the output signal 1203 of the counter circuit is converted from a digital signal to an analog signal by the DA conversion circuit 1204 to generate an output clock signal 5. At this time, the cycle (frequency) of the output clock signal 1205 is switched by the control signal 1206 of the counter circuit.

  The first problem of the conventional frequency synthesizer described above is that the frequency of the output clock signal cannot be switched at high speed. The reason is that even if the frequency division ratio is switched or the frequency of the input clock signal is switched, feedback control is required a plurality of times until the frequency of the output clock signal reaches a steady state.

  The second problem of the conventional frequency synthesizer described above is that the frequency of the output signal cannot be switched to a wide band. The reason is that even if the frequency of the input signal is switched to switch the output frequency of the mixer, the center frequency of the bandpass filter cannot be switched in accordance with the output frequency of the mixer.

  Further, the third problem of the above-described conventional frequency synthesizer is that fine adjustment of the cycle of the output clock signal to be switched or the cycle length of the output clock signal to be switched cannot be made below the cycle of the input clock signal. is there. The reason is that the cycle of the output clock signal is determined only by the count number of the input clock signal.

  The present invention has been invented in view of the above problems, and an object of the present invention is to provide a frequency synthesizer that switches the frequency of an output clock signal at high speed.

  Another object of the present invention is to provide a frequency synthesizer that can switch the frequency of an output signal over a wide band.

  Further, the problem to be solved by the present invention is to provide a frequency synthesizer capable of making the fine adjustment of the cycle length of the output clock signal to be switched or the cycle length of the output clock signal to be switched to be equal to or less than the cycle of the input clock signal. It is to provide.

  The present invention for solving the above-described problems includes a multiphase clock signal generation circuit for generating a multiphase clock signal from a multiphase input signal, and a control circuit for generating a first control signal for controlling the multiphase clock signal generation circuit. A frequency synthesizer having a plurality of multiphase clock signals output from the multiphase clock signal generation circuit as input signals and generating a single output clock signal based on the plurality of multiphase clock signals. The multi-phase clock signal generation circuit has a plurality of phase interpolation circuits, and each of the phase interpolation circuits has a first input signal having a first phase and a second input signal having a second phase. And an output signal having a phase not less than the first phase and not more than the second phase according to the first control signal from the control circuit.

  The present invention for solving the above problems is a frequency synthesizer, which holds in advance input voltages corresponding to a plurality of output frequencies of the voltage controlled oscillation circuit, and switches these voltages to change the frequency of the voltage controlled oscillation circuit. It is characterized by being configured to switch.

  Further, the present invention for solving the above-mentioned problems is a frequency synthesizer, a frequency divider for dividing the frequency of the input, and a phase comparator and charge pump circuit for charging or extracting charges according to the frequency difference of the input A low-pass filter that converts the charge into a voltage, a voltage-controlled oscillator that changes an output frequency with respect to the voltage, a voltage holding circuit that holds an input voltage for a plurality of output frequencies of the voltage-controlled oscillator, and the low-pass filter And a switch for switching the holding voltage of the voltage holding circuit.

  In addition, the present invention that solves the above-described problem is a frequency synthesizer that holds in advance input currents corresponding to a plurality of output frequencies of a current-controlled oscillation circuit and switches these currents to switch the frequency of the current-controlled oscillation circuit. It is comprised as follows.

  Further, the present invention for solving the above problems is a frequency synthesizer, which divides a frequency of an input, a phase comparator and a charge pump circuit for introducing or extracting charges according to the input frequency difference, and A low-pass filter that converts the electric charge into a voltage, a voltage-current conversion circuit that converts the voltage into a current of a current control oscillator, a current control oscillator that changes an output frequency with respect to the input current, and a current control oscillator It has a current holding circuit that holds input currents for a plurality of output frequencies, and a switch that switches the holding current of the low-pass filter and the current holding circuit.

  In addition, the present invention that solves the above problems is a frequency synthesizer that holds in advance input voltages corresponding to a plurality of output frequencies of a voltage-controlled oscillation circuit, and switches these voltages to control by a feedback loop. It is configured to switch the frequency of the oscillation circuit.

  Further, the present invention for solving the above-mentioned problems is a frequency synthesizer, which is a phase comparator and charge pump circuit that inputs or extracts charges according to the frequency difference of the input, and a plurality of low-pass filters that convert the charges into voltage And a voltage-controlled oscillator that changes an output frequency with respect to the voltage, a frequency divider that divides the frequency of the input, and a switch that switches the low-pass filter.

  Further, the present invention for solving the above-mentioned problems is a frequency synthesizer, characterized in that the frequency characteristics of the band pass filter are switched in accordance with the frequency of the spectrum of the output signal of the mixer.

  Further, the present invention for solving the above-mentioned problems is a frequency synthesizer, which is a difference frequency signal between the frequency of the first input signal and the frequency of the second input signal, and the frequency of the first input signal and the second frequency. A mixer that outputs a signal having a frequency that is the sum of the input signal frequency, a switch that switches the frequency of the second input signal, and a difference between the frequency of the first input signal and the frequency of the second input signal. And a band-pass filter capable of switching a center frequency to a signal having a frequency or a signal having a sum of the frequency of the first input signal and the frequency of the second input signal.

  Further, the present invention for solving the above-mentioned problems is a frequency synthesizer, which is a difference frequency signal between the frequency of the first input signal and the frequency of the second input signal, and the frequency of the first input signal and the second frequency. A mixer that outputs a signal having a frequency that is the sum of the input signal frequency, a high-pass filter having a cutoff frequency characteristic at the frequency of the first input signal that is a fixed frequency, and a first input signal that is a fixed frequency. A low-pass filter having a cutoff frequency characteristic at a frequency, a switch for switching a frequency of the second input signal, a switch for switching an output signal of the high-pass filter, and an output signal of the low-pass filter, To do.

  Also, the present invention for solving the above-mentioned problems is a frequency synthesizer, wherein a switch for selecting and outputting any one of a plurality of signals, an input signal and an output signal of the switch are input, and the input A mixer that outputs a signal having a frequency difference between the frequency of the signal and the output signal of the switch, a signal having a frequency that is the sum of the frequency of the input signal and the frequency of the output signal of the switch, and the mixer And a band-pass filter that allows the center frequency to be switched to a difference frequency signal or a sum frequency signal to be output and allows either one of the signals to pass therethrough.

  The present invention for solving the above-mentioned problems is a frequency synthesizer, characterized in that a plurality of multi-phase clock signals generated from an input clock signal are switched at a constant phase interval to generate an output clock signal. .

  The present invention for solving the above problems is a frequency synthesizer, a multiphase clock signal generation circuit for generating a multiphase clock signal from an input clock signal, and an output clock signal by selecting the multiphase clock signal. And a control circuit for generating a control signal for selecting the multiphase clock signal.

  Further, the present invention for solving the above-mentioned problems is a frequency synthesizer, which receives a multiphase clock signal and generates a clock signal that can be switched in finer phase increments, and generates a control signal in the cycle of the clock signal. A plurality of pulse generation circuits having an accumulator circuit that performs switching, and a gate circuit that switches passage or blocking of the clock signal by the control signal, and a circuit that calculates pulses output from the plurality of pulse generation circuits. Features.

  According to the frequency synthesizer of the present invention described above, the frequency of the output clock signal can be switched at high speed.

  Further, according to the above-described frequency synthesizer of the present invention, the frequency of the output signal can be switched over a wide band.

  Further, according to the above-described frequency synthesizer of the present invention, it is possible to finely adjust the cycle of the output clock signal to be switched or the cycle length of the output clock signal to be switched to be equal to or less than the cycle of the input clock signal.

  Also, the frequency synthesizer of the present invention can obtain the output of the frequency synthesizer by simply adding the outputs of each pulse generation circuit by incorporating an accumulator in each pulse generation circuit.

  The frequency synthesizer of the present invention includes a voltage holding circuit that holds input voltages corresponding to a plurality of output frequencies of the VCO, and a switch that switches between these voltages and the output voltage of the low-pass filter. By adopting such a configuration and switching the input voltage of the VCO without using feedback control, the object of the present invention can be achieved.

  The frequency synthesizer of the present invention can achieve the object of the present invention by switching the center frequency of the bandpass filter.

  The frequency synthesizer of the present invention includes a circuit that generates a multiphase clock signal from an input clock signal or a signal obtained by dividing the input clock signal, a circuit that selects these multiphase clock signals and generates an output clock signal, and A circuit for generating a selection signal of the circuit. By adopting such a configuration, the period of the input clock signal is divided by a plurality of multiphase clock signals, and the resolution of these ticks is used to achieve the object of the present invention.

  Embodiment 1 of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing Embodiment 1 of the present invention.

  As shown in FIG. 1, the frequency synthesizer according to the first embodiment of the present invention includes a phase comparator 8 and a charge pump circuit for charging or extracting charges according to the frequency difference between the input clock signal 1 and the output signal 4 of the frequency dividing circuit. 9, a low-pass filter 11 that converts this electric charge into a voltage, a voltage controlled oscillator (VCO) 13 that changes an output frequency with respect to this voltage, a frequency divider 14 that divides an input frequency, and a plurality of VCOs 13 A voltage holding circuit 10 that holds an input voltage corresponding to the output frequency, and a switch 12 that switches a holding voltage of the low-pass filter 11 and the voltage holding circuit 10 are provided.

  Next, a specific configuration of the voltage holding circuit 10 will be described in detail with reference to the drawings.

  FIG. 2 is a block diagram showing the circuit configuration of the voltage holding circuit 10 and is a diagram specifically showing the voltage holding circuit 10.

  As shown in FIG. 2, the voltage holding circuit 10 selects a first buffer 52, a second buffer 53, a third buffer 54, and an output signal of the buffer, to which the monitored voltage 51 is input. 1 switch 55, second switch 56, third switch 57, first capacitor 58 holding the output voltage of the buffer, second capacitor 59, and third capacitor 60. The

  FIG. 3 is a specific circuit diagram of the buffers 52 to 54 used in the voltage holding circuit 10 according to the first embodiment of the present invention. As shown in FIG. 3, the buffers 52 to 54 are configured by connecting the input voltage 71 to the plus terminal of the operational amplifier 72 and connecting the output voltage 73 to the minus terminal.

  Next, the operation in the above configuration will be described in detail with reference to the drawings.

  First, in FIG. 1, the switch 12 is switched to the output signal 2 of the low-pass filter 11 to operate the loop of the phase comparator 8, the charge pump circuit 9, the VCO 13, and the frequency divider circuit 14. Then, this loop is operated until the frequency of the output clock signal is stabilized. At this time, the switch 15 is turned on and the output signal 2 of the low-pass filter 11 is input to the voltage holding circuit 10. At this time, for example, the first switch 55 is turned on, and the signal (monitor voltage 51) input to the voltage holding circuit 10 is input to the first buffer 52, and the first holding voltage that is a function of the monitor voltage 51 is obtained. 61 is held in the first capacitor 58.

  Next, in FIG. 1, the frequency 1 of the input clock signal or the frequency dividing ratio of the frequency dividing circuit 14 is changed to stabilize at a different frequency of the output clock signal. At this time, the voltage holding circuit 10 holds the holding voltage 62 in the second capacitor 59 by turning off the first switch 55 and turning on the second switch 56 in FIG.

  By repeating these operations, a voltage corresponding to the frequency of the VCO 13 is held in each capacitor of the voltage holding circuit 10. The voltage supply operation to the capacitors 58, 50, and 60 described above is performed when the transmitter or receiver using the present embodiment interrupts the transmission / reception operation. During the transmission / reception operation, the frequency of the output clock signal 3 is switched by switching the switch 12 to each holding voltage to be the input voltage of the VCO 13. At this time, the switch 15 is off.

  In FIG. 2, the buffers 52 to 54 preferably output a voltage equal to the monitor voltage 51 and hold the voltage in the capacitors 58 to 60. This is because when there is a difference between the monitor voltage 51 and the output voltage of the buffer, when the monitor voltage 51 is the input voltage of the VCO 13 and when the holding voltage of the capacitors 58 to 60 is the input voltage of the VCO 13, This is because the frequency of the signal 3 is different.

  Further, it is preferable that the input impedance of the buffer is large. This is because the monitor voltage 51 varies when the input impedance is small.

  Next, an application example of the frequency synthesizer of the present invention will be described.

  The frequency synthesizer of the present invention holds voltages corresponding to a plurality of output frequencies of the VCO 13 and can switch frequencies at high speed by switching the voltages.

  An application example of the frequency synthesizer of the present invention will be described with reference to the drawings.

  FIG. 4 is a diagram showing an application example of the frequency synthesizer of the present invention. The frequency synthesizer 217 of the present invention is effective in a radio system that performs frequency hopping as shown in FIG.

  In FIG. 4, an antenna output signal 212 via an antenna 211 is amplified by a low noise amplifier (LNA) 213, and the mixer 215 receives a mixer output signal from the LNA output signal 214 and the output clock signal 216 of the frequency synthesizer 217. 218 is generated.

  Next, the operation of the frequency synthesizer 217 will be described with reference to the drawings.

  FIG. 5 is a diagram specifically showing the operation of the frequency synthesizer. As shown in FIG. 5, the output clock signal 224 of the frequency synthesizer 217 switches between a first frequency 221, a second frequency 222, and a third frequency 223. At this time, the frequency of the clock signal was 1 GHz or more, and the switching time interval was 20 ns or less.

  A second embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 6 is a block diagram illustrating a frequency synthesizer according to the second embodiment of the present invention.

  As shown in FIG. 6, the frequency synthesizer of the second embodiment has a current control oscillator 44 instead of the VCO 13, a current holding circuit 42 instead of the voltage holding circuit 10, and a low-pass filter as compared with the first embodiment. Is different in that it has a voltage-current conversion circuit 41 that converts the output signal into a current. The phase comparator 38, the charge pump circuit 39, the low-pass filter 40, and the frequency divider 45 have the same configuration as the phase comparator 8, the charge pump circuit 9, the low-pass filter 11, and the frequency divider 14 in the first embodiment. Therefore, detailed description is omitted.

  Next, the operation of the second embodiment will be described with reference to the drawings.

  As shown in FIG. 6, as compared with the first embodiment, currents corresponding to a plurality of output frequencies of the current controlled oscillator 44 are held by the current holding circuit 42. At this time, the current held by the current holding circuit 42 is obtained by copying the output current 46 of the voltage / current control circuit 41 after stabilizing the frequency of the output clock signal 31 by the loop including the low-pass filter 40 as in the first embodiment. It is. For example, assuming that the holding current is the first holding current 33, the second holding current 34, and the third holding current 35, the switch 43 switches to these holding currents to switch the frequency of the output clock signal 36.

  According to this embodiment, even when a current controlled oscillator is used instead of a VCO, a current corresponding to the output frequency of a plurality of current controlled oscillators is held, and the frequency can be switched at high speed by switching the current. it can.

  Embodiment 3 of the present invention will be described in detail with reference to the drawings.

  FIG. 7 is a block diagram showing a circuit configuration of Embodiment 3 of the present invention.

  As shown in FIG. 7, the third embodiment does not have the holding voltage circuit 10 as compared with the first embodiment, and has a first low-pass filter 82 and a second low-pass filter 83, and a switch 86 that switches between them. Is different. Further, a plurality of low-pass filters may be provided.

  The phase comparator 93, the charge pump circuit 94, the VCO 88, and the frequency divider 95 have the same configuration as the phase comparator 8, the charge pump circuit 9, the VCO 88, and the frequency divider 14 in the first embodiment. The detailed explanation is omitted.

  Next, the operation of the present embodiment will be described in detail with reference to the drawings.

  As shown in FIG. 7, the low-pass filters 82 and 83 are switched by a switch 86, and voltages corresponding to a plurality of output frequencies of the voltage-controlled oscillator 88 are held in the low-pass filters 82 and 83. For example, the switch 86 is switched to connect the output signal 84 of the first low-pass filter 82 and the input signal 87 of the VCO 88 and operate until the frequency of the output clock signal 90 reaches a steady state.

  Next, the frequency of the input clock signal 91 or the frequency dividing ratio of the frequency dividing circuit 95 is switched to switch the frequency of the output clock signal 90, and the switch 86 is switched to switch the output signal 85 of the second low-pass filter 83 and the VCO 88. The input signal 87 is connected and operated until the frequency of the output clock signal 90 reaches a steady state.

  After holding the voltage in the low-pass filter in this way, the switch 86 is switched to switch the frequency of the output clock signal 90. At the same time, the frequency of the input clock signal 91 for generating the frequency of the output clock signal 90 equal to that when the voltage is held in the low-pass filter or the frequency dividing ratio of the frequency dividing circuit 95 is switched.

  As described above, according to the third embodiment, the voltages corresponding to the plurality of output frequencies of the voltage-controlled oscillation circuit are held in the plurality of low-pass filters, and the frequency switching can be performed at high speed by switching these low-pass filters. Furthermore, it can be operated by feedback control.

  Embodiment 4 of the present invention will be described in detail with reference to the drawings.

  FIG. 8 is a block diagram of Embodiment 4 of the present invention.

  As illustrated in FIG. 8, the frequency synthesizer according to the fourth embodiment includes a switch that switches between the mixer 112, the second input signal 116, the third input signal 117, the fourth input signal 118, and the fifth input signal 119. 115 and a band-pass filter 120. Note that the number of signals input to the switch 115 may be plural other than four. The number of the first input signals 111 may be plural.

  In FIG. 8, when the switch 115 selects the second input signal 116, the switch output signal 114 becomes the second input signal 116, and the mixer 112 determines the frequency of the first input signal 111 and the second input signal. A signal having a frequency that is the sum of the frequency of 116 and a signal having a difference between the frequency of the first input signal 111 and the frequency of the second input signal 116 are output.

  At this time, the control signal 121 of the bandpass filter 120 sets the center frequency of the bandpass filter 120 to a signal having a frequency that is the sum of the frequency of the first input signal 111 and the frequency of the second input signal 116, or the first The frequency is switched to a signal having a difference between the frequency of the input signal 111 and the frequency of the second input signal 116.

As a result, signals other than the center frequency of the bandpass filter 120 are removed, and the output signal is a signal having the sum of the frequency of the first input signal 111 and the frequency of the second input signal 116 or the first input signal. A signal having a frequency difference between the frequency of 111 and the frequency of the second input signal 116 is output. This is shown in FIG. In FIG. 9, the frequency of the first input signal 111 is f ₁ , the frequency of the second input signal 116 is f ₂ , the center frequency of the bandpass filter 120 is f ₁ + f _2, and the first input signal 111 2 shows a state in which a signal having the sum of the frequency of the second input signal 116 and the frequency of the second input signal 116 is output.

  Next, when the switch 115 selects the third input signal 117, the center frequency of the band-pass filter 120 is set by the band-pass filter control signal 121, the frequency of the first input signal 111 and the third input signal 117. The signal is switched to a signal having a frequency summed with the frequency or a signal having a frequency difference between the frequency of the first input signal 111 and the frequency of the third input signal 117.

  As a result, the output signal is a signal having the frequency of the sum of the frequency of the first input signal 111 and the frequency of the third input signal 117, or the frequency of the first input signal 111 and the frequency of the third input signal 117. A signal having the difference frequency is output.

  As described above, the frequency of the output signal can be switched over a wide band by switching the center frequency of the bandpass filter 120 in accordance with the frequency of the output signal of the mixer 112.

  Next, an application example of the above-described frequency synthesizer will be described.

  FIG. 10 is a diagram illustrating an application example of the above-described frequency synthesizer.

  The frequency synthesizer 1217 of the present invention is effective in a radio system that performs frequency hopping as shown in FIG.

  In FIG. 10, an antenna output signal 1212 that has passed through an antenna 1211 is amplified by a low noise amplifier (LNA) 1213, and this mixer output signal 1218 is output by a mixer 1215 with the LNA output signal 1214 and an output clock signal 1216 of a frequency synthesizer as inputs. Generated.

  Embodiment 5 of the present invention will be described in detail with reference to the drawings.

  FIG. 11 is a block diagram of a frequency synthesizer in the fifth embodiment of the present invention.

  As shown in FIG. 11, the frequency synthesizer of the fifth embodiment has a low-pass filter 141 and a high-pass filter 140, an output signal 143 of the low-pass filter 141, and a high-pass filter in place of the bandpass filter 120 as compared with the fourth embodiment. It differs in that it has a switch 144 that switches between 140 output signals 142.

  Next, the operation of the fifth embodiment will be described with reference to the drawings.

  In FIG. 11, for example, when the switch 135 selects the second input signal 136, the switch output signal 134 becomes the second input signal 136, and the mixer 112 receives the first input signal 131 and the second input signal. A signal 136 is input. Then, the mixer 112 has a signal having a frequency that is the sum of the frequency of the first input signal 131 and the frequency of the second input signal 136, and the frequency of the first input signal 131 and the frequency of the second input signal 136. The signal of the difference frequency is output.

At this time, the cutoff frequency of the high-pass filter 140 is set to the first input signal 131. As a result, the output signal 142 of the high-pass filter 140 becomes a signal having a frequency that is the sum of the frequency of the first input signal 131 and the frequency of the second input signal 136. This is shown in FIG. In Figure 12, the frequency of the first input signal 131 and _{f 1,} the frequency of the second input signal 136 and _{f 2,} the signal passing through is the frequency of the first input signal 131 and the second input signal 136 It shows that the signal has a frequency that is the sum of the frequency.

Further, the cutoff frequency of the low-pass filter 141 is set to the first input signal 31. As a result, the low-pass filter output signal 143 becomes a signal having a frequency difference between the frequency of the first input signal 111 and the frequency of the second input signal 116. This is shown in FIG. In FIG. 13, the frequency of the first input signal 131 is f ₁ , the frequency of the second input signal 136 is f ₂ , and the passing signal is the frequency of the first input signal 131 and the second input signal 136. It shows that the signal has a frequency different from the frequency.

  The output signal 142 of the high pass filter 140 and the output signal 143 of the low pass filter 141 are switched by a switch 144 to obtain an output signal 145.

  Further, the switch 135 is switched, and the third input signal 137, the fourth input signal 138, or the fifth input signal 139 is input to the mixer 132, and the output signal 145 of each frequency is obtained.

  According to the present embodiment, the cutoff frequency of the low-pass filter and the high-pass filter is set in accordance with the frequency of the fixed frequency signal among the two input signals of the mixer, and the output of the low-pass filter and the high-pass filter is selected. Accordingly, the circuit scale of the filter can be reduced, and the frequency of the output signal can be switched over a wide band.

  Next, a sixth embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 14 is a block diagram of a frequency synthesizer according to the sixth embodiment of the present invention.

  As shown in FIG. 14, the frequency synthesizer of the sixth embodiment has a frequency dividing circuit 412 that multiplies the period of the input clock signal 411 by a positive integer, and a multiphase clock signal that generates a multiphase clock signal from the frequency dividing circuit output signal 413. A clock signal generation circuit 414, a selector circuit 416 for selecting an output clock signal 417 by selecting from the plurality of multiphase clock signals 415, and a control circuit for generating control signals for the multiphase clock signal generation circuit 414 and the selector circuit 416 418 (control signal 420 of the multiphase clock signal generation circuit, control signal 421 of the selector circuit).

  Next, a specific configuration of each circuit block will be described.

  In FIG. 14, the frequency dividing circuit 412 switches the period of the input clock signal 411 to an integral multiple by the control signal 401 and generates the frequency dividing circuit output signal 413.

  FIG. 15 is a block diagram showing a circuit configuration of the sixth embodiment, in which a multiphase clock signal generation circuit is specifically shown.

  As shown in FIG. 15, the multiphase clock signal generation circuit 414 receives a phase 0 ° signal 451 and a phase 90 ° signal 452 as inputs and generates a phase 0 ° to 90 ° signal, A phase interpolation circuit 456 that receives a 90 ° signal 452 and a phase 180 ° signal 453 as input and generates a phase signal from 90 ° to 180 °, and a phase 180 ° signal 53 and a phase 270 ° signal 454 as inputs. A phase interpolation circuit 457 that generates a signal of 270 ° to 270 °, a signal 454 of a phase 270 °, and a signal 451 of a phase 360 ° (0 °) are input, and a signal of 270 ° to 360 ° (0 °) is generated. And a phase interpolation circuit 458.

  At this time, the phase 0 ° signal 451, the phase 90 ° signal 452, the phase 180 ° signal 453, and the phase 270 ° signal 454 have phases of 90 °, 180 °, and 270 ° from the divider circuit output signal 413, respectively. Occurs by shifting. These signals 451, 452, 453, 454 can also be generated by the frequency divider 412. Further, the output phase of each phase interpolation circuit is switched by the control signal 459 of the phase interpolation circuit.

  FIG. 16 is a diagram specifically illustrating a phase interpolation circuit used in the multiphase clock signal generation circuit.

  As shown in FIG. 16, the phase interpolation circuit includes a first load circuit 481 at the drain ends of the first MOS transistor 483 and the third MOS transistor 485, and a second MOS transistor 84 and a fourth MOS transistor 86. The second load circuit 82 at the drain terminal, the first current source 489 at the source terminals of the first MOS transistor 483 and the second MOS transistor 484, and the third MOS transistor 485 and the fourth MOS transistor 486. A second current source 490 at the source terminal, a first input signal 487 at the gate terminals of the first MOS transistor 483 and the third MOS transistor 485, and a second MOS transistor 484 and a fourth MOS transistor 486. The second input terminal 488 is connected to the gate end of the first output signal 492, and the first output signal 492 and the second output signal 493 are output. At this time, the current amount of the first current source 489 and the second current source 490 is controlled by the current source control signal 491, and the phase of the output signal is switched.

  In addition to this, the phase interpolation circuit can also be configured by connecting the outputs of two CMOS inverters and controlling the drive capability of each inverter. Further, although a four-phase clock signal is input in FIG. 14, it can be configured by using a clock signal having four or more phases.

  In addition, the multiphase clock generation circuit can be configured by connecting a plurality of delay circuits in series and taking out the output of each delay circuit.

  In FIG. 14, a selector circuit 416 selects and outputs a clock signal of one phase from a plurality of input multiphase clock signals by a control signal 420. At this time, the value of the output clock signal 417 is inverted in synchronization with the selected clock signal.

  In FIG. 14, the control circuit 418 of the multiphase clock signal generation circuit and the selector circuit switches the control signal at a timing synchronous or asynchronous with the output clock signal 417.

  Next, the operation of the above embodiment will be described in detail with reference to the drawings.

  FIG. 17 is a diagram illustrating the operation of this embodiment.

  As shown in FIG. 17, the value of the output clock signal 437 is inverted from the low level to the high level at the rising edge of the input clock signal 431. Next, the multiphase clock signal generation circuit 414 generates a signal 432 obtained by delaying the input clock signal by one, and the output clock signal 437 is inverted from the high level to the low level at this rising edge. At this time, the increment delay time 445 is the minimum delay time during which the multiphase clock signal generation circuit 414 is switched.

  Further, a signal 433 obtained by delaying the input clock signal by 2 steps, a signal 434 obtained by delaying the input clock signal by 3 steps, a signal 434 obtained by delaying the input clock signal by 3 steps, a signal 435 obtained by delaying the input clock signal by 4 steps, and an input clock signal A signal 436 delayed by 5 steps and a signal delayed by 1 step are generated, and the output clock signal 437 is inverted at each rising edge.

  By repeating this operation, an output clock signal 437 having a period 444 equal to a delay time of 2 units is obtained.

  FIG. 18 is a diagram showing another operation of the present embodiment.

  As shown in FIG. 18, after the output clock signal 506 is inverted from the low level to the high level at the rising edge of the input clock signal 501, unlike the operation shown in FIG. 17, the input clock signal is input instead of the signal 502 delayed by one step. A signal 503 obtained by delaying the clock signal by 2 is generated, and the output clock signal 506 is inverted from the high level to the low level at this rising edge.

  Further, instead of the signal 504 obtained by delaying the input clock signal by 3 steps, a signal 505 obtained by delaying the input clock signal by 4 steps is generated, and the output clock signal 506 is inverted at this rising edge. By repeating this operation of delaying the clock signal by 2 steps and inverting the output clock operation, an output clock signal 506 having a period 5113 equal to the delay time of 4 steps is obtained. However, this one-step delay time 507 is assumed to be equal to the delay time 445 in FIG.

  Next, the operation of the control signal of the control circuit 418 of the multiphase clock signal generation circuit and selector circuit in FIG. 14 will be described in detail with reference to the drawings.

  FIG. 19 is a diagram specifically illustrating the operation of the control signal.

  As shown in FIG. 19, when a control signal 471 for generating a clock signal having a phase of 0 ° is a binary 4-bit signal “0000”, a clock signal having a phase of 22.5 °, which is a phase 72 increment from the phase of 0 °, is generated. The control signal 476 to be generated is “0001”, the control signal 477 for generating a clock signal having a phase of 45 ° is “0010”, the control signal 478 for generating a clock signal having a phase of 62.5 ° is “0011”, and the clock signal having a phase of 90 ° is The generated control signal 473 is “0100”, the control signal 474 that generates a clock signal having a phase of 180 ° is “1000”, and the control signal 475 that generates a clock signal having a phase of 270 ° is “1100”.

  In FIG. 15, when the upper 2 bits of this control signal are “00”, the output signal 460 of the phase interpolation circuit that generates a signal having a phase of 0 ° to 90 ° is generated. The output signal 461 of the phase interpolation circuit that generates a signal of °, the output signal 462 of the phase interpolation circuit that generates a signal of phase 180 ° to 270 ° when “10”, and the phase 270 ° when “11”. The output signal 463 of the phase interpolation circuit that generates a 360 ° (0 °) signal is selected.

  Further, the phase interpolation ratio of the phase interpolation circuit in FIG. 15 is determined by the control signal of the lower 2 bits. For example, in FIG. 19, the control signal 477 for generating a clock signal having a phase of 45 ° is “0010”, which is the phase for generating a signal having a phase of 0 ° to 90 ° in the upper 2 bits “00” in FIG. By selecting the output signal 460 of the interpolation circuit and setting the lower 2 bits “10” as the control signal 459 of the phase interpolation circuit, a clock signal having a phase of 45 ° is generated.

  FIG. 20 is a diagram specifically illustrating another operation of the control signal in the sixth embodiment of the present invention.

  When the output clock signal 506 is inverted by delaying the clock signal by two increments as shown in FIG. 20, the control signal delays the clock signal by two increments from the first control signal 541 “0000” as shown in FIG. The second control signal 542 "0010", the second control signal 542 "0010" to the third control signal 543 "0100", which delays the clock signal by two steps, and the second clock signal is further delayed by two. Are switched to the fourth control signal 544, the fifth control signal 545, the sixth control signal 546, the seventh control signal 547, and the eighth control signal 548.

  Next, the effect of the present embodiment will be described. In this embodiment, the multiphase clock signal generation circuit generates clock signals at timings between the cycles of the input clock signal, and selects these clock signals to generate an output clock signal. For this reason, the cycle of the output clock signal can be adjusted with a resolution equal to or lower than the cycle of the input clock signal.

  Next, effects of the present embodiment will be described with reference to the drawings.

  FIG. 21 is a block diagram illustrating effects of the sixth embodiment.

  A frequency synthesizer 1217 of the present invention as shown in FIG. 21 is effective in a radio system that performs frequency hopping.

  In FIG. 21, an antenna output signal 1212 that has passed through an antenna 1211 is amplified by a low noise amplifier (LNA) 1213, and the mixer output signal 1218 is output by a mixer 1215 with the LNA output signal 1214 and the output clock signal 1216 of the frequency synthesizer as inputs. appear.

  Next, the operation of the frequency synthesizer 1217 will be described with reference to the drawings.

  FIG. 22 is a diagram specifically showing the operation of the frequency synthesizer.

  As shown in FIG. 22, the output clock signal 1224 of the frequency synthesizer switches between a first frequency 1221, a second frequency 1222, and a third frequency 1223.

  Next, a seventh embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 23 is a block diagram of a frequency synthesizer according to the seventh embodiment of the present invention.

  As shown in FIG. 23, the frequency synthesizer of the seventh embodiment has a first multiphase clock signal generation circuit 524 and a first selector circuit that receive the output signal 523 of the frequency divider circuit as compared with the sixth embodiment. 528 and the second multiphase clock signal generation circuit 525 and the second selector circuit 529 are connected in parallel to select the output signal 530 of the first selector circuit and the output signal 531 of the second selector circuit. 3 selector circuit 532.

  Next, the operation of the present embodiment will be described with reference to the drawings.

  As shown in FIG. 23, when the output signal 530 of the first selector circuit is selected by the third selector circuit 532, the second multiphase clock generation circuit and the second selector circuit are controlled by the control circuit 534. Then, a multiphase clock signal selected by the third selector circuit 132 is generated.

  The effect of the present embodiment will be described.

  In this embodiment, the operation speed of the control circuit can be reduced by sequentially controlling a plurality of pairs of multi-phase clock generation circuits and selector circuits.

  Next, an eighth embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 24 is a block diagram of the frequency synthesizer of the eighth embodiment.

  As shown in FIG. 24, the frequency synthesizer of the eighth embodiment is different from the sixth embodiment in that it has a random number generation circuit 592.

  Next, the operation of the present embodiment will be described in detail with reference to the drawings.

  FIG. 25 is a diagram illustrating the operation of the eighth embodiment of the present invention.

  As shown in FIG. 25, switching is performed at different phase step intervals according to the output signal 593 of the random number generation circuit.

  In FIG. 25, when switching from the first control signal 551 to the second control signal 552, when switching from the second control signal 552 to the third control signal 553, and from the fourth control signal 554 to the fifth control signal 552. When the control signal 555 is switched, when the fifth control signal 555 is switched to the sixth control signal 556, when the seventh control signal 557 is switched to the eighth control signal 558, and when the eighth control signal 558 is switched. When switching from the third control signal 559 to the ninth control signal 559 is a phase delay of 2 increments, when switching from the third control signal 553 to the fourth control signal 554, and from the sixth control signal 556 to the seventh control signal 559 When switching to the control signal 557 is a phase delay of one step.

  Next, effects of the present embodiment will be described with reference to the drawings.

  FIG. 26 is a diagram showing the effect of this embodiment.

  As shown in FIG. 26, by switching between the first phase step interval and the second phase step interval by the random number generation circuit, the spectrum 562 and the second of the output clock signal when operating at the first fixed step interval. A spectrum 563 of the output clock signal when the step is fluctuated can be generated by a random number generation circuit at an arbitrary frequency between the output clock signal spectrum 563 when operating at a fixed step interval. The vertical axis is the spectrum intensity axis 560, and the horizontal axis is the frequency axis 561.

  Next, a ninth embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 27 is a block diagram of Embodiment 9 of the present invention.

  As shown in FIG. 27, in the ninth embodiment, a multiphase clock signal generation circuit 612 that generates a multiphase clock signal from an input clock signal 611, and an output clock signal 614 selected from the plurality of multiphase clock signals 613 are selected. A selector circuit 615 for generating, a multiphase clock signal generating circuit 612, and a control circuit 616 for generating control signals for the selector circuit 615 (control signal 617 for the multiphase clock signal generating circuit, control signal 618 for the selector circuit). The

  Next, specific circuit configurations of these circuit blocks will be described.

  FIG. 28 is a specific circuit configuration diagram of the multiphase clock signal generation circuit 612, the selector circuit 615, and the control circuit 616.

  As shown in FIG. 28, the multiphase clock signal generation circuit 612 receives a phase 0 ° signal 651 and a phase 90 ° signal 652 as input, and generates a phase 0 ° to 90 ° signal 661, A phase interpolation circuit 656 that receives a signal 652 having a phase of 90 ° and a signal 653 having a phase of 180 ° and generating a signal 662 having a phase of 90 ° to 180 °, and a signal 653 having a phase of 180 ° and a signal 654 having a phase of 270 ° are input. A phase interpolation circuit 657 for generating a signal 663 having a phase of 180 ° to 270 °, a signal 654 having a phase of 270 °, and a signal 651 having a phase of 360 ° (0 °) as inputs, and a signal having a phase of 270 ° to 360 ° (0 °) And a phase interpolation circuit 658 for generating 664.

  At this time, the phase 0 ° signal 651, the phase 90 ° signal 652, the phase 180 ° signal 653, and the phase 270 ° signal 654 are shifted in phase by 90 °, 180 °, and 270 ° from the input clock signal 611. generate. Further, the output phase of each of the phase interpolation circuits 655 to 617 is switched by the control signal 617 of the phase interpolation circuit.

  FIG. 29 is a diagram specifically illustrating the phase interpolation circuits 655 to 617 used in the multiphase clock signal generation circuit 612.

  As shown in FIG. 29, the phase interpolation circuits 655 to 617 include the first load circuit 681 at the drain ends of the first MOS transistor 683 and the third MOS transistor 685, and the second MOS transistor 684 and the fourth MOS transistor 684. The second load circuit 682 is provided at the drain end of the MOS transistor 686, the first current source 689 is provided at the source ends of the first MOS transistor 683 and the second MOS transistor 684, and the third MOS transistor 685 and the fourth MOS transistor 685 are connected. The second current source 690 is provided at the source terminal of the MOS transistor 686, the first input signal 687 is provided at the gate terminals of the first MOS transistor 683 and the third MOS transistor 685, and the second MOS transistor 684 and the fourth MOS transistor 684 are connected. A second input terminal 688 is connected to the gate terminal of the MOS transistor 686 to output a first output signal 692 and a second output signal 693. At this time, the current amount of the first current source 689 and the second current source 690 is controlled by the control signal 691 of the current source, and the phase of the output signal is switched.

  In addition to this, the phase interpolation circuit can also be configured by connecting the outputs of two CMOS inverters and controlling the drive capability of each inverter.

  In FIG. 28, a four-phase clock signal is input. However, a clock signal having four or more phases can be used.

  In addition, the multiphase clock generation circuit can be configured by connecting a plurality of delay circuits in series and taking out the output of each delay circuit.

  Next, the operation of the control signal of the control circuit 616 that controls the multiphase clock signal generation circuit 612 and the selector circuit 615 will be described in detail with reference to the drawings.

  FIG. 30 is a diagram for explaining a control signal of the control circuit 616.

As shown in FIG. 30, when a control signal 671 for generating a clock signal having a phase of 0 ° is a binary 4-bit signal “0000”, a control signal 676 for generating a clock signal having a phase of 22.5 ° which is incremented by 1 from phase 0 °. Is "0001", a control signal 677 that generates a clock signal having a phase of 45 ° is "0010", a control signal 678 that generates a clock signal having a phase of 62.5 ° is "0011", and a control signal that generates a clock signal having a phase of 90 ° The control signal 674 for generating a clock signal having a phase of 180 ° is “1000”, and the control signal 675 for generating a clock signal having a phase of 270 ° is “1100”.

  In FIG. 30, when the upper 2 bits of this control signal are “00”, the output signal 661 of the phase interpolation circuit that generates a signal having a phase of 0 ° to 90 ° is displayed. The output signal 662 of the phase interpolation circuit that generates a signal of °, the output signal 663 of the phase interpolation circuit that generates a signal of phase 180 ° to 270 ° when “10”, and the phase 270 ° when “11”. The output signal 664 of the phase interpolation circuit that generates a 360 ° (0 °) signal is selected.

  Further, the phase interpolation ratio of the phase interpolation circuit is determined by the lower 2 bits of the control signal. For example, in FIG. 30, a control signal 677 that generates a clock signal having a phase of 45 ° is “0010”, which is a phase interpolation circuit 665 that generates a signal having a phase of 0 ° to 90 ° with the upper 2 bits “00”. The output signal 661 is selected and the lower 2 bits “10” are used as the control signal 617 of the phase interpolation circuit, thereby generating a clock signal having a phase of 45 °.

  When the clock signal is delayed by 2 steps, the control signal is changed from the first control signal 671 “0000” to the second control signal 677 “0010” that delays the 2 step clock signal. Switching from “0010” to a third control signal 673 “0100” that delays the clock signal by 2 steps is further performed to delay the clock signal by 2 steps.

  Next, the operation of the ninth embodiment will be described with reference to FIGS.

  FIG. 31 is a diagram for explaining the operation of the ninth embodiment, and is a time chart when the phase of the input clock signal is shifted in increments of one. In the time chart of FIG. 31, the phase for each step is 22.5 °. In the case of FIG. 31, the rising phase of the input clock signal is shifted and the falling signal is ignored, but the roles of falling and rising may be reversed.

In FIG. 31, a 0 ° clock signal 651 is a signal having a period T ₀ and always rising at a phase of 0 °.

  First, it is assumed that the control signal 618 of the selector 615 is switched to “00” and the control signal 617 of the phase interpolation circuit is switched to “01” at the left end of FIG. At this time, the selector 615 selects the output signal 661 of the 0-90 ° phase interpolation circuit 655, which is a 22.5 ° signal. In response to the rising signal of the output signal 661 of the phase interpolation circuit 655 of 0 to 90 °, the output signal 614 of the selector 615 outputs a rising signal. This selector has a monostable multilator built in its output stage, and this monostable multilator outputs a pulse that becomes a high level for a short time as the signal 614 from the rising edge of the selected signal. To do.

Further, by adding “0001” to the control circuit 616, the control signal 618 of the selector 615 and the phase interpolation ratio control signal 617 of the phase interpolation circuit are switched from “01” to “10”, and 0 to 90 °. The phase of the output signal 661 of the phase interpolation circuit 655 is shifted by one step and switched to a 45 ° signal. At this time, the selector 615 selects the output signal 661 of the phase interpolation circuit 655 of 0 to 90 ° as it is.
Subsequently, similarly, the output signal 614 of the selector 615 outputs a rise by the rising signal of the output signal 661 of the phase interpolation circuit 655 of 0 to 90 °, and the control signal 617 of the phase interpolation ratio of the phase interpolation circuit is set to “10”. By switching from “11” to “11”, the phase of the output signal 661 of the phase interpolation circuit 655 of 0 to 90 ° is shifted by 1 to obtain a signal of 67.5 °.

  Then, when the rising signal of the output signal 661 of the phase interpolation circuit 655 of 0 to 90 ° comes next, the control signal 618 of the selector 615 that has not changed so far is switched from “00” to “01”, and the selector 615 Switches from the output signal 661 of the phase interpolation circuit 655 at 0 to 90 ° to the output signal 662 of the phase interpolation circuit 656 at 90 to 180 °.

  Also, since the phase interpolation ratio control signal 617 of the phase interpolation circuit is “00”, the output signal 662 of the phase interpolation circuit 656 of 90 ° to 180 ° is a 90 ° signal. At this time, the output signal 662 of the phase interpolation circuit 656 of 90 ° to 180 ° within one cycle from the rising edge of the output signal 614 of the selector 615 is not output. Thereafter, the operation is the same as described above.

  Next, an operation when the phase of the input clock signal is shifted by 2 steps will be described.

  FIG. 32 is a diagram for explaining the operation of the ninth embodiment, and is a time chart when the phase of the input clock signal is shifted by 2 steps. In the time chart of FIG. 32, the phase every two steps is 45 °. In the case of FIG. 32, the rising phase of the input clock signal is shifted and the falling signal is ignored, but the roles of falling and rising may be reversed.

  32, first, assume that the control signal 618 of the selector 615 is switched to “00” and the phase interpolation ratio control signal 617 of the phase interpolation circuit is switched to “10” at the left end of FIG.

  At this time, the selector 615 selects the output signal 661 of the phase interpolation circuit 655 of 0 to 90 ° which is a 45 ° signal. Due to the rising signal of the output signal 661 of 0 to 90 °, the output signal 614 of the selector 615 outputs a rising signal as in the operation of FIG.

  Further, by adding “0010” to the control circuit 616, the control signal 618 of the selector 615 is switched to “01”, and the control signal 617 of the phase interpolation ratio of the phase interpolation circuit is switched to “00”.

  The control signal 618 of the selector 615 causes the selector 615 to switch from the output signal 661 of the phase interpolation circuit 655 of 0 to 90 ° to the output signal 662 of the phase interpolation circuit 656 of 90 ° to 180 °.

  Further, the output signal 662 of the phase interpolation circuit 656 of 90 ° to 180 ° becomes a 90 ° signal by the control signal 617 of the phase interpolation ratio of the phase interpolation circuit. Thereafter, the operation is the same as described above.

  A tenth embodiment of the present invention will be described.

  FIG. 33 is a block diagram of the frequency synthesizer of the tenth embodiment.

  As shown in FIG. 33, the frequency synthesizer of the tenth embodiment is different from the ninth embodiment in that a frequency dividing circuit 810 is provided.

  By having the frequency dividing circuit 810, the input signal 811 input to the multi-phase clock signal generating circuit 612 can be divided into a plurality of signals different from the input clock signal 611. Many types of output signals can be obtained.

  Embodiment 11 of the present invention will be described.

  FIG. 34 is a block diagram of the frequency synthesizer of the eleventh embodiment.

As shown in FIG. 34, in addition to the ninth and tenth embodiments, the frequency synthesizer of the eleventh embodiment includes a plurality of multiphase clock signal generation circuits 612 _{1 to} 612 _n , a plurality of selectors 615 ₁ to 615 _n , The difference is that it has a selector 821.

  By using a plurality of multiphase clock signal generation circuits and selectors, it is possible to generate a signal having a shorter cycle than the input clock signal.

  A twelfth embodiment of the present invention will be described.

  FIG. 38 is a block diagram of the frequency synthesizer of the twelfth embodiment.

  As shown in FIG. 38, the frequency synthesizer according to the twelfth embodiment includes first to fourth pulse generation circuits 2105 to 2108 having four-phase clocks (0 °, 90 °, 180 °, and 270 °) 2101 to 2104 as input signals. And an adder circuit 2124 that adds the outputs 2120 to 2123 of these pulse generation circuits.

  The first pulse generation circuit 2105 includes a phase interpolation circuit 2109, an accumulator 2110, and a gate circuit 2111. The same applies to the second to fourth pulse generation circuits. In the pulse generation circuit, adjacent phase clocks, here, 0 ° and 90 ° clocks are input to the phase interpolation circuit 2109.

  In the phase interpolation circuit, the phases of the outputs 2112 to 2113 are switched according to the value of the least significant bit 2115 in the control signal 2114 from the accumulator. However, 2112 and 2113 are differential signals.

  The accumulator normally adds and accumulates the value of the 3-bit control signal 2118 for each cycle of the output of the phase interpolation circuit, and adds 1 bit to output 4 bits. The accumulator can accumulate values up to “111”, but if the overflow occurs in a certain cycle, the value of the added 1 bit changes and the addition is stopped. Then, in the next cycle, the value of 1 bit is returned to the value before the overflow again, so that the addition is similarly performed until the next overflow. Of the 4-bit output 2114 of the accumulator, the upper 3 bits 2116 to 2117 are used for the control signal for the gate circuit, and as described above, the least significant bit 2115 is used for the control signal for the phase interpolation circuit. The most significant bit 2116 is a bit whose value changes due to the overflow.

  In the gate circuit, when the control signal 2117 from the 2-bit accumulator is equal to a unique value and does not overflow, the output 2113 of the phase interpolation circuit is passed. Conversely, the output 2113 of the phase interpolation circuit is not passed except under this condition. The unique value is different in each gate circuit in the first to fourth pulse generation circuits.

  A reset signal 2119 resets all accumulator values, that is, changes them to the same value. Normally, this value is “0”.

  Next, specific operations will be described with reference to the drawings.

  FIG. 39 is a vector diagram showing the output phase of the phase interpolation circuit in the first to fourth pulse generation circuits 2105 to 2108.

  As shown in FIG. 39, the output phase of the phase interpolation circuit is 3 bits, that is, transitions between 8 states. The output phases 0 ° to 315 ° 2201 to 2208 of the phase interpolation circuit are indicated by binary code values from “000” to “111”, respectively. However, gray code or the like may be used instead of binary code.

  FIG. 40 shows a pulse generation circuit when the gate circuit 2111 passes the output 2113 of the phase interpolation circuit when the control signal 2118 is “011” and the control signal 2117 from the accumulator is “00” in the frequency synthesizer of the twelfth embodiment. It is a time chart figure. However, in this time chart, the case where the rising phase of the pulse generation circuit output 2307 is switched will be described. The same applies when switching the falling phase.

  As shown in FIG. 40, when the reset signal 2301 is “1”, that is, from the time 2351 to 2353, the accumulator outputs 2302 to 2304 are always “0”. However, the accumulator output 2302 is a bit whose value changes due to the overflow, the accumulator output 2303 is 2 bits of the control signal 2117 from the accumulator, and the output 2304 is 1 bit of the control signal of the phase interpolation circuit. In addition, since these 4 bits correspond in order from the most significant bit to the least significant bit, for example, the accumulator output 2302 is equal to the most significant bit. At this time, since the output 2303 of the accumulator is “00”, the gate opening / closing signal 2305 becomes “1”, and the output 2306 of the phase interpolation circuit becomes the pulse generation circuit output 2307 as it is, that is, outputs the phases 0 ° and 2201. To do. However, the gate open / close signal 2305 is a signal whose state is determined by the accumulator outputs 2302 to 2303.

  Next, when the reset signal is “0”, that is, from time 2353 to 2377, the accumulator output changes at the falling time of the phase interpolation circuit output 2307. At time 2357, “011” is added to the accumulator, the accumulator output 2303 changes from “00” to “01”, and the accumulator output 2304 changes from “0” to “1”. Due to the accumulator output 2304, the rise of the phase interpolation circuit output 2307 is switched from the time 2359, that is, the phase of 0 °, to the middle of the time 2359 and the time 2360, that is, the phase of 45 °. Similarly, the falling phase of the phase interpolation circuit output 2307 is switched between the time 2361 and the time 2362. At this time, since the accumulator output 2303 is different from “00”, the gate opening / closing signal 2305 is changed from “1” to “0”, and the phase interpolation circuit output 2306 does not pass through the gate circuit, that is, the pulse generation circuit output 2307 is “ 0 ". In the middle between time 2361 and time 2362, “011” is added to the accumulator, and the same operation is performed.

  Since the overflow occurs at time 2365, the accumulator output 2303 is changed from “11” to “00”, the accumulator output 2304 is changed from “0” to “1”, and the accumulator output 2302 is changed from “0” to “1”. To change. Due to the accumulator output 2304, the rise of the phase interpolation circuit output 2307 is switched from the time 2367, that is, the phase of 0 °, to the middle of the time 2367 and the time 2368, that is, the phase of 45 °. At this time, the accumulator output 2303 is “00”, but since the accumulator output 2302 is “1”, the gate opening / closing signal 2305 remains “0”. For this reason, the phase interpolation circuit output 2306 does not pass through the gate circuit.

  At the fall time of the output of the next phase interpolation circuit, between the time 2369 and the time 2370, the accumulator outputs 2303 to 2304 do not change, but the accumulator output 2302 returns from “1” to “0”. As a result, the gate open / close signal 2305 changes from “0” to “1”, so that the phase interpolation circuit output 2306 passes through the gate circuit and outputs a phase of 45 °.

  The remaining three pulse generation circuits are pulse generation circuits through which the gate circuit passes the output of the phase interpolation circuit when the 2-bit control signals from the accumulator are "01", "10", and "11", respectively. These pulse generation circuits operate in the same manner except that the 2-bit control signal through which the gate circuit passes the output of the phase interpolation circuit is different.

  FIG. 41 is a time chart of the output 2120 to 2123 and the output 2125 of the pulse generation circuit when the control signal 2118 is “011” in the frequency synthesizer of the twelfth embodiment. When the 2-bit control signals from the accumulator are “01”, “10”, and “11”, pulse generation circuits through which the gate circuit passes the output of the phase interpolation circuit correspond to 2501 to 2504, respectively. However, the combination of the order of the first to fourth pulse generation circuits 2105 to 2108 and the 2-bit control signal is not unique. Times 2551 to 2577 are the same times as times 2351 to 2377, respectively.

  During the period from time 2551 to time 2557, the value is changed by the pulse generation circuit output 2501 and the remaining pulse generation circuit outputs 2502 to 2504 are “0”. Output 2505 is output, that is, a phase of 0 ° is output. Similarly, since only one pulse generation circuit output changes the value, the change of all the pulse generation circuit outputs 2502 to 2504 is output to the addition output. At the output 2502 of the pulse generation circuit, a rise is generated between time 2560 and time 2561, that is, a phase of 135 °, 011 is output. Further, at the output 2504 of the pulse generation circuit, the phases 270 ° and 110 are output at time 2566, and at the output 2501 of the pulse generation circuit, the phases 45 ° and 001 are output between time 2571 and time 2572. That is, the phase is switched by 135 °, that is, by “011”.

  The period from time 2555 to time 2577 is 11/8 times the period from time 2551 to time 2555, that is, the period of input clocks 2101 to 2104. Therefore, the frequency from time 2555 to time 2577 is 8/11 of the frequency of the input clock. This frequency is switched depending on the value of the control signal 2118.

  Next, a circuit that generalizes the frequency synthesizer will be described.

  FIG. 42 is a block diagram of the frequency synthesizer of the twelfth embodiment when the number of bits of the control signal of the gate circuit not including the overflow bit is M and the number of bits of the control signal of the phase interpolation circuit is N.

  As shown in FIG. 42, it is composed of M pulse generation circuits 2106 to 2109 having M phase clocks 2001 to 2005 as input signals, and an addition circuit 2013 for adding the outputs of these pulse generation circuits. FIG. 38 corresponds to the case where M = 2 and N = 1. However, M is equal to the number of bits of the control signal.

但し、ｆ_OUTは出力の周波数，ｆ_REFは入力の周波数、Mはオーバフローのビットを含まないゲート回路の制御信号のビット数、Nは位相補間回路の制御信号のビット数、Pはアキュムレータへ加算する制御信号の値である。 The frequency of the output of this frequency synthesizer is expressed by Equation 1.

Where f _OUT is the output frequency, f _REF is the input frequency, M is the number of bits of the control signal of the gate circuit not including overflow bits, N is the number of bits of the control signal of the phase interpolation circuit, and P is added to the accumulator This is the value of the control signal.

  Next, a specific configuration of the accumulator 2011 will be described with reference to the drawings.

  FIG. 43 is a block diagram specifically showing the configuration of the accumulator 2011 in the frequency synthesizer of the twelfth embodiment.

  As shown in FIG. 43, the M + N + 1 bit full adder 2401, the register 2402 holding the result of the full adder, and the value of the control signal according to the value of the most significant bit (overflow bit) 2045 of the register P or “0”, 2048, and a selector circuit 2403 for selecting 2049. However, M and N are the number of bits respectively.

  The register takes in the output 2410 of the full adder every cycle of the output 2404 of the phase interpolation circuit and holds the value until the next cycle.

  When the most significant bit is 0, the full adder adds the values 2405 and 2406 held in the register and the value P of the control signal. On the other hand, when the overflow occurs, the most significant bit changes to 1, so that the selector circuit selects “0” and is input by the full adder.

  As described above, in the twelfth embodiment, an accumulator is built in each pulse generation circuit, so that the output of the frequency synthesizer can be obtained by simple addition of the outputs of the respective pulse generation circuits.

  The present invention described above can be applied to a frequency synthesizer that needs to switch the frequency of the output clock signal at high speed.

  Further, the present invention described above can be applied to a frequency synthesizer that needs to switch the frequency of an output signal in a wide band.

  In addition, the present invention described above can be applied to a frequency synthesizer in which the increment of the cycle of the output clock signal to be switched or the fine adjustment of the cycle length of the output clock signal to be switched needs to be less than or equal to the cycle of the input clock signal. it can.

  Furthermore, the frequency synthesizer to which the present invention is applied is particularly effective in a radio system that performs frequency hopping.

FIG. 1 is a block diagram of a frequency synthesizer according to the first embodiment of the present invention.

FIG. 2 is a block diagram showing a circuit configuration of the voltage holding circuit 10.

FIG. 3 is a specific circuit diagram of the buffers 52 to 54 used in the voltage holding circuit 10 according to the first embodiment of the present invention.

FIG. 4 is a diagram showing an application example of the frequency synthesizer of the present invention.

FIG. 5 is a diagram specifically showing the operation of the frequency synthesizer.

FIG. 6 is a block diagram illustrating a frequency synthesizer according to the second embodiment of the present invention.

FIG. 7 is a block diagram showing a circuit configuration of Embodiment 3 of the present invention.

FIG. 8 is a block diagram of a frequency synthesizer in the fourth embodiment of the present invention.

FIG. 9 is a diagram for explaining the bandpass filter 120.

FIG. 10 is a diagram illustrating an application example of a frequency synthesizer.

FIG. 11 is a block diagram of a frequency synthesizer in the fifth embodiment of the present invention.

FIG. 12 is a diagram for explaining the high-pass filter 140.

FIG. 13 is a diagram for explaining the low-pass filter 141.

FIG. 14 is a block diagram of a frequency synthesizer according to the sixth embodiment of the present invention.

FIG. 15 is a diagram specifically illustrating a multiphase clock signal generation circuit.

FIG. 16 is a diagram specifically illustrating a phase interpolation circuit used in the multiphase clock signal generation circuit.

FIG. 17 is a diagram illustrating the operation of the sixth embodiment.

FIG. 18 is a diagram illustrating another operation of the sixth embodiment.

FIG. 19 is a diagram specifically illustrating the operation of the control signal.

FIG. 20 is a diagram specifically illustrating another operation of the control signal according to the sixth embodiment of the present invention.

FIG. 21 is a block diagram showing the effect of the sixth embodiment.

FIG. 22 is a diagram specifically illustrating the operation of the frequency synthesizer of the sixth embodiment.

FIG. 23 is a block diagram of a frequency synthesizer according to the seventh embodiment of the present invention.

FIG. 24 is a block diagram of the frequency synthesizer of the eighth embodiment.

FIG. 25 shows the operation of the eighth embodiment of the present invention.

FIG. 26 is a diagram illustrating the effect of the eighth embodiment.

FIG. 27 is a block diagram of Embodiment 9 of the present invention.

FIG. 28 is a specific circuit configuration diagram of the multiphase clock signal generation circuit 612, the selector circuit 615, and the control circuit 616.

FIG. 29 is a diagram specifically illustrating the phase interpolation circuits 655 to 617 used in the multiphase clock signal generation circuit 612.

FIG. 30 is a diagram for explaining a control signal of the control circuit 616.

FIG. 31 is a diagram for explaining the operation of the ninth embodiment, and is a time chart when the phase of the input clock signal is shifted in increments of one.

FIG. 32 is a diagram for explaining the operation of the ninth embodiment, and is a time chart when the phase of the input clock signal is shifted by 2 steps.

FIG. 33 is a block diagram of the frequency synthesizer of the tenth embodiment.

FIG. 34 is a block diagram of the frequency synthesizer of the eleventh embodiment.

FIG. 35 is a block diagram of a conventional first frequency synthesizer.

FIG. 36 is a block diagram of a conventional second frequency synthesizer.

FIG. 37 is a block diagram of a third conventional frequency synthesizer.

FIG. 39 is a block diagram of the frequency synthesizer of the twelfth embodiment.

FIG. 39 is a vector diagram showing the output phase of the phase interpolation circuit in the first to fourth pulse generation circuits 2105 to 2108.

FIG. 40 shows a pulse generation circuit when the gate circuit 2111 passes the output 2113 of the phase interpolation circuit when the control signal 2118 is “011” and the control signal 2117 from the accumulator is “00” in the frequency synthesizer of the twelfth embodiment. It is a time chart figure.

FIG. 41 is a time chart of the output 2120 to 2123 and the output 2125 of the pulse generation circuit when the control signal 2118 is “011” in the frequency synthesizer of the twelfth embodiment.

FIG. 42 is a block diagram of the frequency synthesizer of the twelfth embodiment when the number of bits of the control signal of the gate circuit not including the overflow bit is M and the number of bits of the control signal of the phase interpolation circuit is N.

FIG. 43 is a block diagram specifically showing the configuration of the accumulator 2011 in the frequency synthesizer of the twelfth embodiment.

Explanation of symbols

8 Phase comparator 9 Charge pump circuit 10 Voltage holding circuit 11 Low pass filter 12 Switch 13 Voltage controlled oscillator (VCO)
14 divider

Claims (9)

A multiphase clock signal generation circuit for generating a multiphase clock signal from the multiphase input signal;
A control circuit for generating a first control signal for controlling the multiphase clock signal generation circuit;
A frequency synthesizer having a plurality of multi-phase clock signals output from the multi-phase clock signal generation circuit as input signals and generating a single output clock signal based on the plurality of multi-phase clock signals; ,
The multi-phase clock signal generation circuit has a plurality of phase interpolation circuits,
Each of the phase interpolation circuits takes a first input signal having a first phase and a second input signal having a second phase as input signals, and according to the first control signal from the control circuit, A frequency synthesizer that generates an output signal having a phase that is greater than or equal to the first phase and less than or equal to the second phase. The control circuit generates a second control signal for controlling the generation circuit;
2. The frequency synthesizer according to claim 1, wherein the generation circuit generates one output clock signal based on the plurality of multiphase clock signals in accordance with the second control signal.   2. The generation circuit according to claim 1, wherein the generation circuit uses, as the one output clock signal, a signal that is inverted at each rising or falling edge of an arbitrary multiphase clock signal among the plurality of multiphase clock signals. Item 3. A frequency synthesizer according to Item 2.   4. The frequency synthesizer according to claim 3, wherein the generation circuit changes a phase interval of the one output clock signal by switching the arbitrary multiphase clock signal.   3. The frequency synthesizer according to claim 1, wherein the generation circuit uses, as the one output clock signal, a signal that is inverted every rising edge or falling edge of the plurality of multiphase clock signals.   The multiphase clock signal generation circuit is in accordance with the first control signal of binary (N-M) bits, and the generation circuit has a phase represented by N bits in accordance with the second control signal of M bits. 6. The frequency synthesizer according to claim 1, wherein a clock signal having an arbitrary phase is generated.   The frequency synthesizer according to any one of claims 1 to 6, further comprising a frequency divider that sets a cycle of an input clock signal to a positive integer multiple and outputs the same to the multiphase clock signal generation circuit. A plurality of sets of the multiphase clock signal generation circuit and the generation circuit;
The frequency synthesizer according to any one of claims 1 to 7, further comprising a circuit that selects one clock signal among output signals output from the plurality of sets. An amplifier circuit for amplifying the antenna output signal output from the antenna;
A frequency synthesizer according to any of claims 1 to 8,
A radio system comprising: a mixer that generates a mixer output signal by mixing a clock signal output from the frequency synthesizer and a signal output from the amplifier circuit as inputs.

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