JP2007292976A - Liquid crystal display device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify a manufacturing process by reducing the number of sheets of photomasks at the time of manufacturing the TFT substrate of a liquid crystal display device. <P>SOLUTION: Gate wiring GL and a common electrode CCM are formed by using a first photomask on a glass substrate. Next, drain wiring DL and a pixel electrode PX are formed by using a second photomask. Finally, gate wiring terminal GL and a drain wiring terminal DT are formed by using a third photomask. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device having a TFT substrate manufactured using three photomasks and a manufacturing method thereof.

Conventionally, a TFT substrate has been manufactured using seven photomasks. However, Patent Document 1 below describes that a TFT substrate is manufactured using five photomasks. Recently, it has been developed to manufacture a TFT substrate using four photomasks.
JP 2001-201766 A

  In manufacturing a TFT substrate, in order to reduce the cost of a liquid crystal display device as a product, it is necessary to reduce the number of photomasks and simplify the manufacturing process.

  The present invention is characterized in that a TFT substrate of a liquid crystal display device is manufactured using three photomasks.

  By making the number of photomasks three, the manufacturing process is simplified, the throughput is improved, and the reliability of the product is also improved.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a manufacturing process diagram of a transflective TFT substrate by an IPS method (lateral electric field method), showing a plan view on the left side of the drawing and a cross-sectional view on the right side.

  In FIG. 1, a plurality of gate wirings GL and a plurality of drain wirings DL intersecting with the gate wiring GL are formed on a transparent insulating substrate (glass substrate), and pixel electrodes PX are arranged in a matrix at the intersecting portions. To do. A thin film transistor TFT is formed between the pixel electrode PX and the drain wiring DL. The thin film transistor TFT performs a switching operation that is turned on / off by a scanning signal applied to the gate line GL, and applies an image signal from the drain line DL to the pixel electrode PX when turned on. A horizontal electric field corresponding to the image signal is formed by the pixel electrode PX and the common electrode COM.

  As described above, the color filter substrate on which the color filter is formed is disposed so as to face the TFT substrate on which the thin film transistor TFT is formed on the glass substrate. An image is displayed by applying a lateral electric field corresponding to an image signal to a liquid crystal display device in which liquid crystal is sealed between a TFT substrate and a color filter substrate.

  In FIG. 1 (a), ITO (Indium Tin Oxide) serving as a common electrode COM and Mo (molybdenum) / Al (aluminum) / Mo (molybdenum) serving as a gate wiring GL are successively laminated on a glass substrate. A resist is applied on the laminate. In order to reduce the wiring resistance of the gate wiring GL, an Al material having a low wiring resistance is effective.

  As shown in the cross sections A-A ′ and B-B ′, this resist has a two-level resist film thickness by gray-tone exposure (in this case, binary exposure) using the first photomask. Using this first photomask, unnecessary Mo / Al / Mo and ITO are removed at once to form a common electrode COM and a gate wiring GL.

  Next, the resist on the ITO that becomes the common electrode COM and the resist on the gate wiring terminal GT are removed by write ashing. Thereafter, Mo / Al / Mo on the ITO serving as the common electrode COM and Mo / Al / Mo on the gate wiring terminal GT are removed by etching, and then the remaining resist is peeled off.

  In FIG. 1B, an SiN (silicon nitride film) and an a-Si (amorphous silicon) / n + layer, which are gate insulating films, are sequentially formed on the common electrode COM and the gate wiring GL formed by the first photomask. Further, Mo / Al / Mo and ITO to be the drain wiring DL are successively laminated successively on this lamination, and a resist is applied on these laminations.

  As shown in the cross sections C-C ′ and D-D ′, this resist has a three-level resist film thickness by gray-tone exposure (in this case, ternary exposure) using a second photomask. Using this second photomask, unnecessary ITO / Mo / Al / Mo / n + / a-Si is collectively removed to form the drain wiring DL and the pixel electrode PX.

  Next, by the first write ashing, the resist in a part of the opening of the pixel electrode PX is removed, and ITO / Mo / Al / Mo / n + / a-Si in the opening is removed by etching, thereby generating a lateral electric field. The transflective pixel electrode PX is formed by the method.

  Next, the resist of the thin film transistor TFT portion is removed by second light ashing, and ITO / Mo / Al / Mo / n + of the thin film transistor TFT portion is removed by etching, and then the remaining resist is peeled off.

  In FIG. 1C, a protective film PAS is formed on the common electrode COM and the gate wiring GL formed by the first photomask, the drain wiring DL and the pixel electrode PX formed by the second photomask. To do.

  In FIG. 1D, a resist is applied on the protective film PAS. This resist is exposed using a third photomask, and PAS / SiN on the gate wiring terminal GT portion and the drain wiring terminal DT portion is removed by etching as shown in the cross sections EE ′ and FF ′. After exposing the ITO surface connected to the terminal, the resist is peeled off.

  In this embodiment, since the connection surface between the gate wiring terminal GT portion and the drain wiring terminal DT portion is made of ITO, it is difficult to cause electrolytic corrosion, and the ITO in the terminal portion is covered with the protective film PAS and SiN. Moisture in the atmosphere is blocked, and as a result, the reliability of the liquid crystal display device is improved.

  FIG. 2 is a manufacturing process diagram of an IPS type (transverse electric field type) fully transmissive TFT substrate, in which a plan view is shown on the left side of the figure and a cross-sectional view is shown on the right side.

  The difference from the transflective TFT substrate shown in FIG. 1 is that, in FIG. 2B, SiN and a-Si / serving as a gate insulating film are formed on the common electrode COM and the gate wiring GL formed by the first photomask. The point that the n + layer is successively laminated is the same, except that, as shown in the cross sections CC ′ and DD ′, only the ITO that becomes the drain wiring DL is continuously laminated on the laminated layer.

  Therefore, in FIG. 2D, as shown in the cross section F-F ′, Mo / Al / Mo is not stacked on the drain wiring terminal DT portion formed by the third photomask. Other steps are the same as those in FIG.

  In the present embodiment, as shown in the cross section C-C ′, Mo / Al / Mo is not formed in the pixel electrode PX portion, so that the pixel electrode PX can be made to be a totally transmissive type.

  FIG. 3 is a manufacturing process diagram of a transflective TFT substrate by an IPS method (lateral electric field method), showing a plan view on the left side of the drawing and a cross-sectional view on the right side.

  The difference from the transflective TFT substrate shown in FIG. 1 is that, in FIG. 3B, SiN and a-Si / serving as a gate insulating film are formed on the common electrode COM and the gate wiring GL formed by the first photomask. The point that the n + layer is successively laminated is the same, but as shown in the cross sections CC ′ and DD ′, the ITO / Mo / Al serving as the drain wiring DL is successively laminated on the lamination. Different.

  Therefore, as shown in the cross section F-F ′ in FIG. 3D, Al / Mo is exposed in the drain wiring terminal DT portion formed by the third photomask. Other steps are the same as those in FIG.

  In this embodiment, as shown in the cross-section CC ′, the opening of the pixel electrode PX is transmissive, the surface of the pixel electrode PX is made reflective by Al, and the pixel electrode PX is made semi-transmissive and semi-reflective. be able to.

  FIG. 4 is a manufacturing process diagram of a transflective TFT substrate by a VA method (longitudinal electric field method), showing a plan view on the left side and a cross-sectional view on the right side.

  The difference from the transflective TFT substrate shown in FIG. 1 is that ITO is used as the storage capacitor electrode STC in FIG. Accordingly, a common electrode is formed on the color filter substrate facing the pixel electrode PX, and an image is displayed by applying a vertical electric field to the liquid crystal sealed between the common electrode and the pixel electrode PX. .

  Further, the difference from the transflective TFT substrate shown in FIG. 1 is that in FIG. 4B, SiN and a which become a gate insulating film are formed on the storage capacitor electrode STC and the gate wiring GL formed by the first photomask. The point that the -Si / n + layer is successively laminated is the same, but as shown in the cross sections CC 'and DD', ITO / Mo / Al to be the drain wiring DL is successively laminated on the laminated layer. The point to do is different. Further, the drain wiring terminal DT portion is processed in the same manner as the gate wiring terminal GT portion as shown in the cross section E-E ′.

  In FIG. 4A, ITO serving as the storage capacitor electrode STC and Mo / Al / Mo serving as the gate wiring GL are successively stacked on the glass substrate in sequence, and a resist is applied on the stack. In order to reduce the wiring resistance of the gate wiring GL, an Al material having a low wiring resistance is effective.

  As shown in the cross sections A-A ′ and B-B ′, this resist has a two-level resist film thickness by gray-tone exposure (in this case, binary exposure) using the first photomask. Using this first photomask, unnecessary Mo / Al / Mo and ITO are removed at once to form the storage capacitor electrode STC and the gate wiring GL.

  Next, the resist on the ITO and the resist on the gate wiring terminal GT serving as the storage capacitor electrode STC are removed by write ashing. Thereafter, Mo / Al / Mo on the ITO serving as the storage capacitor electrode STC and Mo / Al / Mo on the gate wiring terminal GT are removed by etching, and then the remaining resist is peeled off.

  In FIG. 4B, on the storage capacitor electrode STC and the gate wiring GL formed by the first photomask, a SiN and a-Si / n + layer as a gate insulating film are successively laminated and further laminated. On top of that, ITO / Mo / Al to be the drain wirings DL are successively laminated successively, and a resist is applied on these laminations.

  As shown in the cross sections CC ′, DD ′, and EE ′, this resist is subjected to gray-tone exposure (in this case, ternary exposure) using a second photomask to provide three levels of resist film thickness. And Using this second photomask, unnecessary Al / Mo / ITO / n + / a-Si is removed in a lump to form drain wiring DL and pixel electrode PX.

  Next, as shown in the cross section C-C ′, the resist in the thin film transistor TFT portion is removed and Al / Mo / ITO / n + is removed by etching by the first write ashing.

  Next, by the second write ashing, as shown in the cross sections DD ′ and EE ′, the upper half of the pixel electrode PX part and the drain wiring DL part are removed, and the upper half of the pixel electrode PX part. After the Al / Mo in the drain wiring DL portion is removed by etching, the remaining resist is peeled off.

  In FIG. 4C, the pixel electrode PX is divided into a transmissive part PEN and a reflective part REF, and becomes a transflective type. As described above, the storage capacitor electrode STC and the gate line GL formed by the first photomask, the drain line DL, the transmission part PEN, and the reflection part REF formed by the second photomask are separated. A protective film PAS is formed thereon.

  In FIG. 4D, a resist is applied on the protective film PAS. This resist is exposed using a third photomask, and PAS / SiN on the gate wiring terminal GT portion and the drain wiring terminal DT portion is removed by etching as shown in the cross sections FF ′ and GG ′. After exposing the ITO surface connected to the terminal, the resist is peeled off.

  FIG. 5 is a manufacturing process diagram of a total reflection type TFT substrate by the VA method (vertical electric field method), showing a plan view on the left side of the drawing and a cross-sectional view on the right side.

  A difference from the transflective TFT substrate shown in FIG. 4 is that, as shown in a cross section DD ′ in FIG. It is a point that leaves Al on the surface of PX and makes it a reflective surface. Other steps are the same as those in FIG.

The manufacturing process figure of the transflective TFT substrate by an IPS system (lateral electric field system). The manufacturing process figure of the all-transmissive TFT substrate by an IPS system (lateral electric field system). The manufacturing process figure of the transflective TFT substrate by the IPS system (lateral electric field system). The manufacturing process figure of the transflective TFT substrate by a VA system (vertical electric field system). The manufacturing process figure of the total reflection type TFT substrate by VA system (vertical electric field system).

Explanation of symbols

COM ... Common electrode, GL ... Gate wiring, GT ... Gate wiring terminal, DL ... Drain wiring, PX ... Pixel electrode, TFT ... Thin film transistor, DT ... Drain wiring terminal.

Claims (5)

A plurality of gate wirings, a plurality of drain wirings intersecting with the gate wirings, a pixel electrode disposed at an intersection of the drain wirings and the gate wirings, a thin film transistor formed between the pixel electrodes and the drain wirings, In a liquid crystal display device having a TFT substrate composed of a common electrode that forms an electric field together with a pixel electrode,
The gate wiring and the common electrode are formed with a first photomask,
The drain wiring and the pixel electrode are formed of a second photomask by laminating at least amorphous silicon,
The terminal portion of the gate wiring and drain wiring is covered with at least a protective film and formed with a third photomask. A plurality of gate wirings, a plurality of drain wirings intersecting with the gate wirings, a pixel electrode disposed at an intersection of the drain wirings and the gate wirings, a thin film transistor formed between the pixel electrodes and the drain wirings, In a liquid crystal display device having a TFT substrate composed of a storage capacitor electrode formed under the pixel electrode,
The gate wiring and the storage capacitor electrode are formed by a first photomask,
The drain wiring and the pixel electrode are formed of a second photomask by laminating at least amorphous silicon,
The terminal portion of the gate wiring and drain wiring is covered with at least a protective film and formed with a third photomask.   3. The liquid crystal display device according to claim 1, wherein ITO and Mo / Al / Mo are stacked as the gate wiring, and amorphous silicon and n + are stacked as the drain wiring. A plurality of gate wirings, a plurality of drain wirings intersecting with the gate wirings, a pixel electrode disposed at an intersection of the drain wirings and the gate wirings, a thin film transistor formed between the pixel electrodes and the drain wirings, In a method for manufacturing a liquid crystal display device having a TFT substrate composed of a common electrode that forms an electric field together with a pixel electrode,
The gate wiring and the common electrode are formed with a first photomask, the drain wiring and the pixel electrode are formed with a second photomask, and the terminal portions of the gate wiring and the drain wiring are formed with a third photomask. A method of manufacturing a liquid crystal display device. A plurality of gate wirings, a plurality of drain wirings intersecting with the gate wirings, a pixel electrode disposed at an intersection of the drain wirings and the gate wirings, a thin film transistor formed between the pixel electrodes and the drain wirings, In a method for manufacturing a liquid crystal display device having a TFT substrate composed of a storage capacitor electrode formed under a pixel electrode,
The gate wiring and the storage capacitor electrode are formed with a first photomask, the drain wiring and the pixel electrode are formed with a second photomask, and the terminal portions of the gate wiring and the drain wiring are formed with a third photomask. A method for manufacturing a liquid crystal display device.

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