JP2007290924A - Semiconductor substrate for electronic device, its production method, electronic device, and field-effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To facilitate the improvement of the operation characteristics of an electronic device. <P>SOLUTION: By optimizing crystal growth conditions such as a crystal growth temperature, it is possible to effectively suppress the sublimation of atoms which form the top surface of a semiconductor layer 103 (channel layer A), and in this case, the roughening at the interface between semiconductor layers 103 and 104 can be effectively inhibited. The action of inhibiting the roughening at the interface is ascribable, in addition to the optimization of the crystal growth conditions, to the use of a crystal growth substrate 101 which is constituted from an about 400 μm-thick intrinsic GaN crystal (the semiconductor substrate for an electronic device) produced according the production method. This means that it is very effective and important for making flatter the interface between semiconductor crystal layers build up on the substrate by a crystal growth treatment to use a crystal growth substrate of very high crystal quality. The use of this semiconductor substrate for an electronic device is particularly effective also in this sense. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a flux method in which a semiconductor crystal made of a group III nitride compound semiconductor is grown using a flux, and a semiconductor substrate for electronic devices, an electronic device, and a transistor manufactured using the flux method.
However, the electronic device mentioned here includes a semiconductor element using a semiconductor crystal layer, for example, an amplifier, a switching element, a rectifying element, etc. constituted by a transistor, a diode, etc. And a semiconductor integrated circuit incorporating at least one of a resistor, a capacitor, and an inductor.

  In addition, the above-described transistor may use a field effect or may be a bipolar type. The field effect transistors that can be manufactured according to the present invention include semiconductor elements such as MISFET, MOSFET, HFET, MODFET, JFET, HJFET, and HEMT, and further, power control such as power MOSFET and IGBT. Also included are power transistors and the like.

  The group III nitride compound semiconductor includes a semiconductor crystal composed of binary, ternary, or quaternary InAlGaN having an arbitrary composition ratio, and further includes p-type or n-type impurities. Semiconductors to which etc. are added are also in the category of these “Group III nitride compound semiconductors”.

  According to the conventional Na flux method in which gallium nitride is grown in sodium (Na) flux, a GaN single crystal can be grown at a relatively low temperature of 600 ° C. to 800 ° C. under a pressure of about 5 MPa. it can.

Further, as can be seen from the prior art disclosed in the following Patent Documents 1 to 5, the conventional manufacturing method for growing a group III nitride compound semiconductor crystal by a flux method is usually a base substrate. As the (seed crystal), a template in which a semiconductor layer such as a buffer layer is stacked on a sapphire substrate, a GaN single crystal free-standing substrate, or the like is exclusively used.
Japanese Patent Laid-Open No. 11-060394 JP 2001-058900 A JP 2001-064097 A JP 2004-292286 A Japanese Patent Laid-Open No. 2004-300024

  In particular, when manufacturing a field effect transistor, the generation control and extinction control of the two-dimensional electron gas formed near the interface of the semiconductor crystal layer can be facilitated, the sheet resistance can be reduced, and the element drive voltage can be reduced. The crystal quality of these semiconductor element substrates is very important when reducing the leakage current and the like, or improving the electrostatic withstand voltage performance, life, and yield of the elements.

However, with the conventional Na flux method, it has been difficult to obtain a high-quality semiconductor crystal having a low dislocation density and a substantially flat crystal growth surface. In addition, the conventional Na flux method has a problem in the crystal growth rate and yield, and it has been difficult to put it into practical use for a semiconductor substrate for electronic devices. These problems also applies to _{In x Al y Ga 1-xy} N (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ x + y ≦ 1) other Group III nitride compound semiconductor crystal growth consisting of It is.

  In addition, when a template such as that described above is used, there is a large difference in thermal expansion coefficient between a desired semiconductor crystal made of a group III nitride compound semiconductor and a sapphire substrate. When a semiconductor crystal is taken out from the reaction chamber, many cracks are generated in the crystal. For this reason, when the above template is used as the base substrate, it is difficult to obtain a high-quality semiconductor crystal having a film thickness of 300 μm or more, for example.

The present invention has been made to solve the above-described problems, and an object of the present invention is to produce a high-quality semiconductor substrate for electronic devices at a low cost by the flux method.
A further object of the present invention is to facilitate the improvement of the operating characteristics of any of the aforementioned electronic devices configured using semiconductors.

In order to solve the above problems, the following means are effective.
That is, the first means of the present invention is gallium (Ga), aluminum (Al) or indium (In) in a mixed flux having a plurality of types of metal elements selected from alkali metals or alkaline earth metals. In the method for producing a semiconductor substrate for an electronic device in which a group III nitride compound semiconductor crystal is grown by reacting a group III element) with nitrogen (N), the mixed flux and the group III element are stirred and mixed. However, it is to grow group III nitride compound semiconductor crystals.

  However, the stirring and mixing process in the present invention may be carried out by physically moving the reaction vessel by swinging, rotating, rotating, or the like, or stirring the flux using a stirring bar or a stirring blade. Alternatively, the heat flux may be generated by using a heating means or the like to generate a thermal gradient in the flux and thereby heat convection the flux. That is, the processing method of stirring and mixing in the present invention may be arbitrary. Also, these methods may be implemented in any appropriate combination.

  The second means of the present invention is a mixed flux having a plurality of types of metal elements selected from alkali metals or alkaline earth metals, and includes gallium (Ga), aluminum (Al) or indium (In In the method of manufacturing a semiconductor substrate for an electronic device in which a group III nitride compound semiconductor crystal is grown by reacting a group III element) with nitrogen (N), the group III nitride compound semiconductor crystal is grown. A soluble material that dissolves in the mixed flux is used for at least a part of the base substrate to be used, and the soluble material is used during the crystal growth process of the group III nitride compound semiconductor crystal or the crystal of the group III nitride compound semiconductor crystal. It is to dissolve in the mixed flux near the growth temperature after the growth process.

However, silicon (Si) or the like can be used as the soluble material, but it is not necessarily limited to this.
Further, a protective film is formed on the exposed surface of the soluble material, and the timing or dissolution rate of the soluble material is dissolved in the flux according to the thickness or pattern of the protective film. Is also possible. As a material for such a protective film, for example, aluminum nitride (AlN), tantalum (Ta), or the like can be used. These protective films are formed by a known method such as crystal growth, vacuum deposition, or sputtering. be able to.

According to a third means of the present invention, in the second means, at least a part of the soluble material contains an impurity to be added to the group III nitride compound semiconductor crystal. is there.
However, you may comprise the whole soluble material only with the required impurity.

Further, a fourth means of the present invention is the above-described second or third means, wherein the group III nitride compound semiconductor crystal is grown while stirring and mixing the mixed flux and the group III element. is there.
However, the same optionality as described above can be allowed even in the embodiment of the stirring and mixing process in this case.

According to a fifth means of the present invention, in any one of the first to fourth means, the mixed flux is configured using lithium (Li) or calcium (Ca) and sodium (Na). It is to be.
That is, the second main component next to Na of the mixed flux to be used is at least one of lithium (Li) and calcium (Ca).

A sixth means of the present invention is the method according to any one of the first to fifth means described above, in which a hydrogen (H ₂ ) gas, nitrogen ( N ₂ ) gas, ammonia (NH ₃ ) gas, rare gas (He, Ne, Ar, Kr, Xe, or Rn) or a mixed gas in which two or more of these gases are mixed at an arbitrary mixing ratio And cleaning the crystal growth surface of the seed crystal or the base substrate at a temperature of 900 ° C. or higher and 1100 ° C. or lower and taking a time of 1 minute or longer.
However, the time required for these cleaning processes is more preferably 2 minutes or more and 10 minutes or less.

In addition, according to a seventh means of the present invention, in any one of the first to sixth means, boron (B), an impurity to be added to a desired group III nitride compound semiconductor crystal, Thallium (Tl), calcium (Ca), compounds containing calcium (Ca), silicon (Si), sulfur (S), selenium (Se), tellurium (Te), carbon (C), oxygen (O), aluminum ( Al), indium (In), alumina (Al ₂ O ₃ ), indium nitride (InN), silicon nitride (Si ₃ N ₄ ), silicon oxide (SiO ₂ ), indium oxide (In ₂ O ₃ ), zinc (Zn) ), Iron (Fe), magnesium (Mg), zinc oxide (ZnO), magnesium oxide (MgO), or germanium (Ge) is included in the mixed flux.
These impurities may contain only 1 type, and may contain multiple types simultaneously. These selections and combinations may be arbitrary.

According to an eighth aspect of the present invention, in the semiconductor substrate for an electronic device manufactured by the method for manufacturing a semiconductor substrate for an electronic device according to any one of claims 1 to 7, the dislocation density on the surface thereof. ^Is 1 × 10 ⁵ cm ⁻² or less, and its maximum diameter is 1 cm or more.
However, the dislocation density is preferably as low as possible and the maximum diameter is as large as possible. In particular, in view of industrial practicality, the desired semiconductor substrate is more preferably a circular one having a diameter of about 50 mm to 150 mm.

According to a ninth means of the present invention, in the eighth means, the thickness of the semiconductor substrate for electronic devices is 300 μm or more.
However, the thickness of the semiconductor substrate is more preferably 400 μm or more, and more preferably about 400 μm to 600 μm.

  According to a tenth aspect of the present invention, in the electronic device configured by laminating a semiconductor crystal layer made of a group III nitride compound semiconductor on a crystal growth substrate, the crystal growth substrate is defined in claim 8 or It is comprised from the semiconductor substrate for electronic devices of Claim 9.

  However, the electronic device mentioned here includes a semiconductor element using a semiconductor crystal layer, for example, an amplifier, a switching element, a rectifying element, etc. constituted by a transistor, a diode, etc. And a semiconductor integrated circuit incorporating at least one of a resistor, a capacitor, and an inductor. In addition, the above-described transistor may use a field effect or may be a bipolar type.

The eleventh means of the present invention is a field effect transistor formed by crystal growth of a semiconductor crystal layer made of a group III nitride compound semiconductor. A semiconductor substrate; a channel layer A crystal-grown directly or indirectly on the semiconductor substrate for electronic devices; and a carrier supply layer B crystal-grown directly on the channel layer A, and at least the channel layer described above In the vicinity of the interface between A and the carrier supply layer B, the band gap energy E _B of the carrier supply layer B is made larger than the band gap energy E _A of the channel layer A.

However, the field effect transistors include semiconductor elements used at high frequencies such as MISFET, MOSFET, HFET, MODFET, JFET, HJFET, and HEMT, and further, power control transistors such as power MOSFET and IGBT. Etc. are also included.
A twelfth means of the present invention is that, in the eleventh means, at least one of the channel layer A and the carrier supply layer B is formed from an additive-free semiconductor crystal.

According to a thirteenth means of the present invention, in the eleventh or twelfth means, the channel layer A is formed of binary or ternary Al _x Ga _1-x N (0 ≦ x <1). The carrier supply layer B is formed of ternary Al _y Ga _1-y N (x <y ≦ 1).

  Further, a fourteenth means of the present invention is the method according to any one of the eleventh to thirteenth means, by suppressing the sublimation action of the atoms of the channel layer A forming the vicinity of the interface, The above-mentioned interface is formed substantially flat.

However, in this case, the channel layer A is more preferably formed of GaN crystal, and the carrier supply layer B is formed of Al _y Ga _1-y N (0.15 ≦ y ≦ 0.30). It is more desirable to do.

According to a fifteenth means of the present invention, in any one of the eleventh to fourteenth means, the carrier supply layer B is made of Al _y Ga _1-y N (0.45>y> 0.04). And the aluminum composition ratio y of the carrier supply layer B is substantially monotonously reduced with respect to the distance from the interface.

In this case, however, the aluminum composition ratio y of the carrier supply layer B at the interface is more preferably 0.15 or more and 0.40 or less, and the aluminum composition ratio y at the other interface of the carrier supply layer B is 0. It is more desirable that it is 0.05 to 0.20.
By the above means of the present invention, the above-mentioned problem can be effectively or rationally solved.

The effects obtained by the above-described means of the present invention are as follows.
That is, according to any one of the first to seventh means of the present invention, a high-quality semiconductor crystal can be efficiently produced at a low cost by the flux method. The semiconductor substrate for electronic devices having the feature of item 9 can be manufactured with high quality and efficiency at a realistic production level.

  In particular, according to the first means of the present invention, the dissolution rate of nitrogen in the mixed flux effectively increases based on the stirring and mixing treatment, and the crystal material is uniformly distributed in the flux. Further, such an ideal flux can be constantly supplied to the crystal growth surface without unevenness. Therefore, according to the first means of the present invention, a high-quality semiconductor substrate for electronic devices having a low dislocation density and a substantially flat crystal growth surface can be obtained. In addition, these high-quality semiconductor substrates for electronic devices can be easily grown large in a desired bulk shape based on the high crystal growth rate and yield due to the above-described action.

Further, according to the second means of the present invention, the soluble material is dissolved in the flux during the semiconductor crystal growth step or near the semiconductor crystal growth temperature after the semiconductor crystal growth step. The stress does not act between the base substrate and the semiconductor crystal (semiconductor substrate for electronic devices) due to the temperature lowering action when taking out the desired semiconductor crystal from the reaction chamber. Therefore, according to the second means of the present invention, the density of occurrence of cracks in the desired semiconductor substrate for electronic devices can be greatly reduced as compared with the prior art.
In addition, as the above-described soluble material, for example, a relatively inexpensive material such as silicon (Si) can be used, so that the production cost is lower than the conventional case where a GaN single crystal free-standing substrate is used as a base substrate. It can be kept cheap.

  Further, if the phenomenon that the soluble material is dissolved in the flux is used as the impurity addition process by the third means of the present invention, it is necessary to add an impurity to the semiconductor substrate for a desired electronic device. It is not necessary to carry out the impurity addition process by another method. At the same time, the necessary impurity material can be saved.

  Further, according to the fourth means of the present invention, also in the second or third means, it is possible to obtain the same action and effect as the action and effect of the stirring and mixing process in the first means. .

  In addition, according to the fifth means of the present invention, the yield and growth rate of the semiconductor crystal can be suitably or optimally adjusted based on the mixing ratio of lithium (Li) or calcium (Ca) in the flux. Thereby, the productivity of a desired semiconductor substrate for an electronic device can be adjusted suitably or optimally.

  In addition, according to the sixth means of the present invention, foreign substances or impurities on the crystal growth surface on which a semiconductor crystal is to be grown can be favorably excluded from the crystal growth surface. Crystals can be grown with good quality.

  Further, according to the seventh means of the present invention, a semiconductor substrate for an electronic device having desired electric conduction characteristics and a band gap can be arbitrarily grown.

Further, according to the eighth means of the present invention, a semiconductor substrate for electronic devices useful as a base material constituting the electronic device can be manufactured at a practical level with good quality and low cost.
In addition, since the semiconductor substrate for electronic devices of the present invention has a crystal quality that is very superior to that of the conventional one, the crystal quality of the semiconductor crystal layer formed thereon is also increased based on the crystal growth treatment. For this reason, the characteristics (eg, sheet resistance) of the desired electronic device described above can be improved better than the conventional one. Further, as the crystal quality of the substrate is improved, the thermal conductivity of the substrate is also increased, so that it is possible to obtain a higher heat dissipation effect than before.

  According to the ninth means of the present invention, it is possible to prevent the yield of the electronic devices from being lowered by cracking or scratching the semiconductor substrate for electronic devices during the production of the electronic devices. .

According to the tenth means of the present invention, since a semiconductor substrate for electronic devices having a good quality is used as a crystal growth substrate for the electronic device, each semiconductor crystal layer constituting the electronic device is formed with a good quality.
Therefore, according to the tenth means of the present invention, an electronic device having excellent operating characteristics such as sheet resistance and leakage current can be manufactured. Further, by setting the thickness of the semiconductor substrate for electronic devices to 300 μm or more, it is possible to ensure a high yield of desired electronic devices.

  According to the eleventh means of the present invention, it is possible to satisfactorily form a two-dimensional electron gas at the interface between the channel layer A and the carrier supply layer B. It can be satisfactorily formed in the transistor. Therefore, according to the eleventh means of the present invention, a field effect transistor excellent in operating characteristics can be manufactured.

  According to the twelfth means of the present invention, since the channel layer A or the carrier supply layer B can be a high-quality semiconductor crystal layer, the carrier mobility at the interface can be increased. Therefore, according to the twelfth means of the present invention, a channel layer having a low sheet resistance can be formed.

  According to the thirteenth means of the present invention, the difference in band gap between the channel layer A and the carrier supply layer B can be appropriately ensured while improving the crystal quality of each semiconductor crystal layer. Therefore, the channel layer A is more preferably formed from an undoped GaN crystal layer. In order to reduce the leakage current to the gate electrode, it is more desirable to form the carrier supply layer B from an undoped AlGaN crystal layer.

  In addition, according to the fourteenth means of the present invention, the interface between the channel layer A and the carrier supply layer B can be formed flatter than before, so that carrier scattering at the interface is less likely to occur. Therefore, according to the fourteenth means of the present invention, a channel layer having a low sheet resistance can be formed.

Further, according to the fifteenth means of the present invention, it is possible to appropriately ensure a difference in both band gaps at the interface between the channel layer A and the carrier supply layer B while improving the crystal quality of the carrier supply layer B. it can. Therefore, according to the fifteenth means of the present invention, a carrier supply layer with a small leakage current and a channel layer with a low sheet resistance can be formed simultaneously.
The above-described means of the present invention makes it possible to solve the above problems easily or rationally.

  The film formation pattern that can be formed on the exposed surface of the soluble material according to claim 2 can be formed by a known technique such as photolithography or etching. In addition, the dissolution time can be advanced as the thickness of these protective films decreases, and the dissolution rate should be set higher as the exposed area of the soluble material with respect to the flux becomes wider. Can do. That is, according to these settings, the dissolution of the soluble material is started from the time when the exposed surface of the soluble material comes into contact with the high-temperature flux, and the dissolution rate is approximately equal to the area of the exposed surface. Therefore, by appropriately adjusting these setting conditions, it is possible to arbitrarily adjust the dissolution start time, the required dissolution time, the dissolution rate, and the like of the above-described soluble material. In addition, the time required for dissolving the above-mentioned soluble material can be arbitrarily adjusted by the type, thickness, flux temperature, etc. of the soluble material.

The seed crystal used for crystal growth by the flux method and the method for producing the base substrate may be arbitrary, and the flux method, HVPE method, MOVPE method, MBE method, etc. are effective. The size and thickness may be arbitrary, but considering industrial practicality, a circular one having a diameter of about 50 mm to 150 mm is more desirable. Further, it is desirable that the radius of curvature of the crystal growth surface of the seed crystal or the base substrate is larger.
The lower the dislocation density of the seed crystals and the underlying substrate, the better. However, this is not necessarily the case when the method of any one of claims 2 to 4 is used. That is, in this case, if the dislocation density is too low, the above soluble material (underlying substrate) may be difficult to dissolve in the flux.

Moreover, as a crystal growth apparatus to be used, any apparatus capable of performing the flux method may be used. For example, the apparatus described in Patent Documents 1 to 5 can be applied or applied. However, it is desirable that the temperature of the reaction chamber of the crystal growth apparatus when performing crystal growth according to the flux method can be arbitrarily controlled to rise and fall to about 1000 ° C. Further, it is desirable that the pressure in the reaction chamber can be arbitrarily controlled to increase or decrease to about 100 atm (about 1.0 × 10 ⁷ Pa). Moreover, it is desirable that the electric furnace, stainless steel container (reaction container), raw material gas tank, and piping of these crystal growth apparatuses are formed of, for example, a stainless steel (SUS) material, an alumina material, copper, or the like.

  In particular, when the field effect transistor according to claim 14 is manufactured, for example, as an important parameter governing the crystal growth condition for suppressing the sublimation action of atoms forming the vicinity of the surface of the channel layer A, For example, the crystal growth temperature, the partial pressure of various material gases, the type of carrier gas, the partial pressure of the carrier gas, the V / III ratio, the crystal growth rate, etc. can be considered. Therefore, for example, when Ga atoms of the GaN crystal are particularly easily sublimated, for example, a measure such as setting the partial pressure of trimethylgallium (TMG) to be relatively high or absolute can be considered.

Further, it is preferable crystal growth temperature T _B of the carrier supply layer B at that time is lower than the crystal growth temperature T _A of the channel layer A described above.
Further, it is effective in preventing the rough surface may be a crystal growth pressure P _B of the carrier supply layer B is substantially coincident with the crystal growth pressure P _A of the channel layer A.

In particular, the aluminum composition ratio x is substantially 0, the aluminum composition ratio y is 0.15 or more and 0.30 or less, and the crystal growth pressures P _A and P _B are both substantially normal pressures. It is desirable to set the growth temperatures T _A and T _B so that the conditional expression “950 ° C. ≦ T _B <T _A ” is satisfied.
Furthermore, the crystal growth temperature T _A of the channel layer A more desirable when the 1200 ° C. or less. It is also important to increase 50 ° C. or higher than the crystal growth temperature T _B of the crystal growth temperature T _A carrier supply layer B of the channel layer A. An appropriate range that seems to be more desirable for this temperature difference is between 50 ° C. and 150 ° C.

Further, more desirably, it is to set the crystal growth temperature T _B of the carrier supply layer B as a "950 ℃ ≦ T _B <1050 ℃". In the ninth means of the present invention, the crystal growth temperature T _A of the channel layer A is preferably set to satisfy “1050 ° C. <T _A ≦ 1150 ° C.” in the eighth means.
In addition, the aluminum composition ratio of the channel layer A is preferably approximately 0, and the aluminum composition ratio of the carrier supply layer B is preferably 0.15 or more and 0.30 or less. It is also important that the thickness of the carrier supply layer B is 1 nm or more. A more desirable thickness of the carrier supply layer B is 5 nm or more.
By the above optimization, the interface between the channel layer A and the carrier supply layer B in the field effect transistor according to claim 14 can be effectively flattened.

In particular, when the field effect transistor according to claim 15 is manufactured, the aluminum composition ratio x1 at the interface of the carrier supply layer B is preferably 0.15 or more and 0.40 or less. However, more preferably, the aluminum composition ratio x1 is 0.19 or more and 0.25 or less.
The aluminum composition ratio x2 at the other interface opposite to the above-mentioned interface of the carrier supply layer B at that time is preferably 0.05 or more and 0.20 or less. However, more desirably, the aluminum composition ratio x2 is 0.13 or more and 0.17 or less.

  Further, in a particularly desirable embodiment of the field effect transistor according to claim 15, when the aluminum composition ratio x of the carrier supply layer B is decreased from 0.20 to 0.15 substantially monotonously with respect to the above distance. good.

In addition, at least a part of the group III elements (Al, Ga, In) constituting the semiconductor crystal layers for forming the semiconductor substrate for electronic devices and the electronic devices of the present invention is boron (B) or thallium (Tl). Or at least part of nitrogen (N) may be substituted with phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), or the like.
Moreover, as said p-type impurity (acceptor), well-known p-type impurities, such as magnesium (Mg) or calcium (Ca), can be added, for example.

As the n-type impurity (donor), for example, known n-type impurities such as silicon (Si), sulfur (S), selenium (Se), tellurium (Te), or germanium (Ge) are used. Can be added.
Moreover, two or more elements may be added simultaneously to these impurities (acceptor or donor), or both types (p-type and n-type) may be added simultaneously.
Also, by adding zinc (Zn), iron (Fe), carbon (C), magnesium (Mg), etc., a high-resistance semiconductor crystal layer or a high-resistance semiconductor substrate for electronic devices can be manufactured. Good.

  As a method of laminating a semiconductor crystal layer made of a group III nitride compound semiconductor on the semiconductor substrate for electronic devices, molecular beam vapor phase epitaxy (MBE), metal organic vapor phase epitaxy (MOVPE) Crystal growth methods such as hydride vapor phase epitaxy (HVPE) and liquid phase epitaxy are effective.

Hereinafter, the present invention will be described based on specific examples.
However, the embodiments of the present invention are not limited to the following examples.

A cross-sectional view of the crystal growth apparatus used in Example 1 is shown in FIG.
1. Crystal Growth Device This crystal growth device is for growing a desired semiconductor crystal on the crystal growth surface of the substrate 8 by the flux method. In the heating vessel 2 disposed inside the heat and pressure resistant vessel 1, The gas introduction pipe 4 for introducing the nitrogen-containing gas 7 is connected. A shaft 6 extending from the rocking device 5 is connected to the opposite side of the heating container 2 so as to be coaxial with the gas introduction pipe 4. The oscillating device 5 includes a motor and a motor control device. In the reaction vessel 3 made of boron nitride, the mixed flux and the substrate 8 are put.

2. Crystal Growth by Flux Method Crystal growth for crystal growth of a gallium nitride single crystal using the crystal growth apparatus of FIG. 1 will be described below.
(1) First, a GaN film having a thickness of 3 μm was formed on the crystal growth surface of the sapphire substrate by the MOVPE method, thereby completing the substrate 8 of FIG.
(2) Next, the substrate 8 was placed at the bottom of the reaction vessel 3, and sodium (Na) and lithium (Li) were further added to the reaction vessel 3. At this time, the amount of sodium (Na) was about 8.8 g, and the amount of lithium (Li) was about 0.027 g. When converted to a molar ratio, it is 99: 1.

(3) Next, the reaction vessel 3 was set in the heating vessel 2, and the reaction vessel 3 was tilted in a certain direction. With this setting, the substrate 8 was set so as not to touch the mixed flux of sodium (Na) and lithium (Li).

(4) Next, nitrogen gas (N ₂ ) heated to about 1000 ° C. was passed through the reaction chamber for about 30 minutes to clean the crystal growth surface of the substrate 8. At this time, the gas pressure in the heating container 2 is periodically changed between about 0 to 10 atm (1 to 10 × 10 ⁵ Pa), and nitrogen (N ₂ ) gas is poured into the heating container 2 ( Cleaning gas inflow / exhaust treatment was performed by repeating compression and exhaust.

(5) Thereafter, nitrogen gas was newly introduced, the gas pressure in the heating container 2 was increased to 10 atm (about 10 × 10 ⁵ Pa), and the temperature was set to 890 ° C.
(6) Thereafter, the reaction vessel 3 is swung using the rocking device 5 to move the raw material liquid 9 (mixed flux) back and forth as illustrated in FIGS. 2-A, -B, and -C. Thus, the crystal growth surface of the GaN film was always covered with the thin mixed flux 9. In addition, the temperature and pressure were maintained constant for 4 hours while continuing this oscillation. The oscillation cycle at this time may be about 1 to several reciprocations per minute.

(7) Then, with the reaction vessel 3 tilted so that the flux does not touch the substrate 8, the temperature is lowered and lowered to about room temperature and normal pressure, and the substrate 8 is taken out from the heating vessel 2, and the substrate 8 is placed around the substrate 8. The adhered flux (Na, Li) was removed using ethanol. Thus, a bulk GaN single crystal having a uniform thickness obtained by crystal growth on the substrate 8 was obtained.
The sapphire substrate is then removed by polishing or laser lift-off.

The thickness of the GaN single crystal obtained by the above method was about 10 μm, and the maximum diameter was 5 cm or more.
Moreover, when photoluminescence was measured about this GaN single crystal under normal temperature, the intensity | strength of 10 mW or more was shown with respect to the excitation light of wavelength 325nm.
Further, when the XRD peak half width of the X-ray reflected from the (100) plane was measured, it was 100 arc.sec or less.
From the above, it can be seen that, for example, a desired high-quality semiconductor substrate for an electronic device having a low dislocation density of 400 μm can be obtained by performing the above-described crystal growth treatment for about 160 hours.

  In the above crystal growth, the second main component of the mixed flux is lithium (Li), but calcium (Ca) may be used instead of lithium (Li) as the second main component of the mixed flux. . Further, in addition to lithium (Li), calcium (Ca) may be used.

Boron (B), thallium (Tl), calcium (Ca), compounds containing calcium (Ca), silicon (Si), sulfur (S), selenium (Se), tellurium (Te), carbon (C), Oxygen (O), aluminum (Al), indium (In), alumina (Al ₂ O ₃ ), indium nitride (InN), silicon nitride (Si ₃ N ₄ ), silicon oxide (SiO ₂ ), indium oxide (In ₂ O ₃ ), zinc (Zn), iron (Fe), magnesium (Mg), zinc oxide (ZnO), magnesium oxide (MgO), germanium (Ge), etc. The impurities can be added to a desired GaN single crystal, and according to such a method, the conduction characteristics of a semiconductor substrate for a desired electronic device can be controlled to be conductive or semi-continuous. Or it can be controlled to sex.

A procedure for creating the base substrate (template 10) used in the crystal growth process by the flux method in the second embodiment will be described below with reference to FIG.
1. Preparation of base substrate (1) First, the protective film 15 is formed on the back surface of the silicon substrate 11 (the soluble material of the present application). The protective film 15 may be formed by laminating an AlN layer according to, for example, the MOVPE method, or an appropriate metal such as tantalum (Ta) may be formed using a sputtering apparatus or a vacuum evaporation apparatus. Anyway.

(2) Next, by crystal growth according to the MOVPE method, a buffer layer 12 made of AlGaN is laminated on a silicon substrate 11 having a thickness of about 400 μm, and a GaN layer 13 is further laminated thereon. This GaN layer 13 may be partially dissolved in the flux until the growth of the desired semiconductor crystal by the flux method is started. Therefore, the GaN layer 13 is laminated so as not to disappear at that time.
The template 10 (underlying substrate) can be produced by the above steps (1) and (2).

2. Configuration of Crystal Growth Device FIGS. 4A and 4B are configuration diagrams of the crystal growth device according to the first embodiment. This crystal growth apparatus includes a raw material gas tank 21 for supplying nitrogen gas, a pressure regulator 22 for adjusting the pressure of the growth atmosphere, a leak valve 23, and an electric furnace 25 for performing crystal growth. The piping connecting the raw material gas tank 21 and the electric furnace 25 is made of a stainless steel (SUS) or alumina material, copper, or the like.

A stainless steel container 24 (reaction chamber) is disposed inside the electric furnace 25, and a crucible 26 (reaction container) is set in the stainless steel container 24. The crucible 26 can be formed of, for example, boron nitride (BN) or alumina (Al ₂ O ₃ ).
The temperature in the electric furnace 25 can be arbitrarily controlled to rise and fall within a range of 1000 ° C. or less. Further, the pressure in the crystal atmosphere in the stainless steel container 24 is arbitrarily controlled by the pressure regulators 22 and 29, the leak valve 23, etc. within a range of 1.0 × 10 ⁷ Pa or less via the pipe 28. be able to.

  FIG. 4-B shows a cross-sectional view of the stainless steel container 24. A side wall 27 of the reaction chamber is formed in a cylindrical shape, and a heater H for heating is disposed in a ring shape on the outer lower portion of the foot. The heater H is for generating thermal convection in the mixed flux 9 in the crucible 26 by heating the crucible 26 (reaction vessel) through the bottom of the reaction chamber.

3. Crystal Growth Process Hereinafter, the crystal growth process of the present example using the crystal growth apparatus of FIGS. 4-A and -B will be described with reference to FIGS.
(1) First, sodium (Na), lithium (Li), and Ga which is an element III are put into a reaction vessel (crucible 26), and the reaction vessel (crucible 26) is used as a reaction chamber (stainless steel vessel) of a crystal growth apparatus. 24), the gas in the reaction chamber is exhausted. However, the molar ratio of sodium (Na) to lithium (Li) was 99: 1. In addition, if necessary, any of the above-mentioned additives such as alkaline earth metals may be introduced into the crucible in advance. In addition, when these operations are performed in the air, Na is immediately oxidized, so the operation of setting the substrate and raw materials in the reaction vessel is performed in a glove box filled with an inert gas such as Ar gas. .

(2) Next, the gas pressure in the reaction chamber is periodically varied between about 0 to 10 atm (1 to 10 × 10 ⁵ Pa), and nitrogen (N ₂ ) gas is poured into the reaction chamber (compression). ) And evacuation are repeated to clean the crystal growth surface of the substrate. The processing temperature at this time is 900 ° C., and the cleaning processing time is about 30 minutes.

(3) Next, while adjusting the temperature of the crucible between 850 ° C. and 880 ° C., nitrogen gas (N ₂ ) is newly fed into the reaction chamber of the crystal growth apparatus in parallel with this temperature adjustment step. The gas pressure in the reaction chamber is maintained at about 3 to 5 atmospheres (3 to 5 × 10 ⁵ Pa). At this time, the protective film 15 of the template 10 is immersed in the melt (mixed flux) generated as a result of the temperature rise, and the crystal growth surface of the template 10, that is, the exposed surface of the GaN layer 13 is melted. It is arranged near the interface between the liquid and nitrogen gas.

(4) Thereafter, the heater H in FIG. 4-B is heated to generate thermal convection of the mixed flux 9, thereby continuously agitating and mixing the flux while maintaining the crystal growth conditions of (3) above. Maintained.

  By setting the conditions as described above, the vicinity of the interface between the melt of Ga and Na and the nitrogen gas is continuously supersaturated with the material atoms of the group III nitride compound semiconductor, so that the desired semiconductor crystal (n The type GaN single crystal 20) can be grown smoothly from the crystal growth surface of the template 10 (FIG. 3) (FIG. 5-A). Here, the n-type conductive semiconductor crystal (n-type GaN single crystal 20) is obtained because the silicon substrate 11 melted in the flux is added to the growing crystal as an n-type additive (Si). (FIG. 5-B).

  However, the protective film 15 may be thickly stacked so that the silicon substrate 11 does not melt into the flux during the crystal growth process. In this case, a semi-insulating semiconductor substrate for electronic devices that is not doped with silicon (Si) can be crystal-grown.

4). Dissolution of crystal growth substrate When the n-type GaN single crystal 20 is grown to a sufficient film thickness of, for example, about 500 μm or more by the above crystal growth process, the temperature of the crucible is continuously maintained at 850 ° C. or more and 880 ° C. or less for protection. Waiting for all of the film 15 and the silicon substrate 11 to dissolve in the flux (FIGS. 5-B to C), the gas pressure of nitrogen gas (N ₂ ) is changed to 3 to 5 atm (3 to 5 × 10 ⁵ Pa). ) The temperature of the reaction chamber is lowered to 100 ° C. or lower while maintaining the degree.

  However, the step of dissolving the silicon substrate 11 in the flux and the above-described temperature lowering step may be performed in some overlap. Further, for example, as described above, at least a part of the protective film 15 and the silicon substrate 11 may be dissolved in the flux during the growth process of the GaN single crystal 20. The mode of parallel and simultaneous progress of these steps can be appropriately adjusted depending on, for example, the form of the protective film 15.

5). Flux removal Next, the n-type GaN single crystal 20 (desired semiconductor crystal) is taken out from the reaction chamber of the crystal growth apparatus, the temperature is lowered to 30 ° C. or lower, and the surroundings are also maintained at 30 ° C. or lower. Then, the flux (Na) attached around the n-type GaN single crystal 20 is removed using ethanol.

  By sequentially executing the above steps, a low-cost conductive electronic device semiconductor substrate (n-type GaN single crystal 20) having a thickness of 400 μm or more with significantly fewer cracks than conventional ones can be produced at low cost. Can be manufactured. In addition, if impurities such as Fe are included in the flux, the conduction characteristics of the semiconductor substrate can be controlled based on the amount of addition of the impurities, and thus, for example, a semi-insulating electronic device substrate can be manufactured. Is also possible.

  FIG. 6 is a schematic cross-sectional view showing a stacked structure of the field effect transistor 100 of the third embodiment. This field effect transistor 100 is a semiconductor element formed by sequentially laminating group III nitride compound semiconductors by crystal growth, and the crystal growth substrate 101 is formed according to the manufacturing method of Example 1 or Example 2 above. It is made of a semi-insulating GaN crystal having a bulk thickness of about 400 μm and having excellent crystallinity with no added impurities.

A semiconductor layer 103 made of undoped GaN having a thickness of about 2 μm is formed on the crystal growth substrate 101. The semiconductor layer 103 corresponds to the channel layer A described in claim 11. A semiconductor layer 104 made of undoped Al _0.25 Ga _0.75 N having a thickness of about 35 nm corresponding to the carrier supply layer B according to claim 11 is laminated on the semiconductor layer 103 (channel layer A). . The film thickness of the semiconductor layer 104 (carrier supply layer B) is such that the two-dimensional electron gas layer generated near the interface between the semiconductor layers A and B when the gate is turned on, and the following individual ohmic electrodes (105 and 107) The tunnel effect of carriers (electrons) between the two is set so as to surely and satisfactorily appear.

  Reference numerals 105, 106, and 107 denote a source electrode (ohmic electrode), a gate electrode (Schottky electrode), and a drain electrode (ohmic electrode), respectively. Each ohmic electrode (source electrode 105 and drain electrode 107) is formed by laminating a thin metal layer made of titanium (Ti) with a thickness of about 100 mm and depositing aluminum (Al) thereon with a thickness of about 3000 mm. A metal layer is further laminated by vapor deposition. These ohmic electrodes are well adhered and alloyed by heat treatment at about 700 ° C. to 900 ° C. by flash annealing for less than 1 second. On the other hand, the gate electrode 106 is a Schottky electrode formed by depositing a metal layer made of nickel (Ni) of about 100% by vapor deposition, and further depositing a metal layer made of gold (Au) on the metal layer. .

Hereinafter, a method of manufacturing the field effect transistor 100 will be described focusing on the semiconductor crystal layers A and B (the semiconductor layers 103 and 104) according to claim 11.
Each of the semiconductor layers (semiconductor layers 103 and 104) of the field effect transistor 100 is crystal-grown by vapor phase growth by metal organic compound vapor phase epitaxy (MOVPE). The gases used here are carrier gas (H ₂ or N ₂ ), ammonia gas (NH ₃ ), trimethyl gallium (Ga (CH ₃ ) ₃ ), trimethyl aluminum (Al (CH ₃ ) ₃ ), etc. It is.

FIG. 7 shows the crystal growth conditions of the semiconductor layers A and B of the field effect transistor 100 of the third embodiment. As can be seen from FIG. 7, the crystal growth of the semiconductor layer 103 (that is, the channel layer A of the present invention) made of an undoped GaN crystal having a thickness of about 2 μm constituting the field effect transistor 100 is performed under the following crystal growth conditions. It carried out according to.
(Crystal growth conditions for semiconductor layer A)
(1) Crystal growth temperature T _A : 1100 [° C.]
(2) Crystal growth pressure P _A : 1013 [hPa]

Next, the crystal growth of the semiconductor layer 104 (that is, the carrier supply layer B according to claim 11) made of an undoped Al _0.25 Ga _0.75 N crystal having a thickness of about 35 nm is performed according to the following crystal growth conditions. did.
(Crystal growth conditions for semiconductor layer B)
(1) Crystal growth temperature T _B : 1000 [° C.]
(2) Crystal growth pressure P _B : 1013 [hPa]

In this configuration, the crystal growth temperatures T _A and T _B and the crystal growth pressures P _A and P _{B of} the first and second semiconductor layers A and B (semiconductor layers 103 and 104) are both the same. It is characterized in that the following formula (2) is satisfied. The following formula (1) describes a typical setting example of crystal growth conditions in the manufacturing process of the conventional transistor 900 (FIG. 11) for comparison and comparison with the third embodiment.

(Conventional crystal growth conditions)
T _B > T _A ,
P _B <P _A (1)
(Crystal growth conditions of Example 3)
1000 ° C. = T _B <T _A = 1100 ° C.
P _B = P _A = (Normal pressure) (2)
Under the crystal growth condition of the formula (2), after the semiconductor layer 103 (channel layer A) is stacked by 2 μm, the crystal growth temperature in the crystal growth furnace is lowered, and the crystal growth pressure is maintained at a substantially normal pressure as it is. The

In the conventional example of FIG. 11, since the semiconductor layers 103 and 104 are formed according to the crystal growth conditions of the formula (1), so-called interface roughness that causes undesirable irregularities is formed at the interface between them. High mobility of the two-dimensional electron gas could not be ensured. That is, carrier scattering is very likely to occur at such an interface.
However, according to the crystal growth conditions (the above formula (2)) as in the third embodiment, the sublimation of atoms forming the upper surface of the semiconductor layer 103 (channel layer A) can be effectively suppressed. Therefore, roughening of the interface between the semiconductor layers 103 and 104 can be effectively prevented.

As a result, in the field effect transistor 100 of Example 3, the on-current I is from 0.7 [A / mm] to 1.1 [A / mm] as described in the characteristic column of FIG. improved, the sheet resistance ρ can be reduced from 650 [Omega / □] to 400 [Omega / □], and the mobility μ of the channel what was 1000 [cm ² / Vsec] extent, 1600 [cm ² / Vsec].

These electrical characteristics are extremely high performance equivalent to about 1 × 10 ¹³ [cm ⁻² ] in terms of the sheet carrier concentration of the channel layer (two-dimensional electron gas). . That is, according to the configuration and manufacturing method of the field effect transistor 100 of the first embodiment, the electrical characteristics of the device can be greatly improved as compared with the conventional case.

  In addition, the above-described roughening action of the interface is caused by crystal growth from a semi-insulating GaN crystal having a bulk thickness of about 400 μm and excellent in crystallinity without addition of impurities, manufactured according to the manufacturing method of Example 1 above. This is also based on the configuration of the substrate 101. That is, it is very effective and important to use a crystal growth substrate with extremely high crystal quality in forming a flat interface between semiconductor crystal layers stacked on the substrate by crystal growth treatment. The use of the semiconductor substrate for electronic devices of the present invention is particularly effective.

  FIG. 8 is a schematic cross-sectional view showing the stacked structure of the field effect transistor 200 of the fourth embodiment. The field effect transistor 200 is a semiconductor element formed by sequentially stacking group III nitride compound semiconductors by crystal growth, and the crystal growth substrate 201 is formed according to the manufacturing method of the first embodiment or the second embodiment. It is made of a semi-insulating GaN crystal having a bulk thickness of about 400 μm and excellent in crystallinity to which iron (Fe) is added as an impurity.

A semiconductor crystal layer 203 made of undoped GaN having a thickness of about 2 μm is formed on the crystal growth substrate 201. The semiconductor crystal layer 203 corresponds to the channel layer A according to claim 11. Further, on the semiconductor crystal layer 203 (channel layer A), an undoped Al _x Ga _1-x N (0.15 ≦ x) having a thickness of about 400 mm corresponding to the carrier supply layer B described in claim 11. A semiconductor crystal layer 204 of ≦ 0.20) is laminated.
The aluminum composition ratio x monotonously decreased from 0.20 to 0.15 with respect to the increase in the distance from the interface with the semiconductor crystal layer 203.

  The film thickness (about 400 mm) of the semiconductor crystal layer 204 (carrier supply layer B) is such that the two-dimensional electron gas layer generated near the interface between the semiconductor crystal layers A and B when the gate is turned on and the individual ohmic electrodes described below. The tunnel effect of carriers (electrons) between (205, 207) is set so as to surely and satisfactorily appear.

  Reference numerals 205, 206, and 207 denote a source electrode (ohmic electrode), a gate electrode (Schottky electrode), and a drain electrode (ohmic electrode), respectively. Each ohmic electrode (source electrode 205 and drain electrode 207) is formed by laminating a thin metal layer made of titanium (Ti) with a thickness of about 100 mm and depositing thereon with a thickness of about 3000 mm made of aluminum (Al). A metal layer is further laminated by vapor deposition. These ohmic electrodes are well adhered and alloyed by heat treatment at about 700 ° C. to 900 ° C. by flash annealing for less than 1 second. On the other hand, the gate electrode 206 is a Schottky electrode formed by depositing a metal layer made of nickel (Ni) of about 100% by vapor deposition and further depositing a metal layer made of gold (Au) on the metal layer by about 3000%. .

Hereinafter, a method for manufacturing the field effect transistor 200 will be described focusing on the semiconductor crystal layer 204 (carrier supply layer B).
Each of the semiconductor crystal layers (semiconductor crystal layers 203 and 204) of the field effect transistor 200 is crystal-grown by vapor phase growth by metal organic compound vapor phase epitaxy (MOVPE). The gases used here are carrier gas (H ₂ or N ₂ ), ammonia gas (NH ₃ ), trimethyl gallium (Ga (CH ₃ ) ₃ ), trimethyl aluminum (Al (CH ₃ ) ₃ ), etc. It is.

More specifically, each semiconductor crystal layer was crystal-grown based on the following crystal growth conditions.
1. Channel layer A (semiconductor crystal layer 203)
(1) Crystal growth temperature T _A : 1140 [° C.]
(2) Lamination structure: Single layer (intrinsic GaN crystal with a film thickness of about 2 μm)

2. Carrier supply layer B (semiconductor crystal layer 204)
(1) Crystal growth temperature T _B : 1000 [° C.]
(2) Lamination structure: Multi-layer (6 layers)
First layer: film thickness of about 70 mm, aluminum composition ratio x = 0.20
Second layer: film thickness of about 70 mm, aluminum composition ratio x = 0.19
Third layer: film thickness of about 60 mm, aluminum composition ratio x = 0.18
Fourth layer: film thickness of about 60 mm, aluminum composition ratio x = 0.17
Fifth layer: film thickness of about 70 mm, aluminum composition ratio x = 0.16
Sixth layer: film thickness of about 70 mm, aluminum composition ratio x = 0.15

FIG. 9 shows the characteristics of the gate leakage current of the field effect transistor 200. In FIG. 9, the graph i) at the bottom shows the characteristics of the gate leakage current of the field effect transistor 200, and the graph ii) above shows that the carrier supply layer B has a film thickness of about a single layer. It shows the characteristic of another sample S2, which is formed from a semiconductor crystal layer made of 400Å of Al _0.15 Ga _0.85 N. Graph iii) shows the characteristics of another sample S3 in which the carrier supply layer B is formed of a semiconductor crystal layer made of Al _0.20 Ga _0.80 N having a single layer thickness of about 400 mm. Of course, the other constituent elements are the same as those of the field effect transistor 200 in any of the samples S2 and S3.

From the measurement result of the leakage current, in the field effect transistor 200 described above, the carrier supply layer B is compared with the sample S2 formed from a single semiconductor crystal layer made of Al _0.15 Ga _0.85 N having a thickness of about 400 mm. It can be seen that the leakage current suppressing effect is obtained more than equivalent. Further, in the field effect transistor 200, the leakage current is smaller than that in the case of the sample S3 in which the carrier supply layer B is formed of a single semiconductor crystal layer made of Al _0.20 Ga _0.80 N having a thickness of about 400 mm. It turns out that it is suppressed very effectively with 1/100 or less.

Further, when the sheet resistance at the interface between the channel layer A and the carrier supply layer B was measured for the field effect transistor 200 and the samples S2 and S3, the following measurement results were obtained.
(Sheet resistance)
Field effect transistor 200: about 600 [Ω / □]
Sample S2: about 700 [Ω / □]
Sample S3: about 500 [Ω / □]

  From the above experimental results, in the field effect transistor 200, a high withstand voltage based on a well-suppressed leakage current value and a high electrical conductivity based on a well-suppressed sheet resistance (on resistance) have been conventionally used. It turns out that there is no very good tradeoff and that it is very reasonably balanced. In other words, it has not been easy in the past to achieve a sheet resistance of about 600 [Ω / □] in a field effect transistor in which the leakage current is suppressed to a low level as shown in graph i) of FIG.

The multi-layer structure in the carrier supply layer B is that the supply amount of aluminum supply gas (trimethylaluminum (Al (CH ₃ ) ₃ )) during the crystal growth of the six layers (first to sixth layers). Therefore, for example, when the field effect transistor 200 is manufactured in this way, it is easy to ensure productivity equal to or higher than that of the prior art.

  In addition, the leakage current suppressing action described above is the semi-insulating GaN having a bulk thickness of about 400 μm and excellent in crystallinity produced by adding iron (Fe) as an impurity according to the production method of Example 1 above. This is also based on the fact that the crystal growth substrate 201 is made of crystals. That is, in order to form the carrier supply layer B (semiconductor crystal layer 204) with high quality with low dislocations, it is very effective and important to use a crystal growth substrate with extremely high crystal quality. It is particularly effective to use the semiconductor substrate for electronic devices.

  FIG. 10A shows a schematic perspective view of the amplifier circuit 300 according to the fifth embodiment, and FIG. 10B shows a circuit diagram of the amplifier circuit 300. In this amplifier circuit 300, two field effect transistors 100 are formed side by side by sequentially stacking a group III nitride compound semiconductor on the crystal growth substrate 101 in the same manner as in the third embodiment. However, as shown in FIG. 10-A, a resistor R and a capacitor Cin are further formed on the crystal growth substrate 101, and these elements are electrically connected as shown in FIG. 10-B. Are connected together to form one amplifier.

  According to such a configuration, since the crystal quality of the crystal growth substrate 101 is very high as mentioned in the previous embodiment, the quality of each element is also improved. Therefore, for example, even by manufacturing such an integrated circuit, an amplifier (semiconductor integrated circuit) having excellent operating characteristics can be obtained based on the operation and effect of the present invention.

[Other variations]
The embodiment of the present invention is not limited to the above-described embodiment, and other modifications as exemplified below may be made. Even with such modifications and applications, the effects of the present invention can be obtained based on the functions of the present invention.

(Modification 1)
For example, in Example 3 (FIG. 6), the channel layer A (103) is stacked by crystal growth on the electronic device semiconductor substrate (101) of the present invention. When the semiconductor substrate for use is used, since the crystal quality of the substrate is particularly excellent, the crystal growth substrate (101) itself can also serve as the channel layer A. In that case, the carrier supply layer B (104) may be directly laminated on the electronic device semiconductor substrate (101) of the present invention after sufficiently cleaning the crystal growth surface.
In this case, the manufacturing process of a desired electronic device can be simplified, which is advantageous in terms of productivity.

(Modification 2)
Also, in the above-described Example 3 and Example 4, the configuration example of the FET of the type in which current flows in the lateral direction (horizontal direction) on the semi-insulating semiconductor substrate for electronic devices of the present invention has been shown. The present invention provides an electrode on at least a part of the back surface of a conductive crystal growth substrate (conductive semiconductor substrate for electronic devices), and a vertical direction (vertical direction) on the crystal growth substrate or a semiconductor crystal layer stacked thereon. It can also be applied to a type of FET that causes a current to flow through. Examples of such vertical conduction type electronic devices include field effect transistors described in “JP 2004-260140”, “JP 2000-349284”, “JP 10-294461”, and the like.

  Even in the case where the semiconductor substrate for a conductive electronic device of the present invention is adopted as the substrate of the field effect transistor having the conventional structure, the leakage current and the sheet resistance are reduced as in the above embodiment. Various characteristics of the electronic device can be effectively improved by the effect. In addition, in these electronic devices, it is possible to obtain the action as seen in each of the above embodiments. In particular, in the field effect transistor having the conventional structure described above, a crystal growth substrate (semiconductor for electronic devices) is also provided. Since an electrode is formed on the substrate) itself and a current is passed through the substrate itself, the effect of improving the crystal quality of the conductive substrate based on the use of the semiconductor substrate for electronic devices of the present invention is further expanded.

For example, if the semiconductor substrates for conductive electronic devices of the present invention are used, these substrates have higher electrical conductivity than conventional substrates, and therefore, on-resistance of 1 mΩcm ² or less is known in known power FETs having a conventional structure. It is sufficiently possible or easy to realize. Moreover, since these substrates have higher thermal conductivity than conventional substrates, they are effective in reducing on-resistance and obtaining a heat dissipation effect.

  Note that when forming a desired electronic device, the method of adding impurities to the semiconductor crystal layer stacked on the crystal growth substrate (electronic device semiconductor substrate) does not necessarily depend on the crystal growth treatment. For example, impurities can be added to these semiconductor crystal layers also by methods such as ion implantation and thermal diffusion.

The present invention is useful for manufacturing a semiconductor device using a semiconductor crystal made of a group III nitride compound semiconductor. As these semiconductor devices, in addition to the electronic devices mentioned above, for example, light emitting elements and light receiving elements such as LEDs and LDs, and optical integrated circuits (OEIC) in which they are integrated can be cited.
Further, the transistor of the present invention may use a field effect or may be a bipolar type. The field effect transistors that can be manufactured according to the present invention include semiconductor elements such as MISFET, MOSFET, HFET, MODFET, JFET, HJFET, and HEMT, and further include, for example, power MOSFET and IGBT. A power transistor for power control is also included.

Sectional view of the crystal growth apparatus used in Example 1 Sectional drawing which illustrates operation | movement of the crystal growth apparatus used in Example 1. FIG. Sectional drawing which illustrates operation | movement of the crystal growth apparatus used in Example 1. FIG. Sectional drawing which illustrates operation | movement of the crystal growth apparatus used in Example 1. FIG. Sectional drawing in the creation process of the template 10 of Example 2. Configuration diagram of crystal growth apparatus used in Example 2 Partial sectional view of the crystal growth apparatus used in Example 2 Sectional drawing in the crystal growth process of the semiconductor crystal of Example 2. Sectional drawing in the crystal growth process of the semiconductor crystal of Example 2. Sectional drawing in the crystal growth process of the semiconductor crystal of Example 2. Sectional drawing which shows the laminated structure of the field effect transistor 100 of Example 3 Table showing configuration conditions and characteristics of field effect transistor 100 Sectional drawing of the field effect transistor 200 of Example 4 The graph which shows the characteristic of the leakage current of the field effect transistor 200 Schematic perspective view of the amplifier circuit 300 of the fifth embodiment. Circuit diagram of amplifier circuit 300 of Embodiment 5 Sectional drawing which illustrates the laminated structure of the conventional field effect transistor 900

Explanation of symbols

2: Reaction chamber
3: Reaction vessel
8: Seed crystal
9: Mixed flux
H: Heater
10: Template
20: Semiconductor substrate 100, 200: Field effect transistor 103, 203: Channel layer 104, 204: Carrier supply layer

Claims (15)

Among mixed fluxes having a plurality of types of metal elements selected from alkali metals or alkaline earth metals, group III elements of gallium (Ga), aluminum (Al) or indium (In) and nitrogen (N) In the method for producing a semiconductor substrate for an electronic device in which a group III nitride compound semiconductor crystal is crystal-grown by reacting
A method for producing a semiconductor substrate for an electronic device, comprising growing the group III nitride compound semiconductor crystal while stirring and mixing the mixed flux and the group III element. Among mixed fluxes having a plurality of types of metal elements selected from alkali metals or alkaline earth metals, group III elements of gallium (Ga), aluminum (Al) or indium (In) and nitrogen (N) In the method for producing a semiconductor substrate for an electronic device in which a group III nitride compound semiconductor crystal is crystal-grown by reacting
A soluble material that dissolves in the mixed flux is used for at least a part of the base substrate for crystal growth of the group III nitride compound semiconductor crystal,
The soluble material is added during the crystal growth process of the group III nitride compound semiconductor crystal, or
In the vicinity of the growth temperature after the crystal growth process of the group III nitride compound semiconductor crystal,
A method for producing a semiconductor substrate for an electronic device, comprising dissolving in the mixed flux. The soluble material is at least partly,
The method for producing a semiconductor substrate for an electronic device according to claim 2, further comprising an impurity to be added to the group III nitride compound semiconductor crystal. The method for producing a semiconductor substrate for an electronic device according to claim 2 or 3, wherein the group III nitride compound semiconductor crystal is grown while stirring and mixing the mixed flux and the group III element. . The mixed flux is
It has lithium (Li) or calcium (Ca), and sodium (Na), The manufacturing method of the semiconductor substrate for electronic devices of any one of Claim 1 thru | or 4 characterized by the above-mentioned. Seed crystal or crystal growth surface of the base substrate,
Before crystal growth of the group III nitride compound semiconductor crystal,
Hydrogen (H ₂ ) gas, nitrogen (N ₂ ) gas, ammonia (NH ₃ ) gas, rare gas (He, Ne, Ar, Kr, Xe, or Rn) or two or more kinds of these gases A mixed gas mixed at an arbitrary mixing ratio is used as a cleaning gas.
At a temperature of 900 ° C. or higher and 1100 ° C. or lower,
Take a minute or more
The method for manufacturing a semiconductor substrate for an electronic device according to claim 1, wherein a cleaning process is performed. The mixed flux is
As an impurity to be added to the group III nitride compound semiconductor crystal,
Boron (B), thallium (Tl), calcium (Ca), compounds containing calcium (Ca), silicon (Si), sulfur (S), selenium (Se), tellurium (Te), carbon (C), oxygen ( O), aluminum (Al), indium (In), alumina (Al ₂ O ₃ ), indium nitride (InN), silicon nitride (Si ₃ N ₄ ), silicon oxide (SiO ₂ ), indium oxide (In ₂ O ₃₎ ), Zinc (Zn), iron (Fe), magnesium (Mg), zinc oxide (ZnO), magnesium oxide (MgO), or germanium (Ge). A manufacturing method of a semiconductor substrate for electronic devices given in any 1 paragraph. A semiconductor substrate for electronic devices manufactured by the method for manufacturing a semiconductor substrate for electronic devices according to any one of claims 1 to 7,
A semiconductor substrate for electronic devices, wherein the dislocation density on the surface is 1 × 10 ⁵ cm ⁻² or less and the maximum diameter is 1 cm or more. The semiconductor substrate for electronic devices according to claim 8, wherein the thickness is 300 μm or more. In an electronic device configured by laminating a semiconductor crystal layer made of a group III nitride compound semiconductor on a crystal growth substrate,
The crystal growth substrate is
An electronic device comprising the semiconductor substrate for an electronic device according to claim 8 or 9. In a field effect transistor formed by crystal growth of a semiconductor crystal layer made of a group III nitride compound semiconductor,
A semiconductor substrate for electronic devices according to claim 8 or 9, and
A channel layer A crystal-grown directly or indirectly on the semiconductor substrate for electronic devices;
A carrier supply layer B crystal-grown directly on the channel layer A;
At least in the vicinity of the interface between the channel layer A and the carrier supply layer B,
The band gap energy E _B of the carrier supply layer _B is
Field effect transistor being greater than the band gap energy E _A of the channel layer A. At least one of the channel layer A and the carrier supply layer B is
12. The field effect transistor according to claim 11, wherein the field effect transistor is formed of an additive-free semiconductor crystal. The channel layer A includes
Consisting of binary or ternary Al _x Ga _1-x N (0 ≦ x <1),
The carrier supply layer B is
13. The field effect transistor according to claim 11, wherein the field effect transistor is made of ternary Al _y Ga _1-y N (x <y ≦ 1). The interface is
14. The device according to claim 11, wherein the channel layer A is formed to be substantially flat by suppressing sublimation action of atoms of the channel layer A forming the vicinity of the interface. Field effect transistor. The carrier supply layer B is
Made of Al _y Ga _1-y N (0.45>y> 0.04),
The aluminum composition ratio y of the carrier supply layer B is:
15. The field effect transistor according to claim 11, wherein the field effect transistor decreases substantially monotonously with respect to the distance from the interface.

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