JP2007288028A - Signal delay structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal delay structure by which an accurate and stable signal delay amount can be obtained and the integration degree can be improved by reducing the area of a capacitance part. <P>SOLUTION: A delay circuit element 2 has the capacitance part 6 having a dielectric film 9 between an upper electrode 8 and a lower electrode 12 and a signal line 3 which is connected with either one of the upper electrode 8 and the lower electrode 12 through several contacts 13B and 13C. It is so constructed that the upper electrode 8 functions as a resistor part 5 between the several contacts 13B and 13C. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a signal delay structure suitable for adjusting the timing of a signal in a semiconductor integrated circuit, for example.

  Conventionally, in a semiconductor integrated circuit, a signal delay circuit may be required to synchronize the timing of a signal such as a digital circuit or a limiter amplifier circuit.

  In order to delay the signal, for example, there are one using a gate delay and one using a capacitance. Among them, it is common to use a capacitor mainly to realize a large signal delay.

  FIG. 6 shows a structure of a signal delay circuit element using a capacitor (see Patent Document 1 described later).

  In this element structure, as shown in the equivalent circuit of FIG. 6A, a signal input from the IN (input side) to the signal line 53 is a delay circuit element (CR that is composed of an ON resistance 54 and a capacitor 56 of the transistor Tr. The composite element) 52 is configured to output to the OUT (output) side as a signal having a delay amount proportional to the resistance (R) × capacitance (C) = time constant.

  The signal delay circuit element (CR composite element) 52 shown in FIG. 6B is located on the gate electrode 84 having a predetermined gate width and the semiconductor substrate 78, and is provided in the vicinity of both ends of the gate electrode 84 in the width direction. A source 79 and a drain 80 as diffusion regions, an input side electrode 82 and an output side electrode 83 electrically connected to the source 79 and the drain 80, respectively, and a gate formed between the semiconductor substrate 78 and the gate electrode 84. The channel 81 is formed between the source 79 and the drain 80 by applying a voltage to the gate electrode 84.

  In this structure, when a voltage is applied to the gate electrode 84, it is formed between the resistance 54 of the channel 81 formed below the gate electrode 84 corresponding to the magnitude of the gate voltage, and between the gate electrode 84 and the channel 81. The capacitor 56 is formed in a distributed constant. As a result, a delay element that generates a signal delay amount proportional to resistance (R) × capacitance (C) is formed.

  FIG. 7 shows another delay circuit element using a capacitor (see Patent Document 2 described later).

  In this conventional example, the resistance of the diffusion layer 94 formed in the epitaxial layer 90 of the semiconductor substrate 98 is used, and the capacitance of the depletion layer generated by reverse biasing the PN junction between both layers 94-90 is used. That is, by controlling the reverse bias voltage of the PN junction of the resistance element by changing the voltage of the power source connected to the epitaxial layer 90 via the diffusion layer 93 and the electrode 92, the depletion layer capacitance is controlled, together with the above diffusion resistance. A delay circuit can be configured to adjust the delay time of the input / output signal.

  8 and 9 show still another delay circuit element. Here, as shown in FIG. 8A, a signal input from IN to a signal line 53 is input to a delay circuit element (CR composite element) 52 including a buffer 60A and a capacitor 56, and a buffer (for waveform shaping) 60B. A signal that sequentially passes and is delayed by the delay circuit element 52 is output to OUT.

  FIG. 8B shows an equivalent circuit of this delay circuit element. A signal inputted from IN to the signal line 53 is a delay circuit element (CR composed of an ON-resistance 54A of the transistor Tr of the buffer 60A and a capacitor 56. A signal delayed by the composite element 52 is output. The capacitor 56 is a so-called MIM (Metal-Insulator-) composed of one electrode connected to the signal line 53 between the two buffers 60A and 60B, the other electrode grounded, and a dielectric film between the two electrodes. Metal) structure.

  FIG. 8C shows a timing chart of signal delay. A rectangular wave signal of part a input from IN to the signal line 53 blunts the rising waveform and the falling waveform due to the ON resistance and the capacitor 56 of the buffer 60A. The timing 86 for crossing the logic threshold level in the portion b is shifted backward (slower) in time. The waveform that has become dull due to the rising and falling waveforms being shifted in this way is shaped by the subsequent buffer 60B (for waveform shaping), and is output at the c portion as a rectangular waveform signal having the same rising waveform and falling waveform as the a portion. Is output. Comparing the waveforms of the rectangular waves a and c, the signal is delayed by the amount (delay amount) 87 that the timing of crossing the logical threshold is shifted backward.

  As described above, the delay circuit element 52 using the capacitor 56 uses the time constant τ (= C × R), and the resistance is the ON resistance 54A of the Tr constituting the buffer 60A. That is, when the node 80 is charged, the on-resistance of the p-channel Tr that forms the buffer 60A is related to the time constant τ, and when the node 80 is discharged, the on-resistance of the n-channel Tr is related to the time constant τ. It will be. The capacitance C is obtained by dividing the product of the dielectric constant ε of the dielectric film and the area S of the counter electrode by the film thickness d of the dielectric film (C = εS / d). Becomes a constant value and does not change depending on the potential (V) of the electrode, that is, the magnitude of the signal voltage.

  FIG. 9 shows a substantially square MIM structure capacitor portion 56 in which a lower electrode 62, a dielectric film 59, and an upper electrode 58 are stacked in order to form this capacitor. The upper electrode 58 is connected to the signal line 53 via a contact 63A in the through hole of the interlayer insulating film 57, and this connection point becomes an upper node, while the lower electrode 62 is connected via the contact 61B and the ground line 61. Grounded. The signal line 53 has a width of, for example, 0.1 μm, and the capacitor 6 functions as a capacitor only when a signal is input to the signal line 53.

JP-A-7-226657 (page 7, right column, line 6 to page 8, left column, line 17; FIG. 4) JP-A-2-119411 (Page 2, upper left column, line 16 to lower left column, line 6; FIGS. 5 to 7)

  In the delay circuit element 52 of Patent Document 1 shown in FIG. 6, a channel formed in accordance with a voltage applied to the gate electrode 84 is used, and a channel resistance (R) and a gate-channel capacitance (C). And signal delay is realized. However, since the channel state (especially the depth) is likely to change due to the change in the gate voltage, the time constant, that is, the signal delay amount changes due to the change in the channel resistance. As a result, a stable signal delay amount can be obtained with high accuracy. Is difficult.

  In the delay circuit element of Patent Document 2 shown in FIG. 7, although the resistance is constant as a diffused resistor, the capacitance component uses the depletion layer capacitance due to the reverse bias voltage. It is easy to change, the time constant changes, and the signal delay amount cannot be obtained with high accuracy.

  Such a problem does not occur at least in the capacitance in the delay circuit element 52 shown in FIG. That is, since the capacitor portion 56 has an MIM structure including the upper electrode 58, the dielectric film 59, and the lower electrode 62, the capacitance value is always kept constant for the above-described reason (however, the resistance component is ON of the Tr). It is a resistor, but this can be made almost constant by the transistor design).

However, for example, the time constant τ of 680 psec is set to 1.7 kΩ (0.7 mA, 1.2 V) Tr on-resistance 54A, and the upper electrode 58 has a sheet resistance of 23 Ω / μm ² and 1 M F (μm ² ) MIM ( If an attempt is made to use a metal-insulator-metal capacitor, the area of the capacitor portion is 680 / 1.7 = 400 (μm ² ), and a region corresponding to a square having a side of 20 μm is required. This is because, as Tr is increasingly integrated in a semiconductor integrated circuit, the size of such a capacitor portion is a level that cannot be ignored, which hinders the improvement of the integration degree.

  The present invention has been made in view of such a situation, and an object of the present invention is to obtain a stable signal delay amount with high accuracy and to reduce the area of the capacitor portion to improve the degree of integration (further, It is an object to provide a signal delay structure capable of reducing a change in resistance.

  That is, the present invention includes a capacitor having a dielectric film between a pair of electrodes, and a signal line connected to one of the pair of electrodes via a plurality of contacts, and the plurality of contacts In the meantime, the one electrode is related to a signal delay structure configured to function as a resistance portion.

  According to the present invention, since the capacitor portion has a structure having a dielectric film between a pair of electrodes, the capacitance value C is C = εS / d (ε is the dielectric constant of the dielectric film, and d is the film thickness thereof. , S can be set to a constant value that is uniquely defined by the area of the counter electrode or the dielectric film), and thus a stable capacitance value that is hardly affected by fluctuations in applied voltage or the like can be obtained.

  In addition, since the one electrode functions as a resistance portion between the plurality of contacts, the resistance value can also be set to a constant value depending on the design of the electrode. Therefore, it is possible to always obtain the time constant, that is, the signal delay amount, together with the above-described constant capacitance value with high accuracy and stability. In addition, the resistance portion and the capacitance portion can be accommodated within the area occupied by the capacitance portion, and the signal delay structure can be formed with a small area to improve the degree of integration.

  In the present invention, the other electrode of the pair of electrodes facing the signal line is grounded to obtain a predetermined capacitance value, or forms a part of another signal line parallel to the signal line. Is desirable.

  In this case, the plurality of contacts are provided at three or more locations, and at least the resistance portions between the first and second contacts and between the second and third contacts are connected in series. Is desirable. According to this structure, output signals having different delay amounts can be obtained from at least the second and third contacts.

  Further, it is desirable that the pair of electrodes is made of a metal, a conductive polymer semiconductor material, or an alloy thereof.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

First Embodiment FIG. 1 shows a first embodiment of the present invention.

  A signal delay circuit element (CR composite element) 2 according to the present embodiment as shown in the plan view of FIG. 1A to the AA ′ line cross-sectional view and the BB ′ line cross-sectional view of FIG. Is composed of a capacitor 6 composed of a lower electrode 12, a dielectric film 9 and an upper electrode 8 (resistor 5), and an upper electrode 8 also serving as the resistor 5. The upper electrode 8 is a part of the signal line, and the IN (input side) of the buffer 10A is provided via one contact 13B and the other contact 13C provided in each through hole formed in the interlayer insulating film 7. The signal line 3 is electrically connected to the OUT (output side) signal line 3 having the buffer 10B, and the lower electrode 12 is grounded via the contact 13A and the ground line 11 similar to the above. .

  For example, when the capacitor 6 including the resistor 5 (upper electrode 8) is formed in an elongated pattern (in this example, the width of the upper electrode 8 is 1 μm and the length between the contacts 13B-13C is fixed to 140 μm), it is constant. From the distance between the contacts 13B-13C provided by a distance and the area of the upper electrode 8 (resistor part 5), the resistance value of the resistor part 5 and the capacitance value of the capacitor part 6 between IN and OUT Is uniquely and stable.

That is, when the length of the upper electrode 8 is obtained so as to have the same time constant (680 psec) as the delay circuit element 52 of the conventional example shown in FIG. 9, the on-resistance 4A of the transistor Tr of the buffer 10A is 1.7 kΩ, If the resistance of the resistance portion 5 (sheet resistance 23Ω / μm ² ) (upper electrode 8) is 3.22 kΩ, the total resistance is 4.92 kΩ. Therefore, in order to obtain the target time constant (680 psec), the capacitance value is 680 / 4.92 = 1388.2138 = about 140 (fF). In order to obtain this capacitance value, since 1 fF per 1 μm ² , the length of the upper electrode 8 may be about 140/1 = about 140 (μm).

Thus, the area of the upper electrode 8 (about 140 μm ² ) is about 35% of that of FIG. 9 (400 μm ² ), and the area of the upper electrode 8 can be reduced by about 65%. it can.

  Here, it is desirable that the capacity unit 6 be a MIM (Metal-Insulator-Metal) capacity or a PIP (Poly-Insulator-Poly) capacity.

The material of the upper electrode 8 and the lower electrode 12 is made of at least one metal selected from the group consisting of TiN, Ta, TiTa, etc., or a laminate thereof, or doped polySi doped with p-type or n-type impurities. It is desirable to be made of one kind of conductive polymer semiconductor material selected from the group consisting of polycide such as tungsten silicide, or an alloy thereof. The dielectric film 9 is preferably made of at least one selected from the group consisting of SiO ₂ , SiON, SiN, H _f O ₂ , H _f SiON, Al ₂ O _{3 and the} like, or a laminate thereof.

  In order to obtain a predetermined capacitance value, it is desirable that the dielectric constant of the dielectric film 9 is 3.9 to several tens and the film thickness is several tens of nm. Further, in order to obtain a predetermined resistance value, the upper electrode 8 It is desirable that the film thickness, width, and length of each are several tens of nm, several tens of μm or less, and several hundreds of μm or less.

  As shown in an equivalent circuit diagram of the delay circuit element 2 in FIG. 1C and a more detailed equivalent circuit diagram of the capacitor section 6, the delay circuit element (CR composite element) 2 is formed of the Tr forming the buffer 10A. It has a resistance component due to the on-resistance 4A and the resistance portion 5 (upper electrode 8) and a capacitance component due to the upper electrode 8-dielectric film 9-lower electrode 12. The capacitance unit 6 is equivalent to a distributed constant circuit in which a plurality of resistors 5a, 5b, 5c... Shown in the figure and capacitors 6a, 6b, 6c.

  The timing chart and waveform of signal delay by the delay circuit element 2 are basically the same as those shown in FIG.

  According to the present embodiment, as described above, since the capacitor portion 6 has the dielectric film 9 between the upper electrode 8 and the lower electrode 12, it is difficult to be affected by fluctuations in the applied voltage. A stable capacitance value can be obtained.

  Further, since the upper electrode 8 is configured to function as the resistance portion 5 between the contacts 13B and 13C, this resistance value can also be set to a constant value depending on the design of the electrode. Therefore, it is possible to always obtain the time constant, that is, the signal delay amount, together with the above-described constant capacitance value with high accuracy and stability. In addition, the resistance portion 5 and the capacitance portion 6 can be accommodated within the area occupied by the capacitance portion 6, and the signal delay circuit element 2 can be formed with a small area, thereby improving the degree of integration.

  In addition, in the case where the same time constant τ (680 pec) as in the conventional example is to be realized by the present embodiment, the total resistance value is increased by adding the resistance value of the resistance unit 5 in addition to the on-resistance 4A of Tr. The capacitance value can be decreased in inverse proportion to the increase in the total resistance value. Accordingly, in realizing the equivalent time constant, the upper electrode 8 can be formed with a much smaller area than before (the area can be reduced by 65%), so that the degree of integration of elements including the signal delay element 2 is increased. be able to.

Second Embodiment FIGS. 2 to 3 show a second embodiment of the present invention.

  In the present embodiment, as shown in FIGS. 3 to 4, the upper electrode 8 and the lower electrode 12 are respectively provided as signal lines, and signal lines 23 </ b> A and 23 </ b> B having IN (input side) and OUT (output side), respectively. Except for being connected, the second embodiment is the same as the first embodiment described above.

  As shown in the plan view of FIG. 2A to the AA ′ line cross-sectional view and the BB ′ line cross-sectional view of FIG. 2B, the delay circuit element (CR composite element) 2 according to the present embodiment is , A lower electrode 12, a dielectric film 9, and an upper electrode 8. The upper electrode 8 (resistive part 5 B) includes contacts 13 B formed on the interlayer insulating film 7 on the upper electrode 8 and The contacts 13C are electrically connected to the IN2 (input side) signal line 23B and the OUT2 (output side) signal line 23B, respectively, and the lower electrode 12 (resistor portion 5A) also connects the contact 13A and the contact 13D. And the signal line 23A on the IN1 (input side) and the signal line 23A on the OUT1 (output side), respectively.

  Therefore, both the upper electrode 8 and the lower electrode 12 are not only part of the signal lines provided in parallel adjacent to each other, but also function as a resistance component of the capacitor portion. Therefore, the delay circuit according to the present embodiment. The element 2 is represented by an equivalent circuit shown in FIG.

  A semiconductor device 16 disclosed in Japanese Patent Laid-Open No. 2000-269793 to which this embodiment can be applied will be described with reference to FIG.

This known semiconductor device 16 includes a select signal φ _S , a reverse signal φ _R , a delay circuit 21, signal lines 23A and 23B, a floating capacitor Cs, semiconductor switches 26A and 26B, inverters 24A, 24B and 24C, and NAND elements 25A and 25B. And 25C, and buffers 20A and 20B.

The select signal φ _S is responsible for switching on and off the circuit group, and is in the “H” state when adjusting the signal delay amount. The reverse signal φ _R is in the “H” state when the signal delay amount is increased, and is in the “L” state when the signal delay amount is decreased. When the select signal φ _S is in the “H” state and the reverse signal φ _R is in the “H” state, the signal output from the delay circuit 21 is the inverters 24A, 24B and 24C, and Are inverted by the NAND elements 25A, 25B and 25C and output to the buffer 20B.

As a result, the signals applied to the signal line 23A and the signal line 23B, which are dummy signal lines, have a reversed phase relationship, so that the stray capacitance Cs between them is doubled by the mirror effect, Increases the amount of delay. When the reverse signal φ _R is in the “L” state, a signal having the same phase is applied from the buffer 20B, and as a result, the stray capacitance Cs does not easily exist equivalently, so that the delay amount is reduced.

  That is, in the D part of FIG. 3, its own in-phase waveform or inverted waveform is generated by the gate circuit, and this is run on the signal line 23A adjacent to and parallel to the signal line 23B. In this case, a small delay (signal delay) can be realized by regarding the inter-wiring stray capacitance Cs between the signal lines 23A and 23B as almost zero. Further, when the inversion waveform is run, the inter-wiring stray capacitance Cs between the signal lines 23A and 23B works as a double capacitance as a mirror capacitance, so that a large delay (signal delay) can be generated. In this way, the signal delay can be adjusted in the circuit of the D section.

  However, in this structure, since the inter-wiring stray capacitance Cs between the signal lines 23A and 23B is used, even if it is desired to generate a necessary and sufficient capacitance for signal delay, the distance between the signal lines that run adjacent to each other is desired. This is effective only when it is long to some extent, for example, in the case of a bus line.

  Therefore, in the present embodiment, the upper and lower electrodes 8 and 12 of the capacitor unit 6 are used in the D unit by using the capacitor unit 6 having the four-terminal pattern having the structure shown in FIG. 2 instead of the inter-wiring stray capacitance Cs. Can be provided as the resistance portions 5B and 5A, respectively, and resistance values and capacitance values necessary and sufficient for signal delay can be obtained. As a result, even if the parallel electrodes 8 and 12 are part of the signal line and the distance is much shorter than that of the conventional one, an equivalent signal delay amount can be obtained, so that not only the bus line but also the shorter signal line 23A and 23B can also be applied. In addition, since the capacity unit 6 is the above-described MIM or PIP capacity, the signal delay amount can be obtained accurately and reliably.

  In addition, in the present embodiment, the same operations and effects as described in the first embodiment described above can be obtained.

Third Embodiment FIG. 4 shows a third embodiment of the present invention.

  In the present embodiment, as shown in FIG. 4A, three types of delayed signals are formed from input signals via directly connected delay circuit elements 2A, 2B, and 2C, and the selector 15 selects desired signals. This is basically the same as the first embodiment described above, except that a signal having a delay amount of 2 is selected and output.

  That is, as shown in FIG. 4A, a plurality (three in this case) of delay circuit elements 2 shown in FIG. 1 are connected in series. Actually, the contacts including the ground-side contact 13A are connected. Nine are provided, and the lower electrode 12 is shared by each element. The contact 13A is not limited to being used as the ground side, and the lower electrode may also be used as a signal line as in the second embodiment described above.

  According to this structure, a part of the signal input from the IN (input side) to the signal line 3 sequentially passes through the buffer 10A, the delay circuit element 2A and the buffer 10D, and is delayed by a predetermined amount (output signal). ) Is input to the selector 15. The delay circuit element 2A is sequentially passed through the subsequent buffer 10B, delay circuit element 2B, and buffer 10E, and input to the selector 15 as a second delay signal (output signal) having a larger delay amount. Further, the delay circuit element 2B sequentially passes through the subsequent buffer 10C, the delay circuit element 2C, and the buffer 10F, and is input to the selector 15 as a third delay signal (output signal) having a larger delay amount.

  The first, second, and third delay signals input to the selector 15 have different delay amounts, and a desired delay signal can be selectively output to OUT via the selector 15.

  As clearly shown in FIG. 4B, the upper electrode 8A (resistor 5A) between the contact 13B and the contact 13C, the upper electrode 8B (resistor 5B) between the contact 13C and the contact 13D, and the contact Since the upper electrode 8C (resistor portion 5C) between 13D and the contact 13E is connected in series, the delay amounts of the first, second, and third delay signals described above are the capacitance portions 6A, 6B, It is determined by the length of the upper electrode between the contacts when passing through 6C.

  That is, after a signal is input to the capacitor 6A via the buffer 10A and the contact 13B, the first delayed signal is output to the buffer 10D side via the contact 13C. Then, the second delay signal is output to the buffer 10E via the contact 13D with a larger delay amount while maintaining the delay amount of the first delay signal. Further, the third delay signal is output to the buffer 10F via the contact 13E with a larger delay amount while maintaining the delay amount of the second delay signal.

  Compared to this, the structure shown in FIG. 5 has three delay circuit elements of the conventional structure shown in FIG. 9, and each upper electrode 58 of each of the capacitors 56A, 56B and 56C is connected to each contact 63A. , 63B and 63C, respectively, are connected to the signal line 3. Each lower electrode 62 is grounded via each contact 61B.

  That is, a part of the signal input from the IN (input side) to the signal line 53 is input to the selector 88 as a first delay signal that sequentially passes through the buffer 60A, the delay circuit element 52A, and the buffer 60D and is delayed by a predetermined amount. . The delay circuit element 52A is sequentially passed through the subsequent buffer 60B, delay circuit element 52B, and buffer 60E, and is input to the selector 88 as a second delay signal having a larger delay amount. Further, the delay circuit element 52B sequentially passes through the subsequent buffer 60C, the delay circuit element 52C, and the buffer 60F, and is input to the selector 88 as a third delayed signal that is further delayed. Therefore, as in the example of FIG. 4, the first, second, and third delay signals input to the selector 88 can be selectively output to OUT, and the range of selection when outputting signals with different signal delay amounts is increased. Can be spread.

However, according to the configuration of FIG. 5, as described in FIG. 9, a large area capacitors portion 56A of the (400 [mu] m ^2), 3 pieces of 56B and 56C (total area 1200 [mu] m ²⁾ not have to use. In contrast, according to this embodiment, by using capacitance section 6A of smaller area than the conventional example (140 .mu.m ^2), 6B, and 6C, 3 pieces of delay circuit element 2 shown in FIG. 1 (the total area 420 [mu] m ² It is only necessary to arrange them, and the same operations and effects as described in the first embodiment described above can be obtained.

  As mentioned above, although this invention was demonstrated based on embodiment, it cannot be overemphasized that this invention is not limited to these examples at all, and can be suitably changed in the range which does not deviate from the main point of invention.

  For example, instead of using the above-mentioned Tr on-resistance 4A, it is possible to use a resistor having any other structure as long as it is a resistor, or it is possible to use only the resistance of the upper electrode of the capacitor without using such a resistor. There is no problem. In addition, the shape, pattern, and size of the capacitor element described above can be variously changed. The functions of the upper and lower electrodes described above may be reversed from those described above. In addition, the shape, pattern, and size of the capacitor element described above can be variously changed.

  The delay circuit element 2 and the like described above may be structured to be incorporated in the circuit simultaneously with other elements in a semiconductor process, but may be incorporated as separately manufactured individual parts.

  The signal delay structure of the present invention can be applied to various semiconductor integrated circuits that handle digital signals.

The top view (A) of the delay circuit element by the 1st Embodiment of this invention, its AA 'sectional view, BB' sectional view (B), equivalent circuit schematic (C), and (C ') ). FIG. 4A is a plan view of a delay circuit element according to a second embodiment of the present invention, and a cross-sectional view taken along line A-A ′, a cross-sectional view taken along line B-B ′, and an equivalent circuit diagram (C). 2 is a block diagram of a signal circuit incorporating a delay circuit element. FIG. FIG. 6 is a configuration diagram (A) and a plan view (B) of a delay circuit element according to a third embodiment of the present invention. FIG. 3 is a configuration diagram of a comparative delay circuit element. FIG. 6 is an equivalent circuit diagram (A) and a cross-sectional view (B) of a delay circuit element according to Conventional Example 1. 10 is a cross-sectional view of a delay circuit element according to Conventional Example 2. FIG. FIG. 7 is a configuration diagram (A) of a signal circuit according to Conventional Example 3, an equivalent circuit diagram (B) of a delay circuit element, and a timing chart (C) of signal delay. FIG. 2B is a plan view of the delay circuit element (A) and a sectional view taken along line A-A ′ of FIG.

Explanation of symbols

2, 2A, 2B, 2C ... delay circuit elements, 3, 23A, 23B ... signal lines,
4A: Tr on-resistance, 5, 5A, 5B, 5C ... resistance section,
6, 6A, 6B, 6C ... capacitor part, 7 ... interlayer insulating film, 8, 8A, 8B, 8C ... upper electrode,
9: Dielectric film,
10A, 10B, 10C, 10D, 10E, 10F, 20A, 20B ... buffer,
11 ... ground wire, 12 ... lower electrode,
13A, 13B, 13C, 13D, 13E ... contact, 15 ... selector

Claims (6)

  A capacitor having a dielectric film between a pair of electrodes; and a signal line connected to one of the pair of electrodes via a plurality of contacts, and the one electrode between the plurality of contacts. Is a signal delay structure configured to function as a resistor.   The signal delay structure according to claim 1, wherein the other electrode of the pair of electrodes is grounded.   The signal delay structure according to claim 1, wherein the other electrode of the pair of electrodes forms a part of another signal line parallel to the signal line.   The plurality of contacts are provided at three or more locations, and at least each of the resistance portions between the first and second contacts and between the second and third contacts are connected in series. 3. The signal delay structure described in 3.   5. The signal delay structure according to claim 4, wherein output signals having different delay amounts are obtained from at least the second and third contacts.   The signal delay structure according to claim 1, wherein the pair of electrodes is made of a metal, a conductive polymer semiconductor material, or an alloy thereof.

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