JP2007287822A - Method of manufacturing dielectric deposition, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a dielectric deposition which can form a dielectric layer having a good crystallinity and thereby can obtain a high reliability and prevents the delamination of a bottom electrode, and to provide an electronic apparatus including a dielectric deposition manufactured by this manufacturing method. <P>SOLUTION: The method of manufacturing the dielectric deposition 10 comprises processes of: forming a lower electrode 4 on a substrate; forming the dielectric layer 5 formed of a ferroelectric material or a piezoelectric material on the lower electrode 4; and forming a top electrode 6 on the dielectric layer 5. The process of forming the lower electrode 4 includes a process of forming a first metal layer by an ion beam sputtering method or a DC sputtering method, and a process of depositing a second metal layer on the first metal layer by an electrolytic plating method. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a dielectric deposit body such as a ferroelectric capacitor element and a piezoelectric element, and an electronic apparatus.

  A ferroelectric memory provided with a ferroelectric capacitor (ferroelectric capacitor) is non-volatile, has an operating speed equivalent to that of a DRAM, and any other memory currently being commercialized or studied. It is expected to be one of the next generation memory because it has lower power consumption.

In order to improve the characteristics of such a ferroelectric memory, the crystallinity of a dielectric layer made of a ferroelectric, which constitutes a ferroelectric capacitor, is important. The crystallinity of the dielectric layer is greatly influenced by the crystallinity of the lower electrode below it. Therefore, in order to improve the crystallinity of the dielectric layer, it is very important to improve the crystallinity of the lower electrode which is the base. In order to form a lower electrode with good crystallinity, the formation method (film formation method) is important. As a method for forming the lower electrode (film formation method), a technique using a sputtering method is known (see, for example, Patent Document 1).
JP 2001-244426 A

  Incidentally, noble metals such as platinum and iridium, which are generally difficult to oxidize, are used as electrodes used in ferroelectric capacitors because they are required to withstand a high temperature annealing process in an oxidizing atmosphere. However, the above-described sputtering method is still insufficient for forming such an electrode composed mainly of a noble metal with better crystallinity and good orientation, and with low damage and low stress. Therefore, further improvement is desired.

Also, for example, in an ink jet recording head for an ink jet printer, a piezoelectric element is used as an actuator. For improving the characteristics of such an actuator, a crystal of a lower electrode serving as a base of a dielectric layer made of a piezoelectric material is used. Sex is important.
Conventionally, the lower electrode causes film peeling with respect to the substrate. As a result, a dielectric element (dielectric deposit) such as a ferroelectric capacitor or a piezoelectric element, a ferroelectric memory including the same, The reliability of electronic devices such as actuators may be reduced.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to form a good crystalline dielectric layer, thereby obtaining high reliability, and further, peeling off the film of the lower electrode. It is an object of the present invention to provide a method of manufacturing a dielectric deposit, and an electronic device including the dielectric deposit obtained by the manufacturing method.

The method for producing a dielectric deposit according to the present invention includes:
Forming a lower electrode on the substrate;
Forming a dielectric layer made of a ferroelectric material or a piezoelectric material on the lower electrode;
Forming an upper electrode on the dielectric layer,
The step of forming the lower electrode includes:
Forming a first metal layer by ion beam sputtering or DC sputtering;
And a step of depositing a second metal layer on the first metal layer by an electrolytic plating method.

According to this method of manufacturing a dielectric deposit, when forming the lower electrode on the substrate, the first metal layer is formed by ion beam sputtering or DC sputtering, and then on the first metal layer. Since the second metal layer is deposited by the electrolytic plating method, the crystallinity of the obtained lower electrode can be improved, and thereby the crystallinity of the dielectric layer formed on the lower electrode can also be improved. Can do. In addition, the lower electrode can be prevented from peeling off the substrate, and the reliability of the obtained dielectric deposit can be improved.
That is, by forming the first metal layer on the substrate by ion beam sputtering or DC sputtering, the first metal layer strongly bites into the surface layer portion of the substrate that is the base, and therefore the film of the lower electrode Peeling is prevented. Further, on the first metal layer thus formed, for example, the second metal layer is deposited by the electrolytic plating method using the first metal layer as a cathode. Therefore, by appropriately setting the conditions for electrolytic plating, etc. The orientation of the film and the surface roughness of the film can be adjusted to desired properties. Therefore, the crystallinity as the lower electrode can be improved, and the crystallinity of the dielectric layer formed thereon can be improved.

In the method for manufacturing a dielectric deposit, it is preferable that the first metal layer and the second metal layer are made of a platinum group.
In particular, when the second metal layer formed by electrolytic plating is made of platinum (platinum group), the platinum (platinum group) has a high orientation and a low specific resistance, so that the film thickness can be reduced. Therefore, it is possible to reduce the thickness of the entire lower electrode, and thereby it is possible to miniaturize the obtained dielectric deposit.

The dielectric layer is preferably a perovskite oxide layer.
In the method for manufacturing the dielectric deposit, the dielectric layer may be a ferroelectric, the dielectric deposit may be a ferroelectric capacitor, and the dielectric layer may be a piezoelectric body. And the dielectric deposit may be a piezoelectric element.

  The electronic device of the present invention includes a dielectric deposit obtained by the above-described method for manufacturing a dielectric deposit.

Hereinafter, the present invention will be described in detail with reference to the drawings.
First, a dielectric deposit according to the manufacturing method of the present invention will be described.
FIG. 1 is a side sectional view schematically showing a dielectric deposit obtained by the manufacturing method according to the present embodiment, and reference numeral 10 in FIG. 1 denotes a dielectric deposit. The dielectric deposit 10 includes a substrate 1, an adhesion layer 2 formed on the substrate 1, a lower electrode 4 formed on the adhesion layer 2, and a dielectric formed on the lower electrode 4. It is configured to include (include) the layer 5 and the upper electrode 6 formed on the dielectric layer 5. In this embodiment, the substrate of the present invention is composed of the substrate 1 and the adhesion layer 2.

  As the substrate 1, for example, a silicon substrate can be used. As the adhesion layer 2, for example, a laminated film of silicon oxide and titanium oxide (TiOx) can be used. The adhesion layer 2 allows the substrate 1 and the lower electrode 4 to adhere more favorably. Note that the adhesion layer 2 may not be formed.

  The lower electrode 4 is one electrode for applying a voltage to the dielectric layer 5. In this embodiment, the lower electrode 4 includes a first metal layer 40 and a second metal layer 42 formed on the first metal layer 40. It is composed of. Further, the lower electrode 4 is formed by etching using the same mask as the dielectric layer 5, for example, so that the lower electrode 4 is formed in substantially the same planar shape as the dielectric layer 5.

The first metal layer 40 is formed by an ion beam sputtering method or a DC sputtering method, and is formed to a thickness of about 1 nm to 200 nm, for example. The second metal layer 42 is formed by an electrolytic plating method, and is formed to a thickness of about 10 nm to 200 nm, for example.
The first metal layer 40 and the second metal layer 42 are formed of a noble metal or a platinum group, for example, platinum (Pt), iridium (Ir), ruthenium (Ru), palladium (Pd), or the like. In particular, for the first metal layer 40, nickel (Ni) can also be used. Of these metals, platinum is particularly suitable. In the present embodiment, both the first metal layer 40 and the second metal layer 42 are formed of platinum.

The dielectric layer 5 is made of a ferroelectric material or a piezoelectric material, and is made of, for example, a perovskite oxide made of an oxide having a perovskite structure. This perovskite oxide is, for example, represented by the general formula of ABO ₃ , and for example, A can include Pb, and B can include at least one of Zr and Ti. Furthermore, B can also contain at least one of V, Nb, and Ta. In this case, the oxide can include at least one of Si and Ge. More specifically, examples of the oxide include lead zirconate titanate (Pb (Zr, Ti) O ₃ ) and lead niobate zirconate titanate (Pb (Zr, Ti, Nb) O ₃ ). Can be used.

  The upper electrode 6 is the other electrode for applying a voltage to the dielectric layer 5. Similar to the lower electrode 4, the upper electrode 6 is patterned using, for example, the same mask as the dielectric layer 5. They are formed in substantially the same planar shape. Further, like the lower electrode 4, the upper electrode 6 is formed of a noble metal such as platinum (Pt), iridium (Ir), ruthenium (Ru), palladium (Pd).

  The dielectric deposit 10 becomes a ferroelectric capacitor (ferroelectric capacitor) when the dielectric layer 5 is a ferroelectric, and constitutes a ferroelectric memory as will be described later. Further, the dielectric deposit 10 becomes a piezoelectric element when the dielectric layer 5 is a piezoelectric body, and becomes an actuator in, for example, an ink jet recording head as will be described later.

Next, a method for manufacturing a dielectric deposit according to the present invention will be described with reference to FIGS.
First, for example, a silicon substrate is prepared as the substrate 1.
Next, the adhesion layer 2 is formed on the substrate 1. The adhesion layer 2 is formed by, for example, forming a silicon oxide layer by a thermal oxidation method. Next, a titanium (Ti) film is formed by sputtering, and this is further thermally oxidized to form a titanium oxide (TiO ₂ ) film from the titanium film.

  Next, a platinum film is formed on the adhesion layer 2 with high energy by an ion beam sputtering method or a DC sputtering method to form a first metal layer 40. By using the ion beam sputtering method or the DC sputtering method, as shown in FIGS. 2 and 3, the material particles (platinum particles) 40a of the first metal layer 40 are digged into the adhesion layer 2, and the first metal layer 40 is formed. Can be formed. Thus, the 1st metal layer 40 can be strongly stuck with respect to the contact | adherence layer 2 by making the material particle 40a bite into the contact | adherence layer 2. FIG.

Here, in particular, in the ion beam sputtering method, it is not necessary to generate plasma by discharge, so that film formation can be performed in a high vacuum. For this reason, it is difficult for the impurity gas to be mixed in the film. As a result, film peeling (hillocks) can be prevented from occurring due to high-temperature annealing (for example, 500 ° C. to 700 ° C.) in the process of forming the dielectric layer 5.
In addition, about the temperature at the time of formation of the 1st metal layer 40, it can be set as room temperature-1000 degreeC, for example.

  Next, the second metal layer 42 is formed on the first metal layer 40 with low energy. The second metal layer 42 is formed by electrolytic plating using the first metal layer 40 as a cathode. Specifically, as shown in FIG. 4, the deposited body formed up to the first metal layer 40 is immersed in the electrolytic plating solution 44 in the liquid tank 45, and the first metal layer 40 is energized, whereby the first metal layer A second metal layer (plating layer) 42 is deposited on 40. As described above, platinum is particularly suitable for the second metal layer 42. Therefore, an electrolytic platinum plating solution is used as the electrolytic plating solution 44. With respect to the conditions for electrolytic plating, the orientation of the film of the second metal layer 42 obtained by appropriately setting the concentration and temperature of the plating solution, the potential to be energized to the first metal layer 40 as the cathode, the energization time, and the like. And the surface roughness of the film can be adjusted to desired properties.

That is, by forming the second metal layer 42 by electrolytic plating in this way, the film thickness distribution is good, and the film can be formed more densely than the sputtering method. As described above, the crystallinity of the dielectric layer 5 and the orientation thereof can be further improved by improving the crystallinity and the orientation.
Further, since the second metal layer 42 is formed by the electrolytic plating method as described above, there is no damage caused by collision of plasma and particles at a low temperature as compared with the case where the second metal layer 42 is formed at a low temperature. 42 can be formed.

  Next, the dielectric layer 5 is formed on the second metal layer 42. The dielectric layer 5 can be formed by, for example, a sol-gel method. Here, as a method for forming the dielectric layer 5 by the sol-gel method, first, a compound containing Pb, Zr, Ti or the like, which is a ferroelectric or piezoelectric metal element constituting the dielectric layer 5, such as an alkoxide or the like The organic compound is dissolved (dispersed) in a solvent (dispersion medium), and the obtained solution (dispersion) is disposed on the lower electrode 4 (second metal layer 42) by a known coating method, and then fired. Thus, a technique of obtaining the dielectric layer 5 is employed. As a method other than the sol-gel method, the dielectric layer 5 may be formed by a liquid phase process such as a gas phase method such as a sputtering method, a CVD method, or an MOCVD method, or a hydrothermal synthesis method.

Next, the upper electrode 6 is formed on the dielectric layer 5. The upper electrode 6 can be formed by, for example, a sputtering method, a vacuum deposition method, or the like.
Thereafter, a resist is applied on the upper electrode 6 to form a resist layer (not shown). The resist layer is patterned by a known exposure / development technique, and the upper electrode 6 is masked using the obtained resist pattern as a mask. The dielectric layer 5 and the lower electrode 4 are etched together to form the dielectric deposit 10 of the present invention shown in FIG.

Next, experimental examples will be described.
In this experimental example, the dielectric deposit 10 was formed based on the manufacturing method described above. The substrate 1 is a silicon substrate, the adhesion layer 2 is a laminated film of silicon oxide and titanium oxide (TiOx), the first metal layer 40 and the second metal layer 42 are platinum, and the dielectric layer 5 is niobic acid. Lead zirconate titanate was used, and platinum was used as the upper electrode 6.

The first metal layer 40 was formed using an ion beam sputtering method. The conditions of the ion beam sputtering method were as follows: temperature: room temperature, power: 120 mA / 1200 V, sputtering time: 30 minutes, film thickness: 40 nm. The second metal layer 42 was formed by electrolytic plating using the first metal layer 40 as a cathode. The electroplating method was performed by using an electroplating platinum plating solution as the electroless plating solution 44, energizing conditions for the first metal layer 40 with two potentials of 1 V and 2 V, and an energizing time of 1 minute each. .
For comparison, the lower electrode 4 was formed by a single layer by ion beam sputtering to form a dielectric deposit as a comparative example.

  FIG. 5 shows the hysteresis characteristics of the dielectric deposit 10 (the conduction potential when the second metal layer 42 is formed is 1 V) as the inventive product 1 according to this experimental example, and FIG. 6 shows the inventive product according to this experimental example. FIG. 7 shows hysteresis characteristics of the dielectric deposit 10 (the conduction potential when the second metal layer 42 is formed is 1 V) as 1, and FIG. 7 shows the hysteresis characteristics of the dielectric deposit (one lower electrode 4) of the comparative example. It is.

  As shown in FIGS. 5 to 7, the dielectric deposits 10 of the inventive products 1 and 2 according to the present experimental example can obtain a hysteresis characteristic with better squareness than the dielectric deposit of the comparative example. did it. This is because the second metal layer 42 is formed by electrolytic plating to improve its crystallinity, and therefore the dielectric layer 5 formed using this as a base also has good crystallinity. Conceivable.

Moreover, 2Pr was calculated | required from the polarization value (Polarization; Pr) calculated | required in FIGS. 5-7 about the said invention products 1 and 2 and the comparative example product, and this was made into a regulation value and voltage dependency was calculated | required. FIG. 8 shows the result when the dielectric layer 5 is fired in a lamp annealing furnace, and FIG. 9 shows the result when the dielectric layer 5 is fired in a pressure lamp annealing furnace.
From the results shown in FIGS. 8 and 9, it was found that the rise of 2Pr from 2V is very good particularly in the product 2 of the present invention.

FIG. 10 is an X-ray diffraction diagram of 2θ-θ scan of the dielectric layer 5 and the second metal layer 42 of the lower electrode 4 according to this experimental example. FIG. 11 is an X-ray diffraction diagram of ω scan of the dielectric layer 5 according to this experimental example, and FIG. 12 is an X-ray diffraction diagram of ω scan of the second metal layer 42 according to this experimental example.
From FIG. 10, it was found that there was a peak at a position of 40 °, and the obtained dielectric layer 5 and second metal layer 42 had good uniaxial orientation. Further, the half width (FWHM) of the dielectric layer 5 obtained from the result of FIG. 11 is 3.25, and the half width (FWHM) of the second metal layer 42 obtained from the result of FIG. 12 is 1.12. Since both are small values, it was confirmed that the films each had good crystallinity.

  According to such a method of manufacturing the dielectric deposit 10, when forming the lower electrode 4 on the substrate, the first metal layer 40 is formed by ion beam sputtering or DC sputtering, and then the first metal layer 40 is formed. Since the second metal layer 42 is deposited on the metal layer 40 by the electrolytic plating method, the crystallinity of the obtained lower electrode 4 can be improved, and thereby the dielectric layer 5 formed on the lower electrode 4. The crystallinity can be improved. Moreover, film peeling of the lower electrode 4 with respect to the substrate can be prevented, and the reliability of the obtained dielectric deposit 10 can be improved.

That is, by forming the first metal layer 40 on the substrate by the ion beam sputtering method or the DC sputtering method, the first metal layer 40 can be strongly digged into the adhesion layer 2 that is the base, and therefore the lower electrode. 4 film peeling can be prevented.
In addition, since the second metal layer 42 is deposited on the first metal layer 40 formed in this manner by the electrolytic plating method using the first metal layer 40 as a cathode, the conditions for the electrolytic plating are appropriately set. Thereby, the orientation of the film and the surface roughness of the film can be adjusted to desired properties. Therefore, the crystallinity of the lower electrode 4 can be improved, and the crystallinity of the dielectric layer 5 formed thereon can be improved, whereby the dielectric deposition having good squareness hysteresis characteristics. The body 10 can be provided.

  In addition, according to this manufacturing method, the second metal layer 42 is formed by an electrolytic plating method. Therefore, by appropriately setting the conditions and the like, it is possible to make the obtained film dense, thereby reducing the resistance. The value can be kept low. Therefore, the entire thickness of the lower electrode 4 can be reduced, and a margin in the subsequent etching process can be obtained, so that the lower electrode 4 can be miniaturized (narrow pitch). Accordingly, since the dielectric deposit 10 to be formed can be miniaturized, for example, it is possible to cope with the increase in capacity of the ferroelectric memory.

Next, a modified example of the dielectric deposit body 10 according to the present embodiment will be described.
FIG. 13 is a cross-sectional view schematically showing an example of a modification of the dielectric deposit 10 shown in FIG. 1, and FIG. 14 shows another example of the modification of the dielectric deposit 10 shown in FIG. It is sectional drawing shown typically.

The dielectric deposit body 10 shown in FIG. 13 is different from the dielectric deposit body 10 shown in FIG. 1 in that the lower electrode 4 has a third metal layer 41 between the first metal layer 40 and the second metal layer 42. It is the point comprised by having.
As the third metal layer 41, iridium (Ir) is preferably used. By using iridium as the third metal layer 41, the reliability of the dielectric deposit 10 can be improved. Moreover, as a formation method of this 3rd metal layer 41, ion beam sputtering method, DC sputtering method, etc. are employable, for example. The third metal layer 41 can be formed such that the first metal layer 40 under the third metal layer 41 is partially exposed as shown in FIG. 13 by reducing the film thickness to about 1 nm, for example.

  The dielectric deposit body 10 shown in FIG. 14 is different from the dielectric deposit body 10 shown in FIG. 1 in that a hard layer 3 is provided between the adhesion layer 2 and the lower electrode 4. The hard layer 3 and the adhesion layer 2 function as an elastic layer in, for example, an ink jet recording head. As such a hard layer 3, for example, yttria-stabilized zirconia, cerium oxide, zirconium oxide or the like can be used. Moreover, as a formation method of the hard layer 3, CVD method, a sputtering method, a vapor deposition method etc. are employable, for example.

  In addition to the above-described modification, for example, the first metal layer 40 may have a two-layer structure of a layer formed by ion sputtering and a layer formed by DC sputtering. In particular, when the dielectric deposit 10 is a ferroelectric capacitor, a film made of, for example, TiAlN is used as an oxygen barrier film below the lower electrode 4 (for example, between the adhesion layer 2 and the lower electrode 4). It can also be provided.

  Although the embodiments of the present invention have been described in detail as described above, those skilled in the art will readily understand that many modifications are possible without substantially departing from the novel matters and effects of the present invention. Accordingly, all such modifications are included in the scope of the present invention. For example, the present invention is applied to electronic devices such as various piezoelectric elements (for example, ink jet recording heads and actuators used in ink jet printers) and various ferroelectric capacitors (for example, ferroelectric memories). Applicable.

FIG. 3 is a side sectional view schematically showing a dielectric deposit according to the present invention. FIG. 2 is a side sectional view schematically showing a method for manufacturing the dielectric deposit shown in FIG. 1. FIG. 2 is a side sectional view schematically showing a method for manufacturing the dielectric deposit shown in FIG. 1. FIG. 2 is a side sectional view schematically showing a method for manufacturing the dielectric deposit shown in FIG. 1. The graph which shows the hysteresis characteristic of the dielectric deposit body as the invention product. The graph which shows the hysteresis characteristic of the dielectric deposit body as the invention item 2. The graph which shows the hysteresis characteristic of the dielectric material laminated body as a comparative example goods. The graph which shows the voltage dependence of 2Pr. The graph which shows the voltage dependence of 2Pr. The X-ray diffraction pattern of the 2 (theta)-(theta) scan of a dielectric material layer and a lower electrode (2nd metal layer). The X-ray diffraction pattern of the omega scan of a dielectric material layer. FIG. 6 is an X-ray diffraction diagram of ω scan of a second metal layer. Sectional drawing which shows typically an example of the modification of a dielectric material deposition body. Sectional drawing which shows typically another example of the modification of a dielectric material deposition body.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Board | substrate, 2 ... Adhesion layer, 3 ... Hard layer, 4 ... Lower electrode, 5 ... Dielectric layer, 6 ... Upper electrode, 10 ... Dielectric deposit body, 40 ... 1st metal layer, 41 ... 3rd metal layer , 42 ... second metal layer

Claims (6)

Forming a lower electrode on the substrate;
Forming a dielectric layer made of a ferroelectric material or a piezoelectric material on the lower electrode;
Forming an upper electrode on the dielectric layer,
The step of forming the lower electrode includes:
Forming a first metal layer by ion beam sputtering or DC sputtering;
Depositing a second metal layer on the first metal layer by an electrolytic plating method.   2. The method of manufacturing a dielectric deposit according to claim 1, wherein the first metal layer and the second metal layer are made of a platinum group.   The method for manufacturing a dielectric deposit according to claim 1, wherein the dielectric layer is a perovskite oxide layer.   The method for manufacturing a dielectric deposit according to any one of claims 1 to 3, wherein the dielectric layer is a ferroelectric, and the dielectric deposit is a ferroelectric capacitor.   The method for manufacturing a dielectric deposit according to any one of claims 1 to 3, wherein the dielectric layer is a piezoelectric, and the dielectric deposit is a piezoelectric element. The electronic device containing the dielectric deposit obtained by the manufacturing method of the dielectric deposit in any one of Claims 1-3.

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