JP2007286805A - Memory device and data transfer method, and display drive device and display drive method using them - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory device capable of simplifying transfer of data to each memory. <P>SOLUTION: The memory device comprises IC00-IC03 as a plurality of memory units, and is adapted to execute a burst transfer mode for successively transferring a plurality of unit data to each IC. Each IC includes a transfer start signal line fs receiving a transfer start signal, a counter counting the unit data amount transferred to the IC in response to the transfer start signal supplied to the transfer start signal line, and a transfer end signal line fe outputting a transfer end signal when the counter counted the unit data amount. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a memory device that performs data transfer (write / read) in a burst mode across a plurality of memories, a data transfer method, and a display drive device and a display drive method using the same.

  Development of a display panel in which a large number of light emitting elements are used as pixels and arranged in a matrix has been widely promoted. As one of such display panels, a display panel using an organic EL (electroluminescence) element using an organic material for a light emitting layer as a pixel has already been commercialized. This is also due to the fact that the use of an organic compound that can be expected to have good light-emitting characteristics for the light-emitting layer of the EL element has led to an increase in efficiency and longevity that can withstand practical use.

  As a display panel using such organic EL elements, for example, a passive matrix display panel in which EL elements are simply arranged in a matrix, and a lighting control of pixels by, for example, TFTs (Thin Film Transistors) in each of the EL elements arranged in a matrix. There has been proposed an active matrix type display panel to which an element is added.

  The former display panel has a relatively simple structure and can be manufactured at a low cost. On the other hand, the latter display panel can achieve low power consumption and can be used between pixels. Therefore, it is possible to realize a high-definition display panel that constitutes a large screen.

  In any of the above-described display panels, a control device that controls lighting of the display panel includes a video memory (frame memory) that can store video data for at least one screen. Then, the video data for one screen is written into the memory, and the video data is sequentially read from the memory so that display control of the display panel is performed.

  By the way, in a display device using display pixels typified by the EL element, the number of pixels is set according to the size of the display panel, and the capacity of the video memory is also determined according to the number of pixels. Therefore, when a large number of displays having the same specifications are produced, a memory capacity corresponding to the panel size (number of pixels) is set. However, in order to make this compatible with a small variety of products, a drive circuit having a maximum size memory capacity is prepared in order to have versatility. In most cases, the maximum capacity of the memory is set. A state that is not used occurs.

  In order to increase the use efficiency of the memory, it is conceivable to increase or decrease the number of memory units according to the number of display pixels without preparing a memory for one screen corresponding to the maximum number of pixels. That is, when the number of display pixels is large, the setting is made to increase the memory unit. When the number of display pixels is small, it is possible to increase the use efficiency of the video memory by decreasing the unit accordingly. .

  In order to deal with the above-described means, a plurality of controller ICs each provided with a video memory are prepared, and these controller ICs are operated by chip selection or address designation, whereby a display panel having a relatively large number of pixels can be obtained. It can be driven. When a display panel with a small number of pixels is driven, it is possible to improve circuit utilization efficiency, in other words, cost performance, by setting the number of controller ICs small.

  FIG. 1 illustrates a basic configuration in which a plurality of controller ICs each having a video memory, that is, the above-described memory unit, and these controller ICs are chip-selected. In the example shown in FIG. 1, a driving device for a passive matrix display panel is shown as an example, and IC00 to IC03 as four controller ICs functioning as anode drivers are provided. Each of these IC00 to IC03 is provided with video memories a to d as shown in FIG.

  To each of the IC00 to IC03, video data to be displayed is sent from a CPU (Central Processing Unit) via a bus line (Data Bus). Further, the CPU is configured to supply chip select signals XCS0 to XCS3 to the IC00 to IC03. In this configuration, the cathode driver receives the synchronization signal from the controller IC00 and operates to generate a scanning timing signal.

  On the other hand, in the configuration shown in FIG. 1, the screen as the display panel is divided into four display areas indicated by A to D. Each display area A to D includes the anode driver by each of the above-described IC00 to IC03. It is configured to be driven by the cathode driver. Although not shown in the figure, the display panel is arranged so that a plurality of anode drive lines and a plurality of cathode scanning lines intersect, and the anode of the EL element is located at each intersection of the drive lines and the scanning lines. (Anode) and cathode (cathode) are connected to each other.

  FIG. 2 is a timing chart for explaining the operation of the configuration shown in FIG. 1, and receives the inverted chip select signals XCS0 to XCS3 supplied from the CPU, and receives video memories a to d in the respective IC00 to IC03. Operates such that video data (Data) supplied from the CPU via a bus line (Data Bus) is written.

  In this case, a chip select signal is sequentially supplied from the CPU to each of the IC00 to IC03, and video data of a predetermined unit is continuously sent from the CPU to each of the IC00 to IC03 set in the selected state. Burst transfer is executed. That is, for example, when IC00 is in the selected state, video data (Data) in a predetermined unit is burst transferred to the video memory a in the IC00 that is responsible for the display area A. The IC00 operates to automatically increment the address in the video memory a and sequentially write video data (Data) sent continuously to the memory a.

  After the transfer of the video data to the memory a is completed, the IC01 is next selected, and the video data (Data) is similarly burst transferred to the video memory b in the IC01 responsible for the display area B. The IC01 operates to automatically increment the address of the video memory b and write video data (Data) sent continuously to the memory b. Further, the same burst transfer is executed for the IC02 and IC03 responsible for the display areas C and D, and the video data of the entire display screen composed of A, B, C, and D is written in the memories a to d.

  As a result, the four anode drivers as the controller ICs and the cathode driver operate, and the pixels are selected based on the video data written in the memories a to d in synchronization with the scanning of the display panel composed of A to D. A typical lighting operation is performed, and one screen is displayed. The same operation is repeated in the next frame, and a continuous moving image can be displayed on the display panel composed of A to D.

  FIG. 3 and FIG. 4 show examples in which a plurality of controller ICs each having a video memory are provided, and video data is burst transferred to the video memories a to d for each IC by addressing these controller ICs. Is shown. Note that the configuration shown in FIG. 3 is basically the same as the configuration shown in FIG. 1, and therefore the difference will be described below.

  In order to realize the burst transfer of the video data by the address designation as described above, in the example shown in FIG. 3, the addresses (Address = 00b, = 01b, = 10b, = 11b) are set in the IC00 to IC03. Yes. An address setting line ADD is connected from the CPU to each of IC00 to IC03.

  As shown in FIG. 4, when the chip select signal is in the inverted state (XCS), video data (Data) is burst transferred to the video memories a to d. 3 and 4, the chip select signal is used, but this is configured so that the chip select function can be used when there are similar blocks other than those shown in FIG. Therefore, the chip select line XCS is not necessarily required in the range shown in the figure.

  In the configuration shown in FIG. 3, as shown in FIG. 4, video data (Data) is sequentially transferred in bursts to the video memories a to d in each IC designated by the CPU. Receiving this, each of the video memories a to d executes an operation of sequentially writing video data in units of one burst. As in the example shown in FIG. 1 and FIG. 2, the continuous moving images are displayed on the display screen (display panel) composed of A to D based on the video data written in the memories a to d. Works to let you.

An example in which data is burst transferred to each IC memory chip-selected as described above is disclosed in Patent Document 1, and each addressed memory of each IC is individually disclosed. An example of burst transfer of data is disclosed in Patent Document 2.
JP-A-9-91955 JP-A-5-324465

  By the way, in the above-described data write operation to the memory by burst transfer, it is necessary to perform chip selection or address designation for each IC, and this has a technical problem that the number of signal lines increases. Further, the data transfer side needs to manage video data divided for each IC, which complicates data management. Furthermore, for example, in order to manage video data collectively, there are technical problems such as specifying an address for each line of the IC, increasing redundant portions in data transfer, and reducing the data transfer speed. Yes.

  The present invention has been made paying attention to the technical problems as described above, and further simplifies the transfer of data to each memory while following the data write operation to the memory by the burst transfer described above. It is an object of the present invention to provide a memory device, a data transfer method, a display drive device and a display drive method using the same.

  According to another aspect of the present invention, there is provided a memory device including a plurality of memory units, wherein a plurality of unit data is sequentially transferred to each of the memory units. A memory device configured to execute a transfer mode, wherein each memory unit receives a transfer start signal line for receiving a transfer start signal and the transfer start signal supplied to the transfer start signal line. A counter for counting the unit data amount transferred to the memory unit; and a transfer end signal line for outputting a transfer end signal when the counter counts the unit data amount. Have

  In this case, as described in claim 2, each of the memory units can select an operation mode for receiving a transfer start signal on the transfer start signal line and simultaneously outputting a transfer end signal to the transfer end signal line. It is desirable to be configured as described above.

  The data transfer method according to the present invention, which has been made to solve the above-mentioned problems, is a memory device comprising a plurality of memory units as claimed in claim 3, and a plurality of units for each memory unit. A data transfer method to a memory device in which a burst transfer mode for sequentially transferring data is executed, wherein the data is transferred to the memory unit when the one memory unit receives a transfer start signal. Start counting the amount of unit data, output a transfer end signal when the unit data amount is counted, and supply the transfer end signal to another memory unit as a transfer start signal It is characterized in that it operates.

  In this case, as one preferred embodiment, at least one of the memory units outputs the transfer end signal at the same time as receiving the transfer start signal, and outputs the transfer end signal to the other Control is performed such that an operation mode supplied as a transfer start signal to one memory unit is selected.

  Moreover, the display drive device according to the present invention made to solve the above-described problems uses the memory device according to claim 1 or 2, wherein each of the plurality of unit data is video data, The present invention is characterized in that a display panel is provided on which video display is performed based on video data transferred and written to each memory unit.

  Further, in the display driving method according to the present invention made to solve the above-described problem, the data transfer method according to claim 3 or 4 is used, and each of the plurality of unit data is video data. The display panel is display-driven based on the video data transferred and written to each memory unit.

  Hereinafter, the memory device according to the present invention will be described based on an example in which the memory device according to the present invention is applied to a light emitting display panel drive device (passive matrix display panel drive device). Note that, in each embodiment described below, portions having the same functions as those of the configuration shown in FIG. 1 or FIG. 3 described above are denoted by the same reference numerals, and thus detailed description thereof will be omitted as appropriate.

  In the first embodiment shown in FIG. 5, each IC00 to IC03 functions as an anode driver in the same manner as each IC shown in FIGS. 1 and 3 described above. As shown in the figure, video memories (Memory: ad) are provided. Accordingly, each of the IC00 to IC03 can be referred to as a memory unit.

  In the example shown in the figure, addresses (Address = 00b, = 01b, = 10b, = 11b) are set in the IC00 to IC03, and the address setting line ADD is set from the CPU to the IC00 to IC03. Is connected.

  In the example shown in FIG. 5, the chip select line XCS is connected from the CPU to each IC. However, in the case where there are similar blocks other than those shown in FIG. Therefore, the chip select line XCS is not necessarily required in the range shown in the figure.

  Each IC is provided with a counter, which counts up the unit data amount (one burst unit) transferred to each IC when video data is burst transferred by the CPU. Is. As described above, when video data is transferred in bursts, a counter that automatically increments an address in the video memory can be used as it is, and can be constituted by, for example, a one-line shift register.

  The counter starts counting the amount of video data transferred from the CPU when receiving a transfer start signal on a transfer start signal line (indicated by symbol fs in IC00) provided in each IC. It functions to output a transfer end signal to a transfer end signal line (indicated by the symbol fe in IC00) when the burst unit is counted.

  That is, in the configuration shown in FIG. 5, the code XCSGD0 is a transfer end signal output from IC00 and a transfer start signal supplied to IC01. The code XCSGD1 is a transfer end signal output from the IC01 and a transfer start signal supplied to the IC02. Similarly, code XCSGD2 is a transfer end signal output from IC02 and is a transfer start signal supplied to IC03, and code XCSGD3 is a transfer end signal output from IC03 and a transfer start signal supplied to IC00. Signal.

  In each of the ICs described above, a bypass switch (IC00 has a code SW that can select an operation mode in which the count-up function of the counter is further stopped and the input transfer start signal is bypassed and output as a transfer end signal). And a logic circuit (Logic) for controlling the bypass switch to be turned on or off. In the embodiment shown in FIG. 5, all the bypass switches SW are set to the off state.

  FIG. 6 is a timing chart for explaining the operation of the configuration shown in FIG. First, an IC for starting data transfer, that is, IC00 whose address is 00b in this example, is designated by the XCS signal and the ADD signal, and video data is burst transferred. In the video memory in the designated IC00, data is sequentially transferred from the 0th column of the 0th row of the memory address. When data is transferred to the end of the row, the counter counts up one burst unit, and IC00 outputs a transfer end signal XCSGD0. Note that a symbol Da shown in FIG. 6 indicates video data of one burst unit transferred at this time.

  The transfer end signal XCSGD0 is input as a transfer start signal in the IC01, and the IC01 sequentially transfers the next data from the 0th column of the address 0th row in the memory. At this time, as described above, the counter counts up the amount of data to be transferred, and when counting up one burst unit, IC01 outputs the transfer end signal XCSGD1. Note that the symbol Db shown in FIG. 6 indicates the video data of one burst unit transferred at this time.

  When the above operation is repeated and IC00 receives the transfer end signal XCSGD3 of IC03, IC00 sequentially transfers the next data from the 0th column of the first row, which is the next row of the 0th row that has been transferred. In this way, the video data of the entire display screen composed of A to D is written in the memories a to d. FIG. 7 illustrates the image of the data transfer operation described above.

  When data for one screen is written in the memories a to d, the four anode drivers as the controller ICs and the cathode driver are operated, and each memory is synchronized with the scanning of the display panel composed of A to D. A selective lighting operation of the pixels based on the video data written in a to d is executed, and display for one screen is performed. The same operation is repeated in the next frame, and a continuous moving image can be displayed on the display panel composed of A to D.

  FIG. 8 shows a second embodiment of the memory device according to the present invention. In FIG. 8, portions that perform the same functions as those shown in FIG. 5 already described are denoted by the same reference numerals, and therefore description thereof will be omitted as appropriate. The embodiment shown in FIG. 8 shows an example in which data is burst-transferred to a specific IC. In this example, two central ICs out of four ICs, that is, IC01 and IC02, are shown. An example in which data is burst transferred is shown.

  In order to realize the burst transfer described above, in the configuration shown in FIG. 8, the bypass switches IC00 and IC03 are turned on, and the bypass switches IC01 and IC02 are set off.

  In the setting state of the bypass switch described above, as shown in FIG. 9, the data transfer start IC, that is, IC01 whose address is 01b in this example is designated by the XCS signal and the ADD signal, and the video data is burst transferred. In the video memory in the designated IC01, data is sequentially transferred from the 0th column of the 0th row of the memory address. When data is transferred to the end of the row, the counter counts up one burst unit, and IC01 outputs a transfer end signal XCSGD1. Note that the symbol Da shown in FIG. 9 indicates video data of one burst unit transferred at this time.

  Then, IC02 receives XCSGD1 as a transfer start signal and performs burst transfer of video data in the same manner as IC01. On the other hand, in this embodiment, when IC03 receives the transfer end signal XCSGD2 of IC02, it outputs the transfer end signal XCSGD3 at the same time. The IC00 receiving the transfer end signal XCSGD3 outputs a transfer end signal XCSGD0 at the same time. Subsequently, the IC01 that has received the transfer end signal XCSGD0 sequentially transfers the next data from the 0th column of the next row that has been transferred. FIG. 10 illustrates an image of the above-described data transfer operation.

  As shown in FIG. 10, in this embodiment, data is transferred only to IC01 and IC02. Therefore, according to this, as shown in FIG. 8, the video display range is set in the areas B and C on the display panel.

  Next, FIG. 11 shows a third embodiment of the memory device according to the present invention. In FIG. 11, portions that perform the same functions as those shown in FIG. 5 already described are denoted by the same reference numerals, and therefore description thereof will be omitted as appropriate.

  In the embodiment shown in FIG. 11, an IC for starting transfer is designated by a transfer start signal XCSGD supplied from the CPU. That is, in the embodiment shown in FIG. 5 and FIG. 8, the IC that starts the transfer is determined by the XCS signal and the ADD signal, whereas in the configuration shown in FIG. As shown in FIG. 12, the operation is performed so that the IC whose transfer is started is determined by the external signal XCSGD.

  The basic operation in the configuration shown in FIG. 11 is the same as that shown in FIGS. 5 and 8 described above. After the IC to start the transfer is determined, one line for each IC. Each data is transferred in bursts, and the data is written to each memory. That is, the image of the data transfer (write) operation is the same as the example shown in FIG. According to the configuration shown in FIG. 11, XCS signal lines and ADD signal lines can be reduced.

  FIG. 13 shows a fourth embodiment of the memory device according to the present invention. In FIG. 13, portions that perform the same functions as those shown in FIG. 5 already described are denoted by the same reference numerals, and therefore description thereof will be omitted as appropriate.

  In the embodiment shown in FIG. 13 as well, similarly to the example shown in FIG. 11, an operation is performed so that an IC for starting data transfer is designated first. In the embodiment shown in FIG. 13, a write command signal XWR is supplied to each IC from the CPU. Then, as shown in FIG. 14, the data on the Data line after the transition to XCS = “L” is processed as an IC address, thereby designating an IC that starts data transfer first. In this example, in order to start transfer from IC00, ADD = 00.

  The basic operation in the configuration shown in FIG. 13 is the same as that shown in FIG. 5 and FIG. 8 described above. After the IC to start the transfer is determined, one line for each IC. The operation is performed so that the data is burst transferred and the data is written to each memory. That is, the image of the data transfer (write) operation is the same as the example shown in FIG.

  According to the above-described form, the write data after the transition to XCS = “L” is processed as address information as indicated by the chain line in FIG. Thereby, the ADD line can be deleted.

  According to each of the embodiments described above, each IC functioning as a memory unit receives a transfer start signal line that receives a transfer start signal and a transfer start signal supplied to the transfer start signal line. Since each counter is provided with a counter that counts the unit data amount to be transferred and a transfer end signal line that outputs a transfer end signal when the counter counts the unit data amount, each IC has one burst unit. An operation of sequentially writing video data can be executed. Therefore, simplification of data management and data transfer, speeding up of data transfer, reduction of signal lines, and the like can be realized.

It is the block diagram which showed the basic composition which performs data transfer by the conventional chip select function. FIG. 2 is a timing chart for explaining the operation of the configuration shown in FIG. 1. It is the block diagram which showed the basic composition which performs data transfer by the conventional addressing function. FIG. 4 is a timing chart for explaining the operation of the configuration shown in FIG. 3. 1 is a block diagram showing a first embodiment of the present invention. FIG. 6 is a timing chart for explaining the operation of the configuration shown in FIG. 5. FIG. 6 is a schematic diagram illustrating an image of a data transfer operation performed by the configuration illustrated in FIG. 5. It is the block diagram which showed 2nd Embodiment of this invention. FIG. 9 is a timing chart for explaining the operation of the configuration shown in FIG. 8. It is a schematic diagram explaining the image of the data transfer operation | movement performed by the structure shown in FIG. It is the block diagram which showed the 3rd Embodiment of this invention. FIG. 12 is a timing chart for explaining the operation of the configuration shown in FIG. 11. It is the block diagram which showed 4th Embodiment of this invention. FIG. 14 is a timing chart for explaining the operation of the configuration shown in FIG. 13.

Explanation of symbols

A to D Display panel (display area)
Counter Counter IC00 to IC03 Memory unit SW Bypass switch a to d Memory fs Transfer start signal line fe Transfer end signal line

Claims (6)

A memory device comprising a plurality of memory units and configured to execute a burst transfer mode for sequentially transferring a plurality of unit data to each of the memory units,
Each memory unit includes a transfer start signal line that receives a transfer start signal, and a counter that receives the transfer start signal supplied to the transfer start signal line and counts the unit data amount transferred to the memory unit. And a transfer end signal line for outputting a transfer end signal when the counter counts the unit data amount, respectively.   Each of the memory units is configured such that an operation mode for outputting a transfer end signal to the transfer end signal line can be selected simultaneously with receiving a transfer start signal on the transfer start signal line. The memory device according to claim 1. A data transfer method to a memory device in which a memory device is configured by a plurality of memory units, and a burst transfer mode in which a plurality of unit data is sequentially transferred to each memory unit is executed,
When the one memory unit receives a transfer start signal, it starts counting the amount of the unit data transferred to the memory unit, and outputs a transfer end signal when the unit data amount is counted. A data transfer method, wherein the transfer end signal is operated to be supplied as a transfer start signal to another memory unit.   At least one of the memory units receives the transfer start signal and outputs a transfer end signal simultaneously with the operation mode for supplying the transfer end signal to another memory unit as a transfer start signal. 4. The data transfer method according to claim 3, wherein the data transfer method is selected.   The memory device according to claim 1 or 2, wherein each of the plurality of unit data is video data, and video display is performed based on the video data transferred and written to each memory unit. A display driving device comprising a display panel.   5. The data transfer method according to claim 3 or 4, wherein each of the plurality of unit data is video data, and a display panel is displayed based on the video data transferred and written to each memory unit. A display driving method of a display panel, characterized by driving.

Images