JP2007281806A - Frequency synthesizer corresponding to multimode - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a frequency synthesizer corresponding to multimode which carries out the optimization of a consumption current in all modes, and suppresses enlargement of a chip area. <P>SOLUTION: The synthesizer is provided with a VCO (voltage controlled oscillator) 6, a variable frequency divider which divides a frequency of an output signal of the VCO, a phase comparator 3c which compares phases of the output signal of the variable frequency divider and a reference signal, a charge pump 4c whose charge and discharge outputs are controlled based on an output signal of the phase comparator, and a low pass filter which obtains an average of output signals of the charge pump, and supplies to the VCO as control voltage. The variable frequency divider is configured to count output of a modulus prescaler by a programmable counter, controls a frequency dividing ratio of the modulus prescaler based on the count value, and establishes a frequency dividing ratio from a fraction frequency dividing control unit. The synthesizer is composed to be provided with a plurality of modulus prescalers whose composition is different, and composes frequency synthesizers whose phase comparison frequencies are different by switching the modulus prescalers to the same output frequencies of the VCO. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a frequency synthesizer, and more particularly to a multimode-compatible PLL frequency synthesizer used in a radio base station or the like.

  FIG. 5 shows a conventional configuration in which two frequency synthesizers are connected in parallel in order to alternately use a plurality of fractional-N fractional frequency synthesizers requiring different performances in a time division manner. 1 is a reference oscillator, 2a and 2b are fixed frequency dividers, 3a and 3b are phase comparators, 4a and 4b are charge pumps, 5 is an LPF (low pass filter), 6 is a VCO (voltage controlled oscillator), 7a and 7b Is a modulus prescaler, 8a and 8b are programmable counters, 9 is a fractional frequency division control unit, and 10 is a VCO control unit, which constitute PLL (1) 12 and PLL (2) 13, respectively. Reference numeral 11 denotes a change-over switch that switches between the outputs of the two PLLs.

  This frequency synthesizer will be described in more detail below along with its operation. The modulus prescalers 7a and 7b and the programmable counters 8a and 8b output a signal fdiv obtained by dividing the frequency of the output signal (fvco) of the VCO 6 according to the frequency division ratio set by the fractional frequency division control unit 9. The phase comparators 3a and 3b compare the phases of fdiv and the reference signal (fref) and output pulse signals U and D corresponding to the phase difference to the charge pumps 4a and 4b. The charge pumps 4a and 4b charge and discharge the charge to and from the LPF 5 based on the pulse signals U and D output from the phase comparators 3a and 3b, whereby a DC voltage is input to the control voltage terminal of the VCO 6. The output of the VCO 6 whose frequency changes according to the voltage applied to the control voltage terminal is output to the changeover switch 11 and to the modulus prescalers 7a and 7b. The changeover switch 11 outputs one of fvco1 and fvco2 to the outside as fvco3.

  As described above, in this frequency synthesizer, the VCO 6, the modulus prescalers 7a and 7b, the programmable counters 8a and 8b, the phase comparators 3a and 3b, the charge pumps 4a and 4b, and the LPF 5 form a feedback loop, and fref and fdiv When the frequency and phase coincide with each other, the lock state is entered, and the output signal of the VCO 6 is stabilized. If the VCO 6 is to be built in the semiconductor chip, the VCO control unit 10 is necessary to absorb the characteristic variation due to the manufacturing variation. The circuit operation of the VCO control unit 10 is the same as that described in Patent Document 1, and description thereof is omitted here.

  In FIG. 5, the PLL (1) 12 and the PLL (2) 13 operate in substantially the same frequency band (fvco1≈fvco2), but have different phase comparison frequencies (fref1> fref2), and thereby each frequency synthesizer. Different performance. Hereinafter, the difference in performance between the frequency synthesizers will be described.

  Generally, when the phase comparison frequency is high, each natural frequency can be set high, so that the lockup time can be increased. Next, since the phase noise in the PLL loop band is expressed as (Equation 1), the phase noise is excellent when the phase comparison frequency is high. That is, when fref is doubled with the same fvco, the phase noise is improved by 3 dB.

(Phase noise)
= (Constant) + 20 log (fvco / fref) + 10 log (fref)
= (Constant) +20 log (fvco) -10 log (fref) (Equation 1)
The modulus prescalers 7a and 7b are divided into a fixed frequency dividing unit 14 and a modulus operating unit 15 as shown in FIG. When the frequency dividing ratio of the fixed frequency dividing unit 14 increases, the operating frequency fmod of the modulus operating unit 15 decreases. In general, if the frequency dividing ratio of the fixed frequency dividing unit 14 is increased and the operating frequency fmod of the modulus operating unit 15 is set low, the current consumption can be reduced as a whole of the modulus prescaler.

  On the other hand, in the fractional frequency division synthesizer using fractional N, when the frequency division ratio of the fixed frequency divider 14 is increased, noise generated by the fractional N becomes significant on the PLL closed loop. When the frequency division ratio of the fixed frequency divider 14 is n times with the same fvco and the same fref, the noise generated by the fractional N deteriorates as represented by (Equation 2).

(Fractional N noise degradation) = 20 log (n) (Formula 2)
On the other hand, the noise generated by the fractional N is expressed as (Equation 3), where Δf is the detuning frequency, m is the order of the fractional N, and fref is the phase comparison frequency. (Equation 3) shows that the noise generated by the fractional N has a noise peak at the frequency of fref / 2.

(Fractional N noise)
= 10 log ((2 sin (π · Δf / fref)) ^{2 (m−1)} / fref) + (constant)
... (Formula 3)
Therefore, increasing the frequency division ratio of the fixed frequency divider 14 while increasing the phase comparison frequency fref increases the peak frequency of noise generated by the fractional N and degrades the noise. This is not preferable because noise tends to be noticeable on the PLL closed loop. Therefore, since the modulus prescaler 7a of the PLL (1) 12 in which the phase comparison frequency fref is set high has to reduce the frequency division ratio of the fixed frequency divider 14, the PLL (2) in which the phase comparison frequency fref is set low. ) The current consumption is larger than that of the 13 modulus prescaler 7b. Of course, the fixed frequency divider 2a, the phase comparator 3a, the charge pump 4a, and the fractional frequency division control unit 9 of the PLL (1) 12 are also compared with the PLL (2) 13 as the phase comparison frequency increases. Current consumption increases.

  To summarize the above, the performance of the frequency synthesizer of the PLL (1) 12 and the PLL (2) 13 is expressed as shown in (Table 1) with the PLL (2) 13 as a reference.

  When multiple fractional-N fractional frequency synthesizers that require different performances are used alternately in time division, the synthesizer of each mode is optimal in all performance (phase noise, lock-up time, current consumption) However, there is a problem that the chip area is enlarged.

  As another conventional example, there is a method of using only one having the highest performance among a plurality of fractional frequency synthesizers that require different performance. This is shown in FIG.

In the case of the configuration of FIG. 7, the multimode-compatible frequency synthesizer is realized only by the PLL (1) 12 of FIG. 5. In this case, radio performance (phase noise, lockup time) required in each mode can be realized, but there is a problem that current consumption increases in all modes.
JP 2001-339301 A

  In a frequency synthesizer, reduction of power consumption and reduction of chip area are important issues. When multiple fractional-N fractional frequency synthesizers that require different performances are used alternately in a time-division manner, the conventional configuration has a problem that the chip area is enlarged or the current consumption increases in all modes. .

  An object of the present invention is to solve the above-described conventional problems and to provide a multimode-compatible frequency synthesizer that suppresses an increase in chip area while optimizing current consumption in all modes.

  The multimode-compatible frequency synthesizer of the present invention includes a voltage controlled oscillator that oscillates at a frequency according to a control voltage applied to a frequency control voltage terminal, a variable frequency divider that divides an output signal of the voltage controlled oscillator, A phase comparator that outputs a phase difference signal by phase comparison of a signal obtained from a variable frequency divider and a reference signal, a charge pump whose charge / discharge output is controlled based on an output signal of the phase comparator, A low-pass filter that averages an output signal of a charge pump and supplies the voltage controlled oscillator as the control voltage, and the variable frequency divider has a modulus prescaler capable of setting a plurality of division ratios, and an output of the modulus prescaler A programmable counter that counts the modulus prescale based on the count value of the programmable counter. Dividing ratio of La is controlled, configured such that the dividing ratio from fractional frequency division control unit is set.

  In order to solve the above problems, the multimode-compatible frequency synthesizer of the present invention has a plurality of the modulus prescalers having different configurations, and switches and uses the modulus prescaler for the same output frequency of the voltage controlled oscillator. A frequency synthesizer having different phase comparison frequencies is configured.

  According to the multimode frequency synthesizer having the above configuration, when a plurality of fractional N fractional frequency synthesizers requiring different performances are alternately used in a time division manner, the chip area is optimized while optimizing the current consumption in all modes. Can be suppressed.

  In the frequency synthesizer configured as described above, it is preferable that power supply to the non-selected modulus prescaler among the plurality of modulus prescalers is cut off.

  Further, by switching the input / output current of the charge pump or the constant of the low-pass filter simultaneously with the modulus prescaler, the closed-loop transfer function of the synthesizer can be arbitrarily controlled in frequency synthesizers having different phase comparison frequencies. It is preferable.

  Further, it is preferable that a voltage storage holding unit capable of temporarily storing and charging the input voltage of the voltage controlled oscillator is provided, and the lockup time to a specific frequency can be shortened.

  And a VCO control unit for absorbing manufacturing variations of the voltage-controlled oscillator, and a control state holding unit capable of temporarily storing the control state of the VCO control unit and giving the control state to the VCO control unit. It is preferable to be able to shorten the lock-up time.

  A mobile radio apparatus including the frequency synthesizer having any of the above configurations can be configured.

  In addition, a radio base station apparatus including the frequency synthesizer having any of the above configurations can be configured.

  Hereinafter, a multimode-compatible frequency synthesizer according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a multimode-compatible frequency synthesizer according to Embodiment 1 of the present invention. The frequency synthesizer of the present embodiment is obtained by improving the configuration of the modulus prescaler 7a in the conventional frequency synthesizer shown in FIG. Among the other components, the same components as those of the frequency synthesizer in FIG.

  The modulus prescaler 7c constituting the frequency synthesizer of the present embodiment also has the modulus prescalers 7a and 7b included in the PLL (1) 12 and the PLL (2) 13 in the conventional example shown in FIG. That is, a fixed frequency dividing portion 14a and a modulus operating portion 15a constituting the modulus prescaler 7a, and a fixed frequency dividing portion 14b and a modulus operating portion 15b constituting the modulus prescaler 7b are provided. The change-over switches 16 and 17 are inserted in the inputs and outputs of the modulus prescalers 7a and 7b, and either one is selected by the synthesizer switching signal 18.

  The synthesizer switching signal 18 is also supplied to the fixed frequency divider 2c, and the fixed frequency divider 2c changes the frequency dividing ratio accordingly, so that the phase comparison frequency fref can be switched. Further, the synthesizer switching signal 18 is also supplied to the charge pump 4c or the LPF 5c, and the input / output current of the charge pump 4c or the constant of the LPF 5c can be switched accordingly. Further, although not shown, the power supply to the non-selected one of the modulus prescalers 7a and 7b is cut off.

  When the transfer functions of the charge pump 4c and LPF 5c are Kd and F (s) and the control sensitivity of the VCO 6 is Ko, the closed-loop transfer function H (s) of the synthesizer is expressed by (Equation 4). When the oscillation frequency fvco, the phase comparison frequency fref, and the control sensitivity Ko of the VCO 6 are already determined, the closed loop transfer function H of the synthesizer is controlled by controlling the transfer functions Kd and F (s) of the charge pump 4c and the LPF 5c. (S) can be set arbitrarily.

H (s)
= Kd * F (s) * Ko / (s + Kd * F (s) * Ko * fref / fvco)
... (Formula 4)
With such a configuration having a switching function, the chip area can be designed with the same performance as compared with the conventional example of FIG. Further, compared with the conventional example of FIG. 7, the chip area is slightly increased, while the current consumption for each mode can be optimally designed.

  As described above, according to the present embodiment, when a plurality of fractional N fractional frequency division synthesizers that require different performances are used alternately in a time division manner, the synthesizers of the respective modes are set to the full performance (phase noise). , Lock-up time, current consumption) and chip area can be optimally designed.

(Embodiment 2)
FIG. 2 is a block diagram showing the configuration of the multimode-compatible frequency synthesizer according to the second embodiment of the present invention. Compared with the frequency synthesizer shown in FIG. 1, the frequency synthesizer of the present embodiment is provided with a voltage storage holding unit 19 and a control state holding unit 20 that holds the control state of the VCO control unit 10 as a new configuration. It is a feature.

  As shown in FIG. 3, the voltage storage holding unit 19 includes an A / D converter 21, a digital value holding unit 22, a D / A converter 23, and a changeover switch 24. In the voltage storage holding unit 19, the voltage of the input / output unit is converted into a digital value by the A / D converter 21 through the changeover switch 24 and stored in the digital value holding unit 22 during voltage storage. At the time of voltage charging, the digital value stored and held in the digital value holding unit 22 is converted into an analog value by the D / A converter 23 and output to the input / output unit through the changeover switch 24. During the period when the voltage storage holding unit 19 is not operating, the changeover switch 24 operates so that the input / output unit becomes high impedance.

  In the following, the circuit operation of the frequency synthesizer having the configuration of FIG. 2 will be described with reference to FIG. 4 with respect to the circuit operation of the frequency synthesizer having the configuration of FIG. The circuit operation of the frequency synthesizer when the modulus prescalers 7a and 7b in FIG. 1 or FIG. 2 are used will be described as PLL (1) and PLL (2), respectively.

  FIG. 4A shows the frequency synthesizer having the configuration shown in FIG. 1 when the frequency synthesizer performs continuous switching operation from PLL (2) → PLL (1) → PLL (2) based on the performance described in (Table 1). The circuit operation is shown. Times T1 to T5 indicate a series of operations of PLL (2) circuit startup, VCO selection adjustment operation, frequency pull-in, transmission / reception, and circuit shutdown. In this case, the output frequency of the VCO 6 is fvco (F1), and the input control voltage of the VCO 6 is V1. The same operation process is performed at times T6 to T10 and times T11 to T15. Here, at time T0 to T5 and time T11 to T15, the configuration is the same frequency synthesizer PLL (2), which operates at the same frequency.

  FIG. 4B similarly shows the circuit operation of the frequency synthesizer configured as shown in FIG. Differences from the circuit operation of the frequency synthesizer configured as shown in FIG. 1 will be described. It can be predicted before time T13 that the output frequency of VCO 6 is fvco (F1) and the input control voltage of VCO 6 is near V1 at times T11 to T15. When the frequency pull-in of the synthesizer PLL (2) is completed at time T3, the input control voltage of the VCO 6 is stored in the voltage storage holding unit 19. Before and after, the control state of the VCO control unit 10 is stored in the control state holding unit 20.

  While the frequency synthesizer PLL (1) of another configuration is operating from time T6 to T10, the voltage storage holding unit 19 and the control state holding unit 20 hold the values and the VCO 6 input control voltage and the VCO control unit. 10 so as not to affect the control state. At time T12, confirming that the output frequency of the VCO 6 is set to fvco (F1), the voltage storage holding unit 19 sets the input control voltage of the VCO 6 to V1, and the control state holding unit 20 sets the storage state to VCO. Set in the control unit 10.

  By operating as described above, the time required for the VCO selection adjustment operation at time T12 and the frequency pull-in at time T13 in FIG. 4A can be significantly reduced.

  According to the multimode-compatible frequency synthesizer of the present invention, when a plurality of fractional N fractional frequency synthesizers that require different performances are used alternately in a time division manner, the chip area is optimized while optimizing the current consumption in all modes. This is useful as a variable frequency synthesizer used in a radio base station or the like.

The block diagram which shows the structure of the multimode corresponding | compatible frequency synthesizer in Embodiment 1 of this invention. The block diagram which shows the structure of the multimode corresponding | compatible frequency synthesizer in Embodiment 2 of this invention. The block diagram which shows the structure of the voltage memory holding | maintenance part 19 in Embodiment 2 of this invention. Table showing circuit operation of each multimode frequency synthesizer in the first and second embodiments Block diagram showing the configuration of a conventional multimode frequency synthesizer Block diagram showing the internal configuration of the modulus prescaler that composes the same frequency synthesizer Block diagram showing the configuration of another conventional multimode frequency synthesizer

Explanation of symbols

1 Reference oscillator 2a, 2b, 2c Fixed frequency divider 3a, 3b, 3c Phase comparator 4a, 4b, 4c Charge pump 5a, 5b, 5c LPF (low pass filter)
6 VCO (Voltage Controlled Oscillator)
7a, 7b, 7c Modulus prescaler 8a, 8b Programmable counter 9 Fraction division control unit 10 VCO control unit 11 Changeover switch 12 PLL (1)
13 PLL (2)
14, 14a, 14b Fixed frequency dividers 15, 15a, 15b Modulus operating units 16, 17 Changeover switch 18 Synthesizer switching signal 19 Voltage storage holding unit 20 Control state holding unit 21 A / D converter 22 Digital value holding unit 23 D / A converter 24 selector switch

Claims (7)

A voltage controlled oscillator that oscillates at a frequency according to a control voltage applied to the frequency control voltage terminal;
A variable frequency divider for dividing the output signal of the voltage controlled oscillator;
A phase comparator that outputs a phase difference signal by comparing the phase of the signal obtained from the variable frequency divider and a reference signal;
A charge pump whose charge / discharge output is controlled based on an output signal of the phase comparator;
A low-pass filter that averages the output signal of the charge pump and supplies the voltage-controlled oscillator as the control voltage;
The variable frequency divider includes a modulus prescaler that can set a plurality of division ratios, and a programmable counter that counts the output of the modulus prescaler, and the division ratio of the modulus prescaler is based on the count value of the programmable counter. In a frequency synthesizer that is controlled and configured to set the frequency division ratio from a fractional frequency division control unit,
A multi-mode comprising a plurality of the modulus prescalers having different configurations, and a frequency synthesizer having a different phase comparison frequency is configured by switching and using the modulus prescaler for the same output frequency of the voltage controlled oscillator. Compatible frequency synthesizer.   The frequency synthesizer according to claim 1, wherein power supply to the modulus prescaler that is not selected among the plurality of modulus prescalers is cut off.   The closed-loop transfer function of the synthesizer can be arbitrarily controlled in a frequency synthesizer having different phase comparison frequencies by switching the input / output current of the charge pump or the constant of the low-pass filter simultaneously with the modulus prescaler. The frequency synthesizer according to 1 or 2.   4. A voltage storage holding unit capable of temporarily storing and charging the input voltage of the voltage controlled oscillator, and capable of reducing a lock-up time to a specific frequency. The described frequency synthesizer.   A VCO control unit for absorbing manufacturing variations of the voltage controlled oscillator, and a control state holding unit capable of temporarily storing the control state of the VCO control unit and giving the control state to the VCO control unit. The frequency synthesizer according to claim 1, wherein the lock-up time can be shortened.   A mobile radio apparatus comprising the frequency synthesizer according to claim 1.   A radio base station apparatus comprising the frequency synthesizer according to claim 1.

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