JP2007279902A - Memory control method, memory control device, image processor and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform high-speed processing with a minimized memory capacity in various image processors using a line memory. <P>SOLUTION: The image processor 100 supplies image data stored in a memory such as DRAM 10 or SRAM 20 to an image processing part 30 to perform predetermined image processing. The DRAM 10 is composed of a plurality of memory banks, a memory control part 50 controls reading and writing of image data to each memory. When input image data is written to the DRAM 10, the memory control part 60 writes division image data obtained by dividing the image data in predetermined units to the DRAM 10 so that each of the division image data continued in the line direction or row direction is not stored in the same memory bank. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technique for performing image processing at high speed with a small-capacity memory.

In the image processing, for example, processing such as filter processing or block processing is performed on a block composed of pixels of a plurality of rows and a plurality of columns. An image processing apparatus that performs such image processing generally includes a line memory that stores image data in the row direction. For example, in the case of an image processing apparatus that performs image processing in units of 5 × 5 pixel blocks, it is sufficient to hold four lines of image data with four line memories. A DRAM (Dynamic Random Access Memory) is often used when transferring image data to such an image processing apparatus. This is because DRAM is suitable for data transfer to a line memory because it can transfer data with consecutive addresses at high speed. In addition, since DRAM is cheaper than SRAM (Static Random Access Memory) and the like and has a relatively simple structure, it can be said that it is advantageous from the viewpoint of circuit scale and cost.
JP-A-10-162131

  By the way, in the image processing apparatus described above, each line memory does not necessarily have to hold the entire line of image data. For example, in the example described above, it is sufficient that each line memory can hold data for five pixels. However, since a DRAM is not suitable for reading a small amount of data over a plurality of lines, conventionally, it has been a general configuration that image data other than a block to be processed is also read together and stored in a line memory. It was. For this reason, the memory capacity of the line memory has to be increased, and the image processing apparatus becomes complicated and expensive. However, if the line memory is simply reduced and only the necessary image data is read from the DRAM, the read operation becomes a bottleneck and the processing speed is reduced.

  In order to eliminate such inconvenience, it is also effective to some extent to apply the technique described in Patent Document 1. However, since the technique described in Patent Document 1 can only perform continuous access in the horizontal direction (row direction) and continuous access in a specific rectangular area at high speed, the technique is low in versatility and can be used for various image processing. It is difficult to apply.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a technique for enabling high-speed processing with a small memory capacity in various image processing apparatuses using a line memory.

  In order to achieve the above-described object, the present invention executes predetermined image processing on image data via a memory having a plurality of memory banks capable of storing image data representing an array of pixels in a plurality of rows and a plurality of columns. A memory control device for supplying to the image processing apparatus, a writing means for writing the image data in the memory, a reading means for reading the image data written in the memory by the writing means, and the reading Supply means for supplying the image data read from the memory by the means in an order according to the image processing executed by the image processing apparatus, and the writing means includes a first of the input image data. Each of the divided image data of a plurality of columns obtained by dividing the row by a predetermined division unit is stored in different memory banks in which the continuous divided image data is different from each other in the memory. Each of the divided image data in a plurality of columns obtained by dividing the second row adjacent to the first row of the image data in the division unit is equivalent to the same column in the first row. The divided image data is stored in a memory bank different from the memory bank in which the divided image data is stored, and the continuous divided image data is written so as to be stored in different memory banks. Alternatively, a memory control device that continuously reads the divided image data continuous in the column direction is provided.

The present invention also provides a first memory having a plurality of memory banks capable of storing image data representing an array of pixels in a plurality of rows and a plurality of columns, and a first memory capable of storing the image data stored in the first memory. 2 memory, image processing means for performing predetermined image processing on image data stored in the second memory, first writing means for writing image data in the first memory, and the first memory First reading means for reading image data written to the first memory by writing means, and image data read from the first memory by the first reading means to the second memory A second writing means for writing, and the image data written in the second memory by the second writing means in the order according to the image processing executed by the image processing means, Second to supply Reading means, wherein the first writing means continuously divides each of the divided image data of a plurality of columns obtained by dividing the first row of the input image data by a predetermined division unit. A plurality of columns in which image data is written so as to be stored in different memory banks of the first memory, and a second row adjacent to the first row of the image data is divided by the division unit. Each of the divided image data is stored in a memory bank different from the memory bank in which the divided image data corresponding to the same column in the first row is stored, and continuous divided image data is stored in each other in the first memory. The first reading means writes the divided image data continuous in the row direction or the column direction in the image data continuously so as to be stored in different memory banks. To provide an image processing apparatus for reading the.
In this image processing apparatus, the first memory can store more data than the second memory, and the second memory can write and read data at a higher speed than the first memory. It is desirable that the configuration be capable of. Further, it is desirable that the first memory is a DRAM and the second memory is an SRAM.

According to such a memory control device and image processing device, the divided image data that are continuously read in the row direction and the column direction are stored in different memory banks. Therefore, it is possible to efficiently read image data in both the row direction and the column direction, and so-called “horizontal reading (continuous reading in the row direction)” and “vertical reading (continuous reading in the column direction)” are performed at high speed. Can be done. Further, the memory control device and the image processing device are not particularly limited in units of blocks for executing image processing, and therefore can be applied to various image processing devices having different image processing to be executed.
In the memory control device and the image processing device described above, the divided image data continuous in the row direction or the column direction is continuously read out from the image data. However, the divided image continuous in the row direction or the column direction is used. It is not always possible to read out all of the data at once. For example, two pieces of divided image data continuous in the row direction of the first row are read out continuously, and then two pieces of continuous data in the row direction of the second row are read. An operation of continuously reading the divided image data may be performed.

  Furthermore, the present invention can be provided as a memory control method for the memory control device to supply image data to the image processing device, and a program for realizing the method. That is, according to the present invention, an image in which a memory control device performs predetermined image processing on the image data using a memory having a plurality of memory banks capable of storing image data representing an array of pixels of a plurality of rows and a plurality of columns. A memory control method for supplying to a processing device, wherein each of divided image data of a plurality of columns obtained by dividing a first row of input image data by a predetermined division unit is divided continuously A first step of writing the image data so as to be stored in different memory banks of the memory, and a second row adjacent to the first row of the input image data are divided in the division unit. Each of the plurality of columns of divided image data is stored in a memory bank different from the memory bank in which the divided image data corresponding to the same column in the first row is stored, and A second step of writing so that subsequent divided image data is stored in different memory banks, and reading out the divided image data written in the memory in the first and second steps; And a third step of continuously reading out the divided image data that is continuous in a row direction or a column direction in the image data. It can also be specified as a program for realizing this method.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the embodiment described below, it is assumed that “image data” is 32-bit data per pixel input in a dot sequential format. In the image data, the upper 8 bits are data such as dummy data (hereinafter referred to as “0 data”) irrelevant to the image processing performed by the image processing apparatus, and the remaining 24 bits are R (red), G ( It is assumed that they are 8-bit color components (hereinafter referred to as “R data”, “G data”, and “B data”, respectively) for each color of green and B (blue). In the embodiment described below, it is assumed that one word is 16 bits.

[Constitution]
FIG. 1 is a block diagram schematically showing the configuration of an image processing apparatus 100 according to an embodiment of the present invention. As shown in the figure, the image processing apparatus 100 includes a DRAM 10, an SRAM 20, an image processing unit 30, an SRAM 40, a DRAM 50, and a memory control unit 60. In the figure, the arrow indicated by a broken line indicates the transfer path of the image data. Image data is input from a host device (not shown) via an input / output interface (not shown).

  The DRAMs 10 and 50 are so-called four-bank memories each having a memory cell array physically or logically divided into four. Each of the memory cells of the DRAMs 10 and 50 holds binary information by the electric charge accumulated in the capacitor. The DRAMs 10 and 50 differ only in their positions, and there is no difference in specific configuration. In the present embodiment, for convenience of explanation, it is assumed that the DRAMs 10 and 50 are SDRAMs (Synchronous DRAMs) that operate in synchronization with a clock signal, and the burst length thereof is “8 (words)”. In the following, each of the memory cell arrays physically or logically divided is referred to as “(memory) bank”, and is described as “bank 0”, “bank 1”, “bank 2”, and “bank 3”. Thus, each memory bank is distinguished.

  The SRAMs 20 and 40 are memories that hold binary information by flip-flops. The SRAMs 20 and 40 can read or write data at a higher speed than the DRAMs 10 and 50 described above, but have a smaller capacity than the DRAMs 10 and 50. Note that the SRAMs 20 and 40 differ only in their positions, and there is no difference in the specific configuration.

  The image processing unit 30 includes a plurality of line memories and an ASIC (Application Specific Integrated Circuit) for executing predetermined image processing such as filter processing and block processing. The image processing performed by the image processing unit 30 is arbitrary, and the number of line memories varies depending on the mode of image processing performed by the image processing unit 30, but in the present embodiment, the image processing unit 30 has 5 × 5 pixels. It is assumed that filter processing using image data is performed and a line memory for four lines is provided.

  The memory control unit 60 includes an LSI (Large Scale Integration) that controls operations related to reading and writing of the DRAMs 10 and 50 and the SRAMs 20 and 40 described above. The memory control unit 60 generates an address of data to be read or written by a predetermined calculation, and controls data transfer between the memories.

[Operation]
With the above configuration, the image processing apparatus 100 performs a filtering process on image data input from an external apparatus (not shown), and outputs the processed image data. Since the image data is transferred along the arrow indicated by the broken line in FIG. 1, the image data before processing is stored in the DRAM 10 and the SRAM 20, and the image data after processing is stored in the SRAM 40 and the DRAM 50. . Hereinafter, various operations executed by the image processing apparatus 100 will be specifically described.

  Note that the image processing apparatus 100 according to the present embodiment performs image processing by so-called banding. Here, banding is a method of dividing image data into predetermined rectangular areas (bands) and executing image processing for each divided area. Here, the size of the band in the row direction (hereinafter referred to as “band length”) is the same as the size of the image data in the row direction, and the size of the band in the column direction (hereinafter referred to as “band height”). It is assumed that “5 (pixel)”.

(1) Write Operation to DRAM 10 First, an operation when the memory control unit 60 of the image processing apparatus 100 writes image data to the DRAM 10 will be described. FIG. 2 is a schematic diagram of the image data shown to explain the address generated for the memory control unit 60 to write the image data to the DRAM 10. As shown in the figure, the memory control unit 60 alternately generates addresses specifying bank 0 and bank 1 for the odd-numbered data of the image data, and bank 2 and bank 3 for the even-numbered data. Addresses that specify are generated alternately. In this embodiment, since the burst length is “8”, image data for 8 words is written in one writing operation. Since the image data corresponds to 32 bits for each pixel, that is, 2 words, image data for 4 pixels is sequentially stored in bank 0 by one burst transfer, and bank 1 is immediately written in bank 0. The image data for four pixels continuous to the image data is sequentially stored. In the same manner, the image data for four pixels are sequentially stored in the bank 2 and the bank 3 as well. The specific address when the image data is stored in each memory bank is not particularly limited, but it is desirable that the sequentially stored image data be stored so as to be continuous with each other in the memory bank.

  In this way, the memory control unit 60 sequentially generates addresses from the first line of the image data, and stores the image data in the storage area specified by this address. As a result, the image data is divided every 4 pixels (that is, 8 words) and stored in the memory bank of the DRAM 10. Hereinafter, the image data configured in units corresponding to the burst length is referred to as “divided image data”. As shown in FIG. 2, the adjacent divided image data are not stored in the same memory bank in either the row direction or the column direction. The reason why the divided image data is stored in this way is to enable a read operation described later to be performed at high speed.

(2) Reading Operation from DRAM 10 Next, an operation when the memory control unit 60 of the image processing apparatus 100 reads image data stored in the DRAM 10 will be described. The memory control unit 60 reads the continuous 8 words (that is, 4 pixels) of the divided image data stored in each memory bank by one burst transfer, and this operation is performed for 5 lines of the original image data. The process of performing is one cycle, and the entire image data is read by repeating this cycle.

  FIG. 3 is a timing chart showing a read operation performed by the memory control unit 60 at this time and a conventional read operation. FIG. 4 is a diagram showing the position in the original image data of the divided image data read according to the timing chart shown in FIG. In this read operation, the CAS latency is assumed to be “2.5”. In FIG. 3, “CLK” indicates a clock signal, “Command” indicates an input command, “Address” indicates a selected address, and “Data” indicates data to be read. The arrow shown in FIG. 3A represents the memory bank switching timing. For example, the arrow shown at the sixth clock in FIG. 3A indicates that the memory bank to be selected is switched from bank 0 to bank 1. That is, before and after this switching, an operation is performed in which the memory bank selected after inputting the read command (read) for bank 0 is switched to bank 1 and the active command (ACT) for bank 1 is input.

  As shown in FIG. 3A, a command (read) for selecting the row address (ROW0) and column address (COL0) of bank 0 and reading the divided image data of bank 0 is input, and immediately thereafter. When the same operation is performed on the bank 1 after switching the memory bank, the data (10-17) stored in the bank 1 is read immediately after the data (00-07) stored in the bank 0 is read out. Can do. In the same manner, the data (20 to 27) stored in the bank 2 is read immediately after the data (10 to 17) stored in the bank 1 is read, and the data (20 to 27) stored in the bank 2 is read out. ), The data (30 to 37) stored in the bank 3 can be read out immediately after reading out. As a result, as shown in FIG. 4, the divided image data corresponding to two lines of the original image data is continuously read out.

  Then, as shown by an arrow in FIG. 5, this operation is performed by bank 0 in the first row → bank 1 in the first row → bank 2 in the second row → bank 3 in the second row → bank 0 in the third row →. → By repeating the process corresponding to the band height, such as bank 1 in the fifth row, all of the divided image data including the pixels necessary for the filter processing can be read out. As can be seen from FIG. 5, when reading the divided image data, it is possible to sequentially switch the memory banks to be read without repeatedly reading the divided image data of the same memory bank. Therefore, it is possible to efficiently read out necessary data without causing a time during which no data is read. On the other hand, as shown in FIG. 3B, when data in another row is read without switching the memory bank, the data reading is not continuous and a delay occurs. This is because when a memory cell in a different row is accessed in the same memory bank, a new active command cannot be input until a precharge command (not shown) is input. .

(3) Writing / Reading Operation to / from SRAM 20 Next, the operation when the memory control unit 60 of the image processing apparatus 100 writes the image data read from the DRAM 10 to the SRAM 20 and reads the image data will be described. First, the memory control unit 60 sequentially stores the image data in the SRAM 20 in the order read from the DRAM 10. That is, the memory control unit 60 generates an address by which the read image data is sequentially stored in the SRAM 20 by calculation.

  FIG. 6 is a schematic diagram showing data stored in the SRAM 20 at this time. In the figure, the numbers such as “00”, “01”, “02” attached to each data indicate the correspondence with the data shown in FIG. Each has a data capacity of one word. Since the image data is 32-bit data input in a dot sequential format, each data constitutes one set of “0 data and R data” or “G data and B data”. That is, data “00” and “01” constitute one pixel, and similarly, data of two consecutive words constitute one pixel.

  The image processing unit 30 performs image processing for each color component of each color. That is, the processing for this block is performed by performing filtering processing three times using 5 × 5 pixels for each of R data, G data, and B data. Therefore, the memory control unit 60 reads data from the SRAM 20 to sequentially supply data for 5 × 5 pixels to the image processing unit 30 for each color component of each color.

  FIG. 7 is a diagram for explaining a procedure by which the memory control unit 60 reads data from the SRAM 20. 7A, 7B, and 7C show procedures for reading R data, G data, and B data, respectively. As illustrated in FIG. 7A, when reading R data, the memory control unit 60 reads data corresponding to the R data of the data “00”. That is, at this time, the memory control unit 60 generates an address to read out the lower 8 bits of the data “00”. Then, the memory control unit 60 designates an address obtained by adding 24 bits to the address designated for reading immediately before, so that the R data corresponding to the next adjacent pixel, that is, the lower 8 bits of the data “02” Is read. The memory control unit 60 performs the same operation on the R data for five pixels corresponding to the first row, and reads the R data for five pixels. Thereafter, the memory control unit 60 reads the R data in the second to fifth rows in the same manner, and finally supplies the R data for 5 × 5 pixels to the image processing unit 30. Then, the image processing unit 30 executes the filtering process by storing the R data in the line memory.

  Subsequently, the memory control unit 60 executes an operation of reading G data and B data from the SRAM 20. These operations are also performed in substantially the same procedure as the R data reading operation described above. However, as shown in FIGS. 7 (b) and 7 (c), the addresses designated for data reading are naturally different. When reading the G data, the memory control unit 60 designates an address for reading the upper 8 bits of data “01”, “03”, “05”, etc., and when reading the B data, the data “01”, “ Designates an address for reading out the lower 8 bits such as “03” and “05”. Then, the G data and B data for 5 × 5 pixels read out in this way are supplied to the image processing unit 30.

(4) Operation after Execution of Image Processing Next, the handling of image data after the image processing unit 30 performs the filter processing will be described. Data output from the image processing unit 30 is written into the SRAM 40 and then written into the DRAM 50. At this time, the read / write operation performed by the memory control unit 60 may be determined according to the subsequent processing performed after the image data is output from the image processing apparatus 100. For example, if the image data is output in the same format as when it is input to the image processing apparatus 100, the image data after filtering is stored in the DRAM 10 by performing the operations performed in the DRAM 10 and the SRAM 20 in the reverse procedure. It is possible to store the same in the DRAM 50 in the same format. However, the read / write operation of the memory control unit 60 is not particularly limited to the above-described example, and may be any as long as it matches the output mode from the image processing apparatus 100.

[effect]
As described above, according to the image processing apparatus 100 of the present embodiment, the divided image data is written by writing the divided image data so that none of the adjacent divided image data is stored in the same memory bank. It is possible to read continuously. As a result, the image processing apparatus 100 can efficiently supply data to the image processing unit 30. Further, according to the image processing apparatus 100, even when reading out the entire image data of a certain row, it is possible to read out sequentially while switching the two memory banks, so that so-called horizontal reading can be performed at high speed. is there. Furthermore, according to this image processing apparatus 100, it is possible to read out a plurality of lines of image data at high speed without reading out the entire lines. Therefore, according to this image processing apparatus 100, so-called vertical reading can be performed at high speed even with a relatively inexpensive configuration mainly using a DRAM.

  Further, the image processing apparatus 100 according to the present embodiment can be applied to various image processing by changing the reading operation from the DRAM 10. For example, if the process performed by the image processing unit 30 is a filter process using image data of 3 × 3 pixels, the divided image data for three rows are continuously displayed in the column direction as indicated by arrows in FIG. Read it out. For example, if the processing performed by the image processing unit 30 is block processing using 8 × 8 pixel image data, the original image data continues in the row direction as indicated by arrows in FIG. 9. The operation of continuously reading the two divided image data may be performed for eight rows.

[Modification]
In the above description, one preferred embodiment of the present invention has been illustrated, but the present invention is not limited to the above-described embodiment, and can be implemented in various other modes. In the present invention, for example, the following modifications can be applied to the above-described embodiment. These modifications can be combined as appropriate.

  In the above-described embodiment, the word length, burst length, and the like are limited for the sake of convenience of explanation. It is possible to use. Also, the image data is not limited to so-called RGB data of 32 bits, and may be 24-bit RGB data not including the above-described 0 data, or image data consisting of only the luminance component (Y), or luminance component and color difference. It may be image data composed of components (Cb, Cr). Further, the image data is not limited to the dot sequential format but may be a frame sequential format.

  In the above-described embodiment, the DRAMs 10 and 50 are synchronous DRAMs (SDRAMs), but asynchronous DRAMs can also be used. When an asynchronous DRAM is used, a function corresponding to the above-described command can be realized by a combination of logic levels of control signals.

  In the above-described embodiment, the SRAM 20 is provided between the DRAM 10 and the image processing unit 30, but the present invention may be applied to a configuration in which the SRAM 20 is not provided. That is, depending on the format of the image data and the specifications of each part of the image processing apparatus 100, the image data read from the DRAM 10 can be supplied to the image processing unit 30 in the read order. For example, if the image processing unit is configured to be able to expand the supplied image data and select necessary data, a memory corresponding to the SRAM 20 is not necessary.

  In the above-described embodiment, the DRAM 10 has a four-bank configuration. However, the number of memory banks may be any number as long as it is two or more. For example, if the DRAM has a two-bank configuration of bank 0 and bank 1, as shown in FIG. 10, continuous divided image data is stored in different memory banks, and adjacent to the original image data. By writing the image data so that the divided image data corresponding to the same column in different rows is stored in different memory banks, the original image data can be continuously read out in both the row direction and the column direction. Thus, a set of divided image data over a plurality of lines can be read at high speed.

  In the above-described embodiment, it has been described that the memory control unit 60 is configured by an LSI or the like. However, the memory control unit can be configured by a program that realizes a function corresponding to the memory control unit 60. . That is, the present invention can be specified not only as the above-described image processing device and memory control unit (memory control device) but also as a program that realizes the function of the memory control unit. Similarly, the present invention can also be specified as a memory control method performed by the memory control unit.

1 is a block diagram illustrating a configuration of an image processing apparatus according to an embodiment of the present invention. It is a figure for demonstrating the address produced | generated in order that the memory control part of an image processing apparatus may write image data in DRAM. 5 is a timing chart showing a read operation performed by a memory control unit of the image processing apparatus and a conventional read operation. It is the figure which showed the position in the original image data of the divided image data read according to the timing chart shown to Fig.3 (a). It is a figure for demonstrating the order in which an image processing apparatus reads division image data. It is the schematic diagram which showed the data memorize | stored in SRAM of an image processing apparatus. It is a figure for demonstrating the procedure in which the memory control part of an image processing apparatus reads data from SRAM. It is the figure which showed the modification of the read-out operation | movement which an image processing apparatus performs. It is the figure which showed the modification of the read-out operation | movement which an image processing apparatus performs. It is the figure which showed the modification of the write-in operation which an image processing apparatus performs.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Image processing apparatus 10, 50 ... DRAM, 20, 40 ... SRAM, 30 ... Image processing part, 60 ... Memory control part

Claims (9)

A memory control method for using a memory having a plurality of memory banks capable of storing image data representing an array of pixels in a plurality of rows and a plurality of columns and supplying the image data to an image processing apparatus that performs predetermined image processing Because
Each of a plurality of columns of divided image data obtained by dividing the first row of the input image data by a predetermined division unit is stored in different memory banks of the memory. A first step of writing,
Each of divided image data of a plurality of columns obtained by dividing a second row adjacent to the first row of the input image data in the division unit is a divided image corresponding to the same column in the first row. A second step of writing such that the data is stored in a memory bank different from the memory bank in which the data is stored, and the successive divided image data are stored in different memory banks, respectively;
Reading out the divided image data written in the memory in the first and second steps and supplying the divided image data in an order according to the image processing executed by the image processing apparatus, wherein And a third step of continuously reading out the divided image data continuous in the column direction. A memory control device for supplying image data to an image processing device that executes predetermined image processing via a memory having a plurality of memory banks capable of storing image data representing an array of pixels in a plurality of rows and columns. There,
Writing means for writing the image data into the memory;
Reading means for reading image data written in the memory by the writing means;
Supply means for supplying image data read from the memory by the reading means in an order according to image processing executed by the image processing apparatus;
The writing means includes
Each of a plurality of columns of divided image data obtained by dividing the first row of the input image data by a predetermined division unit is stored in different memory banks of the memory. Each of the plurality of columns of divided image data obtained by dividing the second row adjacent to the first row of the image data in the division unit corresponds to the same column in the first row. Write so that the divided image data is stored in a different memory bank from the memory bank in which the divided image data is stored, and the continuous divided image data is stored in different memory banks.
The reading means includes
The memory control device, wherein the divided image data continuous in the row direction or the column direction in the image data is continuously read out. A first memory having a plurality of memory banks capable of storing image data representing an array of pixels in a plurality of rows and columns;
A second memory capable of storing image data stored in the first memory;
Image processing means for performing predetermined image processing on the image data stored in the second memory;
First writing means for writing image data into the first memory;
First reading means for reading image data written in the first memory by the first writing means;
Second writing means for writing image data read from the first memory by the first reading means to the second memory;
Second reading means for reading the image data written in the second memory by the second writing means in an order according to the image processing executed by the image processing means and supplying the image processing means to the image processing means; Prepared,
The first writing means includes:
Each of the divided image data of a plurality of columns obtained by dividing the first row of the input image data by a predetermined division unit is divided into different memory banks in which the continuous divided image data is different from each other in the first memory. Each of the plurality of columns of divided image data obtained by dividing the second row adjacent to the first row of the image data in the division unit is written in the same row in the first row. Is stored in a memory bank different from the memory bank in which the divided image data is stored, and continuous divided image data is written to be stored in different memory banks of the first memory,
The first reading means includes:
An image processing apparatus, wherein the divided image data continuous in a row direction or a column direction in the image data is continuously read out. The first memory is a memory having four or more memory banks,
The said 1st writing means makes the memory bank which writes the division | segmentation image data of the said 1st line different from the memory bank which writes the division | segmentation image data of the said 2nd line mutually. The image processing apparatus described. The first memory can store more data than the second memory;
The image processing apparatus according to claim 3, wherein the second memory is capable of writing and reading data at a higher speed than the first memory.   The image processing apparatus according to claim 3, wherein the first memory is a DRAM.   The image processing apparatus according to claim 6, wherein the division unit corresponds to a burst length of the first memory.   The image processing apparatus according to claim 3, wherein the second memory is an SRAM. A program for a computer to supply image data to an image processing apparatus that executes predetermined image processing using a memory having a plurality of memory banks capable of storing image data representing an array of pixels in a plurality of rows and columns. Because
In the computer,
Each of a plurality of columns of divided image data obtained by dividing the first row of the input image data by a predetermined division unit is stored in different memory banks of the memory. A first function to write,
Each of divided image data of a plurality of columns obtained by dividing a second row adjacent to the first row of the input image data in the division unit is a divided image corresponding to the same column in the first row. A second function for writing data such that data is stored in a memory bank different from the memory bank in which the data is stored, and continuous divided image data is stored in different memory banks,
A function of reading the divided image data written in the memory by the first and second functions and supplying the divided image data in an order corresponding to the image processing executed by the image processing device, wherein the image data includes a row direction or A program for realizing the third function of continuously reading the divided image data continuous in the column direction.

Images