JP2007273872A - Design method of semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology of remarkably reducing dispersion in signal delay times without changing the delay time while suppressing increase in a gate cell size. <P>SOLUTION: In a flip-flop 2 being one of gate cells provided to an output circuit or the like, only sizes of a gate length and a gate width of MOS transistors configuring inverters 6, 9, 12 serving as input output sections of the flip-flop 2 as principal causes to dispersion in the signal delay time are selected greater than those of transistors of a standard gate cell, thereby considerably reducing the dispersion in the delay time without changing delay characteristic. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a design technique of a semiconductor integrated circuit device, and more particularly to a technique effective for reducing delay time variation in a gate cell.

  As the scale of logic circuits in a semiconductor integrated circuit device increases, a technique for reducing variations in signal delay time among functional modules becomes important.

  For example, in a gate cell such as a flip-flop / latch or an AND circuit constituting an output circuit, variation in delay time is reduced by increasing the gate width of a MOS (Metal Oxide Semiconductor) transistor constituting a drive unit in the output circuit. ing.

Further, as a technique for reducing variations in the electrical characteristics of standard gate cells in this type of semiconductor integrated circuit device, at least one of transistors adjacent to a transistor having a different gate length from other transistors is always turned off. This suppresses variations in characteristics of basic cells (see Patent Document 1), and a transistor in at least one basic cell of a plurality of basic cells has a different gate length from transistors in other basic cells (patent) References 2 and 3).
JP 2006-5103 A Japanese Patent Laid-Open No. 11-220028 JP-A-10-135431

  However, the present inventors have found that there are the following problems in the technique for reducing the delay time variation of the signal in the gate cell as described above.

  That is, when the gate width of the MOS transistor is increased, the gate cell size is increased. For example, in a gate cell composed of a large number of logic circuits such as flip-flops, the increase in the gate size becomes more remarkable. There is a problem that the layout area of the semiconductor chip becomes large.

  In addition, in the case of a gate cell or the like, the cell size is also determined according to the driving capability (load capacity). In the case of a small cell size, there is a limit in increasing the gate width of the MOS transistor, which is sufficient. There is a possibility that the delay time variation cannot be reduced.

  As a result, there is a risk that the yield of the semiconductor integrated circuit may be lowered or the reliability may be lowered.

  An object of the present invention is to provide a technique capable of significantly reducing variations in signal delay time without changing the delay time while suppressing an increase in cell size in a gate cell.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A method for designing a semiconductor integrated circuit device according to the present invention includes: a gate length and a gate width of a transistor that constitutes a driver of an input unit in a gate cell and a driver transistor that constitutes a driver of an output unit; It is larger than the transistor that does not become.

  Moreover, the outline | summary of the other invention of this application is shown briefly.

  The semiconductor integrated circuit device design method according to the present invention reduces variations in delay time by increasing the gate length and gate width of the driver transistor.

  Also, the designing method of the semiconductor integrated circuit device according to the present invention is designed so that the gate length and the gate width of the driver transistor are respectively set to be substantially the same as the ratio of the gate length and the gate width of the transistor that does not become the driver transistor. Is.

  In the semiconductor integrated circuit device design method according to the present invention, the driver transistor is composed of an element having a large fanout or a long signal drive distance and a large load capacity.

  In the semiconductor integrated circuit device design method according to the present invention, the gate of the driver transistor is designed such that a plurality of gates each having a larger gate length and gate width are connected in parallel.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) The variation in delay time can be greatly reduced without changing the delay time of the gate cell.

  (2) Further, the increase in gate cell size can be made small.

  (3) According to the above (1) and (2), the reliability can be greatly improved while preventing the semiconductor integrated circuit device from being enlarged.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is an explanatory diagram showing a configuration example of an output circuit provided in a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 shows a logical configuration in a flip-flop provided in the output circuit of FIG. FIG. 3 is a circuit diagram showing a logical configuration of an AND circuit provided in the output circuit of FIG. 1, FIG. 4 is an explanatory diagram showing variation dependence in MOS transistors, and FIG. FIG. 6 is a layout diagram showing an example of a transistor constituting an inverter in a standard gate cell, and FIG. 7 is a diagram showing a technique for reducing variation in signal delay time in an inverter serving as an output unit of the AND circuit 3. FIG. 8 is a layout diagram showing an example of a transistor constituting the inverter of the AND circuit of FIG. 3, and FIG. 8 is a diagram showing another example of the transistor constituting the inverter of the AND circuit of FIG. FIG. 9 is a layout diagram illustrating an example of a transistor in the inverter provided in the flip-flop 2 in FIG. 2, FIG. 10 is a cross-sectional view taken along line AA ′ of FIG. 9, and FIG. BB ′ sectional view of the transistor Tp, FIG. 12 is a flowchart showing a design example in the gate cell according to the embodiment of the present invention.

  In the present embodiment, the output circuit 1 is a circuit cell that is provided in a functional block or the like provided in a semiconductor integrated circuit device and includes a plurality of gate cells. As shown in FIG. 1, the output circuit 1 includes gate cells such as flip-flops 2 and 3, an inverter 4, and an AND circuit 5.

  The clock terminals clk of the flip-flops 2 and 3 are connected so that a clock signal is input, and the data output terminal q of the flip-flop 2 is connected to the input section of the inverter 4. Further, one input part of the AND circuit 5 is connected to the output part of the inverter 4.

  In addition, various logics are provided in the preceding stage of the data input terminal d of the flip-flop 2, between the output unit of the AND circuit 5 and the data input terminal d of the flip-flop 3, and in the subsequent stage of the data output terminal q of the flip-flop 3. A cell (gate cell) is connected.

  FIG. 2 is a circuit diagram showing a logical configuration of the flip-flop 2 provided in the output circuit 1.

  The flip-flop 2 includes inverters 6 to 13 and switch circuits 14 and 15. The output part of the inverter 6 is connected to the input part of the switch circuit 14. The input part of the inverter 6 becomes the data input terminal d of the flip-flop 2. An input part of the inverter 7 and an output part of the inverter 10 are respectively connected to the output part of the switch circuit 14.

  The input part of the switch circuit 15 is connected to the output part of the inverter 7 and the input part of the inverter 10, and the input part of the inverter 8 and the output part of the inverter 11 are connected to the output part of the switch circuit 15. Each is connected.

  The switch circuits 14 and 15 have a configuration in which transistors composed of a P-channel MOS and an N-channel MOS are connected in parallel.

  The input unit of the inverter 9 is connected to the output unit of the inverter 8 and the input unit of the inverter 11, and the output unit of the inverter 9 serves as the data output terminal q of the flip-flop 2. The input part of the inverter 12 is connected so that the clock signal CLK is inputted, and the input part of the inverter 12 becomes the clock terminal clk.

  The output section of the inverter 12 includes an input section of the inverter 13, one control terminal of the inverter 10, the other control terminal of the inverter 11, a gate terminal (control terminal) of an N-channel MOS transistor constituting the switch circuit 14, and the switch circuit 15. Each of the P channel MOS transistors is connected to a gate terminal (control terminal), and an inverted signal ckb of the clock signal CLK is supplied to each of the control terminals.

  The output part of the inverter 13 includes the other control terminal of the inverter 10, one control terminal of the inverter 11, the gate terminal (control terminal) of the P-channel MOS transistor constituting the switch circuit 14, and the N-channel MOS transistor constituting the switch circuit 15. The clock signal ck obtained by inverting the inverted signal ckb by the inverter 13 is supplied to each of the control terminals.

  FIG. 3 is a circuit diagram showing a logical configuration of the AND circuit 5 provided in the output circuit 1.

  The logical product circuit 5 includes a negative logical product circuit 16 and an inverter 17 as shown in the figure. The output part of the NAND circuit 16 is connected to the input part of the inverter 17, and the output part of the inverter 17 becomes the output part of the AND circuit 5.

  In the case of the output circuit 1 shown in FIG. 1, the circuits most caused by the variation in signal delay time are the inverters 6, 9, 12, and 17 constituting the input / output unit shown in FIG. 2 and FIG. 3.

  By optimizing the gate length and gate width size of the MOS transistors (driver transistors) constituting the inverters 9 and 17, it is possible to reduce variations in signal delay time without changing the delay characteristics.

  Further, by optimizing the gate length and gate width size of the MOS transistors (driver transistors) constituting the inverters 6 and 12, the effects such as process variations and transistor threshold voltage variations are relatively reduced. can do.

  FIG. 4 is an explanatory diagram showing variation dependency in the MOS transistor.

  In FIG. 4, the horizontal axis indicates the gate length / gate width of the transistor, and the vertical axis indicates the variation of the drain-source current Ids. On the horizontal axis, the gate length / gate width increases toward the left.

  As shown in the figure, the variation of the drain-source current Ids decreases in proportion to the increase in the gate length / gate width of the transistor.

  FIG. 5 is an explanatory diagram showing a technique for reducing variations in signal delay time in the inverter 17 serving as the output unit of the AND circuit 5 (FIG. 3).

  In FIG. 5, the solid line shows the actual average of the delay time, the dotted line shows the delay time variation of the inverter in which the gate length / gate width of the transistor is increased, and the alternate long and short dash line shows the gate length of the transistor. / This shows variation in delay time of an inverter configured as a standard cell without increasing the gate width.

  As shown in the figure, by increasing the gate length / gate width of the transistors constituting the inverter, it is possible to reduce the variation in delay time regardless of the driving force of the inverter. In addition, as shown in the figure, the delay time variation reduction is more effective when the drive distance is longer (the load capacity is larger), and the capacity variation of the load capacity is larger as the inverter has a smaller driving capacity. The effect is getting bigger.

  From this, it can be seen that a reduction in variation in delay time in the logical path can be achieved by increasing the gate length / gate width of the transistors constituting the inverter 17 of the output unit.

  6 to 8 are explanatory diagrams showing an example when the inverter 17 of the AND circuit 5 is laid out on a semiconductor chip.

  FIG. 6 shows a layout of transistors Tp and Tn constituting a general inverter in a standard gate cell. FIG. 7 shows a layout when the gate length / gate width of the transistors (driver transistors) Tp1 and Tn1 constituting the inverter 17 are made larger than the transistors Tp and Tn of FIG.

  FIG. 8 shows a layout when the gate length / gate width of the transistors (driver transistors) Tp2 and Tn2 are made larger than those of the transistors Tp1 and Tn1 of FIG. .

  As described above, the inverter 17 has a configuration in which a P-channel MOS transistor and an N-channel MOS transistor are connected in series between the power supply voltage VDD and the reference potential VSS.

  The gate G of these P-channel MOS transistor and N-channel MOS transistor becomes the input part In of the inverter 17, and the connection part of the P-channel MOS transistor and the N-channel MOS transistor becomes the output part OUT of the inverter 17.

  In FIG. 6, a P-channel MOS transistor Tp is laid out above, and an N-channel MOS transistor Tn is laid out below. In the transistor Tp, the source S to which the power supply voltage VDD is supplied is laid out on the left side, and the drain D connected to the drain D of the transistor Tn is laid out on the right side.

  In the transistor Tn, the source S connected to the reference potential VSS is laid out on the left side, and the drain D connected to the drain D of the transistor Tp is laid out on the right side. A gate G is laid out at the center of the transistors Tp and Tn.

  Similarly, in FIG. 7, a P-channel MOS transistor Tp1 is laid out above, and an N-channel MOS transistor Tn1 is laid out below. In the transistor Tp1, the source S to which the power supply voltage VDD is supplied is laid out on the left side, and the drain D connected to the drain D of the transistor Tn1 is laid out on the right side.

  In the transistor Tn1, a source to which the reference potential VSS is connected is laid out on the left side, and a drain D connected to the drain D of the transistor Tp1 is laid out on the right side. A gate G is laid out at the center of the transistors Tp1 and Tn1.

  In FIG. 8, a P-channel MOS transistor Tp2 is laid out above, an N-channel MOS transistor Tn2 is laid out below, and the power supply voltage VDD is connected to the source S of the transistor Tp2, and the reference potential VSS is connected to the source S of the transistor Tn2. This is the same as in FIG. 7, except that two gates G are formed at the center of the transistors Tp2 and Tn2. (In FIG. 8, the drain D is between two gates, and both ends (left and right) are sources S (VDD or VSS connection)).

  The transistors Tp1 and Tn1 in FIG. 7 have the same size of the gate G (gate length and gate width) while maintaining a constant ratio of the gate length L: gate width W to that of the transistors Tp and Tn in FIG. The transistors Tp2 and Tn2 in FIG. 8 are connected in parallel with the ratio of gate length L: gate width W being constant and the number of gate stages being two.

  Thus, as shown in FIG. 7, the gate length / gate width are set to be constant while maintaining the ratio of the gate length L: gate width W of the transistors Tp1, Tn1, as compared to the gate G of the transistors Tp, Tn of FIG. By increasing the value, it is possible to significantly reduce the delay time variation of the signal without changing the delay characteristic. Further, since only the gate length and the gate width of the transistor effective for reducing the variation in signal delay time are increased, the manufacturability is also facilitated.

  Furthermore, as shown in FIG. 8, the variation in the delay time of the signal in the AND circuit 5 can be greatly reduced by providing the gates G of the transistors Tp2 and Tn2 in two stages.

  6 to 8, the effect of reducing variation in delay time increases in the order of FIG. 8, FIG. 7, and FIG.

  FIG. 9 is an explanatory diagram showing a layout of transistors in the inverters 6 to 13 provided in the flip-flop 2.

  As described above, the gate lengths / gate widths of the transistors Tp3 and Tn3 constituting the inverters 6, 9, and 12 constituting the input / output unit caused by the variation in the signal delay time are the largest (the standard gate cell transistors and the gates). The length: gate ratio is the same), and the other inverters 7, 8, 10, 11, 13 are formed to have the gate length / gate width of the standard gate cell transistor, respectively.

  9, the layout of transistors Tp3 and Tn3 in inverters 6, 9, and 12 is shown on the right side, and the layout of transistors Tp4 and Tn4 in inverters 7, 8, 10, 11, and 13 is shown on the left side.

  9, similarly to FIGS. 7 and 8, a P-channel MOS transistor Tp3 (, Tp4) is laid out above, and an N-channel MOS transistor Tn3 (, Tn4) is laid out below. Yes.

  In the transistor Tp3 (, Tp4), the source S to which the power supply voltage VDD is supplied is laid out on the left side, and the drain D connected to the drain D of the transistor Tn3 (, Tn4) is laid out on the right side. .

  In the transistor Tn3 (, Tn4), the source S connected to the reference potential VSS is laid out on the left side, and the drain D connected to the drain D of the transistor Tp3 (, Tp4) is laid out on the right side. . A gate G is laid out at the center of the transistors Tp3 (, Tp4) and Tn3 (, Tn4).

  Also in this case, the gate length / gate width size of the transistors Tp3, Tn3 constituting the inverters 6, 9, 12 serving as the drivers of the input / output units of the flip-flop 2 is set to the inverters 7, 8, By making the transistors 10, 11, and 13 larger than the transistors Tp4 and Tn4, variations in signal delay time can be reduced without changing the delay characteristics.

  Also here, the gate length of the transistors Tp3, Tn3 constituting the inverters 6, 9, 12 and the transistors Tp4, Tn4 constituting the inverters 7, 8, 10, 11, 13 that do not serve as the drivers of the input / output units: The ratio is the same.

  Thus, by increasing the gate length / gate width of only the driver of the input / output unit constituting the gate cell, for example, the larger and more complex gate cell such as the flip-flop 2, the larger the gate size becomes. The increase can be negligible.

  10 is a cross-sectional view taken along the line A-A ′ of the transistor Tp4 in FIG. 9, and FIG. 11 is a cross-sectional view taken along the line B-B ′ in the transistor Tp3 in FIG. 9.

  In FIG. 10, an N-WELL 19 is formed on a semiconductor substrate 18, and P-type semiconductor regions 20 and 21 that function as a source / drain are formed on the left and right sides of the N-WELL 19, respectively.

  An insulating film 22 made of, for example, cobalt silicide is formed above the P-type semiconductor regions 20 and 21, and a gate 24 is formed above the N-WELL 19 via an insulating film 23 such as silicon oxide. Has been.

  Insulating films 25 and 26 such as silicon oxide are formed on the top and side surfaces of the gate 24. An N-type semiconductor region 27 that functions as a Halo region is formed below the vicinity of the gate 24 in the N-WELL 19.

  In FIG. 11, the configuration is the same as in FIG. 10, and an N-WELL 29 is formed on the semiconductor substrate 28, and P-type semiconductor regions 30 functioning as source / drain are formed on the left and right sides of the N-WELL 29. , 31 are formed.

  An insulating film 32 is formed above the P-type semiconductor regions 30 and 31, and a gate 34 is formed above the N-WELL 29 via an insulating film 33. Here, the difference from FIG. 10 is that the gate length of the gate 34 is larger than that of the gate 24 (FIG. 10).

  Insulating films 35 and 36 such as silicon oxide are formed on the upper and side surfaces of the gate 34. An N-type semiconductor region 37 that functions as a Halo region is formed below the vicinity of the gate 34 in the N-WELL 29.

  FIG. 12 is a flowchart showing a design example in a gate cell such as a flip-flop.

  First, logic design is performed using a high-level programming language such as C language (step S101), and then logic synthesis is performed in which the logic designed program is developed on the gate (step S102).

  Thereafter, logic verification is performed to verify the operation of the logically synthesized logical path (step S103). If the logic verification is normal, layout design is performed for layout on the semiconductor chip (step S104), and then timing verification is performed (step S105). If the timing verification is NG, the process returns to step S104 to reset the gate length / gate width of the transistor.

  In the layout design in step S104, a primitive library and a variation reduction library are prepared as libraries. The primitive library is a library that stores standard gate cell design data.

  The reduction library is a library in which design data of a cell (for example, an inverter serving as a driver that constitutes the input / output unit of the gate cell) effective in reducing variation in signal delay time of the logic path in the gate cell is stored.

  Then, the layout design is performed by increasing the gate length and the gate width of the cell, which are effective for reducing the variation in the signal delay time of the logic path in the gate cell, using the reduction library.

  In this way, by performing cell layout design that is effective in reducing variation in signal delay time of the logic path in the gate cell using the reduction library, variation in signal delay time of the logic path is reduced, so timing verification is easy. Thus, the number of correction man-hours can be reduced.

  Thus, according to the present embodiment, the gate size and the gate width of the transistors constituting the driver of the input / output unit constituting the gate cell are made larger than those of the standard cell transistors, respectively. Variation of the signal delay time of the logical path can be reduced without significantly increasing.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is suitable for a design technique in a semiconductor integrated circuit device configured using gate cells.

It is explanatory drawing which shows the structural example of the output circuit provided in the semiconductor integrated circuit device by one embodiment of this invention. FIG. 2 is a circuit diagram showing a logical configuration of a flip-flop provided in the output circuit of FIG. 1. FIG. 2 is a circuit diagram illustrating a logical configuration of an AND circuit provided in the output circuit of FIG. 1. It is explanatory drawing which showed the dispersion | variation dependence in a MOS transistor. It is explanatory drawing which showed the reduction technique of the signal delay time variation in the inverter used as the output part of the AND circuit of FIG. It is a layout diagram showing an example of a transistor constituting an inverter in a standard gate cell. FIG. 4 is a layout diagram illustrating an example of a transistor constituting an inverter of the AND circuit in FIG. 3. FIG. 4 is a layout diagram illustrating another example of a transistor that constitutes an inverter of the AND circuit of FIG. 3. FIG. 3 is a layout diagram illustrating an example of a transistor in an inverter provided in the flip-flop 2 of FIG. 2. FIG. 10 is an A-A ′ cross-sectional view of the transistor of FIG. 9. FIG. 10 is a B-B ′ sectional view of the transistor Tp of FIG. 9. It is a flowchart which shows the example of a design in the gate cell by one embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Output circuit 2, 3 Flip-flop 4 Inverter 5 AND circuit 6-13 Inverter 14, 15 Switch circuit 16 Negative AND circuit 17 Inverter 18 Semiconductor substrate 19 N-WELL
20, 21 P-type semiconductor regions 22, 23 Insulating film 24 Gates 25, 26 Insulating film 27 N-type semiconductor region 28 Semiconductor substrate 29 N-WELL
30, 31 P-type semiconductor regions 32, 33 Insulating film 34 Gates 35, 36 Insulating film 37 N-type semiconductor regions Tp, Tn transistors Tp1, Tn1 transistors (driver transistors)
Tp2, Tn2 transistors (driver transistors)
Tp3, Tn3 transistor (driver transistor)
Tp4, Tn4 transistor

Claims (5)

  A driving capability of a transistor that constitutes a driver of an input unit in a gate cell and a driver transistor that constitutes a driver of an output unit is made larger than a transistor that does not become a driver transistor in the gate cell. Design method. The method for designing a semiconductor integrated circuit device according to claim 1,
The driver transistor is
A design method of a semiconductor integrated circuit device, wherein variation in delay time is reduced by increasing a gate length and a gate width of the driver transistor. The method of designing a semiconductor integrated circuit device according to claim 2,
The driver transistor is
A design method for a semiconductor integrated circuit device, wherein a gate length and a gate width are designed to be substantially the same as a ratio between a gate length and a gate width of a transistor which does not become a driver transistor. In the design method of the semiconductor integrated circuit device according to any one of claims 1 to 3,
The driver transistor is
A design method of a semiconductor integrated circuit device, wherein the device has a large fanout or a long signal drive distance and a large load capacity. The method of designing a semiconductor integrated circuit device according to claim 1 or 4,
The driver transistor is
A method for designing a semiconductor integrated circuit device, comprising: a plurality of gates each having a larger gate length and gate width of the driver transistor connected in parallel.

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