JP2007272679A - Ladder program optimization apparatus and optimization program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ladder program optimization apparatus that can automatically optimize created and edited ladder programs and can extend the range of optimization. <P>SOLUTION: The ladder program optimization apparatus has a program optimization means 402 for replacing device expressions of a plurality of circuit blocks having the same instruction configuration and device type and different device numbers in a program analyzed by a ladder program analysis means 401, to handle them as a common subexpression, and checking whether the replaced program has a reduced program size and maintains processing equivalence even after the replacement. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a ladder program optimizing device and an optimizing program for optimizing a ladder program used for a programmable controller, for example.

  Programmable controllers are widely used from small-scale machine control to large-scale production facility control. The programmable controller is connected to input devices such as various sensors and switches and output devices such as motors and electromagnetic valves. In a large-scale production facility, the number of input devices and output devices is enormous.

  The programmable controller expresses the connection between the input device and the output device with a ladder program. This ladder program is created by modularizing a part of the ladder program that is input from the program development environment by the designer or already written in the programmable controller.

When a new ladder program is created, a ladder program for controlling a small machine can be created from the beginning using a program development environment. However, in a large-scale production facility, the number of input devices and output devices becomes enormous, and the ladder program that expresses these connections becomes complicated, so the method of inputting from the beginning is inefficient. In such a case, a program is created by combining modular ladder programs created in the past.
However, in the method of combining modularized ladder programs, the creation of the program is made more efficient, but since it includes logic duplication and redundant data transfer, it becomes a ladder program with a large program size.

  In addition, a ladder program that is easy to read by humans has a large size because of duplication of logic and redundancy. For the purpose of reducing the program size, it is also possible to write a program with awareness of program optimization. However, it is possible to develop a program in a shorter time by creating a program without being aware of optimization. In addition, a program having no logical redundancy has high execution efficiency, but it takes time to decode the processing contents, and the efficiency of debugging and maintenance work is reduced. Thus, if priority is given to the efficiency of program development and maintenance, the size of the ladder program increases.

  Furthermore, in recent years, not only the control of equipment but also the processing of data related to production are performed on the programmable controller. Since a ladder program for data processing is required in addition to a ladder program related to device control, the size of the ladder program is increased.

  As the program size increases, there is a problem that the execution time becomes longer as the processing amount increases and the program size does not fit in the program capacity of the programmable controller. For the purpose of shortening the program processing time and program size, it is possible to visually check the program and proceed with replacement with a smaller program description. However, it takes a lot of time and effort to find a part that can be optimized from a program with tens of thousands of lines, and to rewrite it by reducing the size by completely equivalent processing to the original program. .

In order to solve such a problem, a method has been proposed in which a ladder program is optimized by automatically removing logic duplication and collecting common processes. For example, Patent Document 1 discloses the integration of overlapping logic, partial block replacement, and subroutine processing.
Partial block replacement is a process of detecting a common part of a ladder program, substituting the calculation result of the partial block into one variable, and replacing the part where the common part appears in subsequent programs with that variable. . Thereby, since the overlapping process is not repeated, the size of the program is reduced and the processing time can be shortened.

JP-A-9-198110

  In this conventional optimization method using partial block replacement, since the instruction and device configuration are for the same subexpression, there is a problem that it cannot cope with the case where the instruction configuration is the same but the devices are different. It was. The device here corresponds to a variable in a high-level programming language.

  In the programmable controller, there are cases where a plurality of similar devices are connected, and the output signal is calculated with a combination of logics based on the same input signal. In such a case, exactly the same processing is described by a combination of substantially the same devices, and only a part of the devices of the output destination and input source are different ladder programs. In the conventional optimization method, there is a problem that optimization cannot be performed for such a ladder program because the instruction and the device configuration are targeted for the same sub-expression.

  The present invention has been made to solve the above-described problems. A ladder program that can automatically optimize a ladder program after creation or editing and that can expand the range of optimization. An object is to obtain a program optimization device and an optimization program.

  The ladder program optimizing apparatus according to the present invention provides a device representation for a plurality of circuit blocks having the same instruction configuration and device type in the program analyzed by the ladder program analyzing means and having different device numbers. A program optimization means that checks whether the program size is reduced and processing equivalency is maintained before and after replacement for the replaced program. It is.

  In the ladder program optimizing apparatus of the present invention, the device representation is replaced for a plurality of circuit blocks having the same instruction configuration and device type and different device numbers. The ladder program can be automatically optimized, and the range of optimization can be expanded.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing an application example of a ladder program optimizing device according to Embodiment 1 of the present invention.
A programmable controller 100 shown in FIG. 1 includes a CPU 101 and an I / O 102 and controls the production facility 200, and its operation is described by a ladder program. The CPU 101 is a processor for controlling production equipment by receiving signals from various switches and sensors via the I / O 102 and outputting signals to a motor and a solenoid valve. The I / O 102 is an interface for inputting / outputting signals with the production facility 200.

  The ladder program development device 300 has a function of creating and editing a ladder program executed by the programmable controller 100 and outputting the ladder program to the programmable controller 100. Further, it has a function of taking out a ladder program from the programmable controller 100, and after taking out an existing ladder program stored in the programmable controller 100, it can be edited and written again into the programmable controller 100. The ladder program development device 300 can exchange a ladder program with the ladder program optimization device 400.

  The ladder program optimizing apparatus 400 is an apparatus on which the ladder program optimizing method of the present invention actually operates. The ladder program optimizing apparatus 400 has a function of receiving a ladder program from the ladder program developing apparatus 300, optimizing the ladder program, and then transferring it again to the program developing apparatus. The ladder program development device 300 and the ladder program optimization device 400 may be physically combined on one device.

Next, details of the ladder program optimizing device 400 will be described.
FIG. 2 is a configuration diagram of the ladder program optimizing device according to the first embodiment.
As shown in the figure, the ladder program optimizing device 400 includes a ladder program analyzing unit 401, a program optimizing unit 402, and a ladder program generating unit 403.

  The ladder program analysis unit 401 has a function of converting the input pre-optimization ladder program 501 into a predetermined expression such as an instruction list expression (hereinafter referred to as IL). The program optimizing unit 402 has a function of performing an optimization process on the IL program converted by the ladder program analyzing unit 401. The optimization here includes optimization of a logical condition that eliminates logical redundancy, deletion of useless instructions that delete instructions that are never executed, and optimization by the optimization method of the present invention. Is included.

  The program optimizing unit 402 replaces the device representation for a plurality of circuit blocks having the same device type and device type in the program analyzed by the ladder program analyzing unit 401 and having different device numbers. And a function for confirming whether the program size is reduced for the replaced program and whether processing equivalence is maintained before and after the replacement. The program optimization unit 402 includes a program replacement determination unit 404. The program replacement determination unit 404 reduces the program size of the replaced program, and maintains processing equivalency before and after replacement. A function to check if it is hit is realized.

  That is, the program replacement determination unit 404 has a function of determining whether or not the optimizable portion detected by the program optimization unit 402 should be replaced with an optimization candidate program. For example, for a replacement candidate program, it is determined whether the program size has been reduced or if a problem does not occur due to the replacement of the program. When the program size is reduced and no problem occurs, a determination is made to allow replacement. On the other hand, if the program size is the same or increases, or the program size is reduced, but replacement causes a problem, the replacement of the program is not permitted.

  The ladder program generation unit 403 is a unit that generates a ladder program based on the program optimized by the program optimization unit 402 and outputs the ladder program as an optimized ladder program 502.

  Such a ladder program optimizing device 400 is realized by a computer, and includes, as hardware, a CPU, a ROM, a RAM, a display device, an input device, a hard disk (not shown), and a program corresponding to each means. ing.

  For example, the CPU uses a ROM and a RAM, reads predetermined programs stored in the hard disk, executes the respective programs, and functions as a ladder program analysis unit 401, a program optimization unit 402, and a ladder program generation unit 403. Realize. The CPU also functions as a program selection unit that optimizes together with the input device and the display device. The display device displays the ladder program before and after optimization. Further, the hard disk functions as a ladder program recording means before and after optimization.

Next, the operation of the first embodiment will be described.
FIG. 3 is an explanatory diagram of the pre-optimization ladder program 501.
FIG. 4 is an explanatory diagram of the optimized ladder program 502.
FIG. 5 is an explanatory diagram showing a part of the analyzed IL program.
The ladder program analysis unit 401 inputs the pre-optimization ladder program 501 shown in FIG. 3 and converts it into an IL program as shown in FIG.

Next, the operation of the program optimization unit 402 will be described.
A circuit block is a minimum unit of a ladder program and indicates a group of input elements and output elements. The program optimizing unit 402 detects a common part among a plurality of circuit blocks from the IL program. The program optimizing means 402 detects a part having the same instruction configuration, the same device type, and a different device number, and replaces it with an expression by an index device. Here, the instruction configuration means the type of instruction (LOAD instruction, AND instruction, etc.) and the arrangement of instructions (alignment such as an OR instruction after the AND instruction).

  The device name means a device name and device number such as “X1” and “M100”. Furthermore, the device type refers to a group of devices whose classification is determined for each purpose of use such as “X”, “Y”, “M”, and the like. The device number refers to a number following an alphabetic character indicating the type of device, such as “X1”, “Y10”, “M100”. A device is uniquely determined by a device type and a device number.

  Here, the index device is a device that modifies the device number. For example, the index device is expressed as “Zn”. Here, n is an integer. The index device is described after the device number. “X0Z1” is an example of a device expression using an index device. When the value of the “Z1” device is 0 (zero), “X0Z1” means “X (0 + 0)” → “X0” device. When the value of the “Z1” device is 1, “X0Z1” means “X (0 + 1)” → “X1” device. In this way, a device that is qualified with an index device can switch the indicated device by changing the value of the index device.

Next, the operation of the program optimization unit 402 will be described in detail using the flowchart of FIG.
The process shown in FIG. 6 and the process of FIG. 7 described later are performed by a program optimization control means (not shown) in the program optimization means 402.

  First, the counter A is added to the first instruction of the first circuit block of the ladder program, and the counter B is added to the first instruction of the next circuit block (step ST101). Next, it is determined whether the instruction and device indicated by the counter A are the same as the instruction and device indicated by the counter B (step ST102). If they are the same, they are registered in the common part list as common parts of the program (step ST103). Then, the counter A and the counter B are advanced so as to indicate the next instruction, respectively (step ST104). Here, the difference flag indicating whether or not the instruction and device indicated by the counter A and the counter B are the same is set to OFF (step ST105).

  Next, it is determined whether the instruction and device indicated by the counter A and the counter B are the same (step ST106). If they are the same, the command and device are additionally registered in the previous common part list as common parts (step ST107). If the counter A or the counter B is at the end of the circuit block, the process proceeds to A (step ST108). The process A is a process of the program replacement determination unit 404, which will be described later. If the counter A or the counter B is not the end of the circuit block, the counter A and the counter B are advanced by one, and each is changed to indicate the next instruction (step ST109). Then, the process returns to step ST106, and it is determined again whether the instructions and devices indicated by the counter A and the counter B are the same.

  If the contents indicated by the counter A and the counter B are different in step ST106, the state of the difference flag is determined (step ST110). If the difference flag is OFF, it is turned ON (step ST111). Next, when the instructions and devices indicated by the counter A and the counter B are the same, different devices are registered in the different device list (step ST112). On the other hand, when the difference flag is ON in step ST110, the process proceeds to the process of the program replacement determination unit 404 described later.

  In step ST102, if the instructions or devices indicated by counter A and counter B are different, counter B is advanced by one so as to indicate the next instruction (step ST113). If the counter B is not the end of the circuit block, the process returns to step ST102 (step ST114). If the counter B is at the end of the circuit block, the counter B is moved to the head of the next circuit block (step ST115). At this time, it is determined whether there is a next circuit block indicated by the counter B (step ST116). If the next circuit block exists, the process returns to step ST102. If the next circuit block does not exist, the counter A is moved to the head of the next circuit block, and the counter B is moved to the head of the next circuit block of the counter A (step ST117). Then, it is determined whether the counter A is the last circuit block (step ST118), and if it is the last circuit block, the process ends. If it is not the last, it returns to step ST102.

In the optimized program shown in FIG. 4, the portion surrounded by “FOR” and “NEXT” is repeatedly executed as many times as specified by the argument of “FOR”. “INC” is an instruction for adding one device value specified by an argument.
Replacement of a program requires addition of “FOR”, “NEXT”, and “INC” instructions, and the replacement does not necessarily reduce the program size. Therefore, in order to determine whether the replacement of the program has the effect of reducing the size of the program and whether the replacement of the program can realize an equivalent process, the determination is performed by the program replacement determination unit 404.
In this example, “FOR” and “NEXT” are used, but it is also possible to convert the expression into a combination of a jump instruction and a label.

FIG. 7 is a flowchart showing processing for different devices in the program optimization unit 402.
First, it is determined whether or not the device types of the different device lists registered in step ST112 of FIG. 6 are the same (step ST301). If the device types are the same, the difference between the device numbers is calculated (step ST302). Next, based on this difference, an index device expression is created (step ST303). The index device expression is an expression of the device shown in FIG. That is, in step ST303, the part of the different device number is replaced with the expression by the index device, and based on the common part list in which the common program is stored, the part is surrounded by a FOR-NEXT statement and looped, thereby the program size. Create a program with reduced Furthermore, this program is registered as an optimized program replacement candidate (step ST304). In step ST301, if the device types of the different devices are different, the process is immediately terminated.

  In this example, the case where there is one device having a different device number is shown. However, when there are a plurality of devices having different device numbers, a different device list is created for each corresponding device. By setting an index device, the program size can be similarly reduced.

  In the past, two circuit blocks were targeted. However, when expanding the range of optimization to three circuit blocks, the two circuit blocks differ from the common part list first as described above. Create a device list. Next, for the third circuit block following the two circuit blocks, it is determined whether there is an instruction configuration common to the common part list. There is a common command configuration, the devices attached to the command are the same, and only the device at the position corresponding to the different device list is different, and the difference in the device number is the difference between the two previous circuit blocks. If it is the same, it is treated as a common part. When the difference between devices is different, it cannot be handled as a common part, and therefore optimization is performed by closing the previous two circuit blocks.

  Further, when the change of the device number is not 1, it can be realized by calculating a difference between the device numbers and replacing the value with a process of adding or subtracting the value of the device in the loop process. In the example after optimization shown in FIG. 4, since the device number is different by one, an INC instruction that adds 1 to the device value is used. For example, when the device value increases by 2, an ADD instruction is used.

Next, the operation of the program replacement determination unit 404 will be described.
FIG. 8 is a flowchart showing the operation of the program replacement determination unit 404.
The program replacement determination unit 404 confirms the effect of replacement of the program optimization control unit in the program optimization unit 402 and determines the validity of replacement. First, the program replacement determination means 404 compares the program size before and after replacement for the programs registered as replacement candidates in step ST304 of FIG. 7 (step ST401). If it is determined that the program size after replacement is small (step ST402), the processing equivalence is checked (step ST403). The equivalence of this process is a process for determining whether the calculation result of the program is different due to the replacement. In addition to the logical equivalence, the equivalence to the change in the timing of the input signal is confirmed. If there is no problem in equivalence (step ST404), the program optimization control means is notified of replacement permission (step ST405). In step ST402, if the program size is not reduced or if there is a problem in equivalence in step ST404, the program optimization control means is notified of no replacement (step ST406).

Next, the process equivalence in step ST403 will be described.
An example of a case where a problem occurs due to program replacement is an interrupt program. Execution of an interrupt program is a function of interrupting a program being executed and executing a program associated with the interrupt condition when a set interrupt condition is satisfied. When the processing of the corresponding interrupt program is completed, the processing returns to the interrupted program and resumes execution from that position.

  Problems caused by the interrupt program occur when the same device is used for the program to be optimized and the interrupt program. Assume that there is a process of repeatedly reading a value of a certain device, performing a logical operation, and assigning it to another device. Here, since there is a common part in the process of the part where the value of a certain device is repeatedly read, it is assumed that the part is bundled as a common partial expression and replaced with another device in order to reduce the size. By this replacement, the processing of the common part is integrated into one device, so that it is not necessary to repeat the same processing, and the size of the program can be reduced.

  However, when a value is written to a device in which the operation results of the common part are aggregated and then the value of the device is rewritten by the interrupt program, a problem occurs because the value of the device storing the operation result changes.

  If a program with such a condition is replaced by optimization, the operation of the program differs before and after optimization depending on the timing of interruption. Therefore, such a program replacement should not be performed. Based on such a viewpoint, the program replacement determination unit 404 suppresses conversion of a program in which such a problem occurs.

  In this way, when the IL program is optimized by the program optimizing unit 402 and the program replacement determining unit 404, the ladder program generating unit 403 generates a ladder program from the optimized IL program.

  As described above, in the first embodiment, the program replacement determination unit 404 that determines the replacement process after the replacement of the program is provided, so that the program can be optimized appropriately. Moreover, the optimization object of a program can be expanded by taking in index device expression. Furthermore, when the program size exceeds the program capacity of the programmable controller 100 due to the addition of the program, there is an effect that the program can be downloaded and executed in a short time without taking time and effort to reduce the program size. In addition, since the program is converted into a smaller program that performs equivalent processing, more processing can be realized in the programmable controller 100 having the same program capacity.

  As described above, according to the ladder program optimizing apparatus of the first embodiment, the ladder program analysis unit that analyzes the ladder program, the configuration of instructions in the program analyzed by the ladder program analysis unit, and the device type are equal. In addition, multiple circuit blocks with different device numbers are handled as common subexpressions by replacing the device representation, and the program size is reduced for the replaced program and processed before and after replacement. Program optimization means for confirming whether the equivalence is maintained, and ladder program generation means for generating a ladder program from the program confirmed by the program optimization means, the ladder program after creation or editing Can be automatically optimized and the scope of optimization It can be large.

Embodiment 2. FIG.
FIG. 9 is a block diagram showing the ladder program analysis means 401 of the second embodiment.
The ladder program analysis unit 401 according to the second embodiment includes a device sort unit 405 and a logic optimization unit 406. The device sort unit 405 has a function of changing the arrangement of devices, and the logic optimization unit 406 has a function of optimizing a logical operation.

  The reduction in program size according to the present invention targets two programs having the same instruction configuration but different device numbers. For this reason, even if a program has a different instruction order, if the instruction order can be changed within a range that guarantees an equivalent operation result, the instruction order is changed to unify the configuration and optimize The target of. By this conversion, it is possible to expand the program size reduction object according to the present invention. Such conversion is performed by the device sort unit 405 and the logic optimization unit 406.

First, the operation of the device sort unit 405 will be described.
When “AND” instructions are consecutive or “OR” instructions are consecutive, the devices used are sorted, for example, in ascending order based on the device number, and the order of the instructions of the program is changed. FIG. 10 shows a sample program before sorting devices, and FIG. 11 shows a program after sorting.

FIG. 12 is a flowchart showing the operation when devices are sorted.
The device sort unit 405 first reads one line of IL converted by the conversion unit (not shown) in the ladder program analysis unit 401 (step ST501). Here, one line is a combination of an instruction and a device. Next, it is determined whether it is the end of the program (step ST502). In the case of termination, the process is terminated. If not the end, it is determined whether the instruction of the read IL program is an AND instruction (step ST503). In the case of the AND instruction, the instruction is read as long as the AND instruction continues for the subsequent program, and the corresponding device is registered (step ST504). If the subsequent instruction is no longer an AND instruction, the registered devices are rearranged in ascending order, for example, and the original program is changed (step ST505).

  If it is not an AND instruction in step ST503, it is determined whether it is an OR instruction (step ST506). If the subsequent instruction is an OR instruction, the instruction is read as long as the OR instruction continues, and the corresponding device is registered (step ST507). If the subsequent instruction is no longer an OR instruction, the registered devices are rearranged in ascending order, for example, and the original program is changed (step ST508).

  Further, in step ST504 to step ST505 and step ST507 to step ST508, sorting is performed even in a unit of processing that is a unit when operating the stack at the time of execution connected by ANB or ORB. As an example of sorting criteria at this time, there is a method of sorting the smallest device number in the set as the set number. When a plurality of device types coexist, there is a method in which the device types are first arranged in alphabetical order and then sorted based on device numbers.

Next, the operation of the logic optimization unit 406 will be described.
When expressed by a combination of an “AND” instruction and an “OR” instruction, it can be converted into a program that generates an equivalent operation result by switching the order of the instruction and the device corresponding to the instruction. In particular, the number of steps of the ladder program to be generated can be reduced by changing the order of the devices corresponding to the instructions so that the stack operation is optimized. Examples of this are shown in FIGS.

FIG. 13 shows a ladder program before the order of instructions is changed. The size of this program is 38 steps. In this ladder program, an ANB instruction is entered. This ANB instruction is an instruction that takes the logical product of the top element of the stack and the next element. By changing the order of the stack operations by changing the order of the instructions of the program, the number of instructions can be reduced.
FIG. 14 shows a ladder program in which ANB instructions are reduced by logic optimization. By changing the order of the instructions, the number of steps is reduced to 36 steps.

  By rearranging the order of the instructions of the program in such a way as to reduce the number of instructions, the order of the instructions in the program can be made uniform. For this reason, a plurality of circuit blocks that cannot be recognized as common parts as they are can be recognized by rearrangement based on the reduction of the program size, and the optimization target can be expanded.

  These program changes can be performed by the ladder program analysis unit 401 or can be performed by the program optimization unit 402 before the program is replaced. That is, the device sort unit 405 and the logic optimization unit 406 may be provided in either the ladder program analysis unit 401 or the program optimization unit 402.

  As described above, according to the ladder program optimizing apparatus of the second embodiment, the device sort unit for replacing the device sequence is provided, and the program optimization unit is a program in which the device sequence is replaced by the device sort unit. Since the device representation is replaced, the application target of the optimization process can be expanded, and as a result, the size of the program can be further reduced.

Embodiment 3 FIG.
FIG. 15 is a configuration diagram of the program optimization unit 402a according to the third embodiment.
The program optimization unit 402a according to the third embodiment includes a device conversion unit 407 and a program replacement determination unit 404a. The program optimization unit 402a optimizes the input IL program 503 and outputs an optimized IL program 504. It is. The device conversion means 407 is means for replacing a device appearing in the program with another device. In this device replacement, the name of the device is replaced so that the optimization method according to the present invention can be applied. That is, at least one of the device type and the device number constituting the device name is replaced. The program replacement determination unit 404a performs replacement determination on the program whose device has been replaced by the device conversion unit 407. The processing of the replacement determination itself is the same as that of the program replacement determination unit 404 of the first embodiment. is there.

  In the first embodiment, in step ST301 and step ST302 in FIG. 7, the device type is determined, and the difference between the devices is calculated. In the third embodiment, when the device type is different by the device conversion unit 407, the device type is unified by replacing the device, and the optimization method according to the present invention is applied. Furthermore, the device names are replaced so that the optimization method according to the present invention is applied to three or more circuit blocks.

  To replace the device name, there are a method of replacing the corresponding device over the entire program, and a method of replacing the device only before and after the portion to be optimized. In the replacement method over the entire program, the device name is replaced over the entire program. Therefore, replacement must be performed within a range in which it is guaranteed that the operation of the entire program does not change. Therefore, a device directly connected to an input or output signal cannot be a target for such replacement. An input / output device that does not directly affect an input / output target or a device used for calculation in the programmable controller 100 is a target.

  On the other hand, the method of replacing a device only before and after the portion to be optimized limits the range affected by the replacement, and thus can handle devices that affect input / output. However, it is necessary to substitute the device value into the device for optimization so that optimization can be performed before the optimization point. In addition, if there is a write process for the device at the optimization location and the device value may change, it is necessary to substitute the value from the device to the original device after the optimization location. There is. As described above, in the method of replacing the device only before and after the portion to be optimized, it is necessary to add a process for transferring the value of the device, so that the program size becomes large. When replacing a program, replacement determination is performed in consideration of the additional program size.

16 and 17 are explanatory diagrams showing a ladder program before device conversion and a ladder program optimized by performing device conversion.
In the program example shown in FIG. 16, the portion “X8” is “X9”, unlike the ladder program shown in FIG. For this reason, it is not possible to optimize the ladder program as shown in FIG. Therefore, the device conversion unit 407 replaces the problem “X9” device with “X8”. These devices can be replaced because the device type is “X”.

  Specifically, the replacement is performed as shown in the second line of FIG. This means that the value of “X9” is substituted for “X8”, and the following two conditions are necessary for such replacement. The program replacement determination unit 404a outputs a determination result that can be replaced only when the following conditions are satisfied.

(1) The optimization effect can be obtained even when the increase in program size due to the addition of replacement is taken into account. In this example, the addition of the second row increases two steps. However, it was 39 steps before the optimization, but after the optimization, 25 + 2 = 27 steps (as described in the first embodiment, it is optimized to 25 steps. There is an optimization effect.
(2) The replacement device is not used in other parts of the program In this example, it is necessary that the “X8” device is not used in other parts of the program.

  In this example, only the device number is replaced for the X device, but it is also possible to replace the device type as necessary, such as replacing the X device with the M device. However, the Y device is not specified as the replacement destination. That is, the Y device is a device used for output, and if a certain Y device (for example, Y10) is designated as the replacement destination just because it is not used in the program, a value is substituted for that Y device, This is because a signal is output to the outside.

  As described above, according to the ladder program optimizing apparatus of the third embodiment, the device conversion unit that replaces at least one of the device type and the device number is provided, and the program optimization unit determines whether the device type is the device type. Since the device representation is replaced with the program in which at least one of the device numbers is replaced, the optimization target can be further expanded, and as a result, the optimization efficiency of the entire program can be further improved.

Embodiment 4 FIG.
In the fourth embodiment, after the loop is formed, the common portion is bundled out of the loop.
FIG. 18 is a configuration diagram of the program optimization unit 402b according to the fourth embodiment.
The program optimization unit 402b of the fourth embodiment includes an out-of-loop movement unit 408 and a program replacement determination unit 404b, performs optimization on the input IL program 503, and outputs an optimized IL program 504a. It is. The out-of-loop moving unit 408 is a unit that moves a portion that is not related to the loop processing out of the loop among the portions that are looped by the program optimization control unit (not shown) in the program optimization unit 402b. The program replacement determination unit 404b is a unit that performs replacement determination on the program processed by the out-of-loop moving unit 408, and the processing of the replacement determination itself is the same as the program replacement determination unit 404 of the first embodiment. .

FIG. 19 is an explanatory diagram showing a ladder program before moving the common part out of the loop.
In this figure, the portion within the broken line frame 510 is a process performed every time in the loop, and the same calculation result can be obtained and the processing time can be shortened even if the part goes out of the loop. For this reason, the outside-loop moving means 408 substitutes the calculation result of that portion into another device, and changes so as to refer to that device in the loop.
FIG. 20 is an explanatory diagram showing the result of moving the common part of FIG. 19 out of the loop.
The ladder program shown in FIG. 19 has 36 steps, whereas the ladder program shown in FIG. 20 reduces to 35 steps.

The movement out of the loop is performed with respect to a portion common to a plurality of circuit blocks extracted in step ST107 in FIG. In this common part, a value that changes every time a loop is executed is not used, and a combination of an instruction and a device irrelevant to the loop is detected and moved out of the loop. The relationship between the loop, the instruction, and the device is determined based on whether the device depends on the number of loops in the loop. In addition, a device that depends on the value of a device that depends on the number of loops is also excluded from being moved out of the loop as a device related to the loop.
By moving processing irrelevant to the loop in this way, it is possible to reduce the program execution time while reducing the program size.

  As described above, in the fourth embodiment, the same processing is looped and unified, so that readability can be improved. In addition, in the case of an operation in which the part to be changed is described repeatedly, it is necessary to change the same number of parts as the number of repetitions, but by making the loop into a loop, the changed parts can be combined into one place, There is an effect that the maintainability is improved.

  As described above, according to the ladder program optimizing apparatus of the fourth embodiment, the program optimizing unit performs processing irrelevant to the loop outside the loop with respect to the program replaced with the loop processing by replacing the device expression. Therefore, it is possible to reduce the program execution time while reducing the size of the program.

  Further, according to the optimization program of the present invention, the computer that performs the optimization process on the ladder program is caused to function as any one of the ladder program optimization devices in the first to fourth embodiments. Therefore, the ladder program optimizing device that exhibits the effects of any one of the first to fourth embodiments can be realized on a computer.

It is a block diagram which shows the example of application of the ladder program optimization apparatus by Embodiment 1 of this invention. It is a block diagram of the ladder program optimization apparatus by Embodiment 1 of this invention. It is explanatory drawing of the ladder program before optimization of the ladder program optimizing device by Embodiment 1 of this invention. It is explanatory drawing of the ladder program after optimization of the ladder program optimizing device by Embodiment 1 of this invention. It is explanatory drawing of the IL program after the analysis of the ladder program optimizing device by Embodiment 1 of this invention. It is a flowchart which shows operation | movement of the ladder program optimization apparatus by Embodiment 1 of this invention. It is a flowchart which shows the process with respect to a different device of the ladder program optimization apparatus by Embodiment 1 of this invention. It is a flowchart which shows operation | movement of the program replacement determination means of the ladder program optimization apparatus by Embodiment 1 of this invention. It is a block diagram which shows the ladder program analysis means of the ladder program optimization apparatus by Embodiment 2 of this invention. It is explanatory drawing of the sample program before the sort in Embodiment 2 of this invention. It is explanatory drawing of the sample program after the sort in Embodiment 2 of this invention. It is a flowchart which shows the operation | movement at the time of the device sort in Embodiment 2 of this invention. It is explanatory drawing of the ladder program before changing the order of the instruction | indication in Embodiment 2 of this invention. It is explanatory drawing of the ladder program after changing the order of the instruction | indication in Embodiment 2 of this invention. It is a block diagram which shows the program optimization means of the ladder program optimization apparatus by Embodiment 3 of this invention. It is explanatory drawing which shows the ladder program before the device conversion in Embodiment 3 of this invention. It is explanatory drawing which shows the ladder program after the device conversion in Embodiment 3 of this invention. It is a block diagram which shows the program optimization means of the ladder program optimization apparatus by Embodiment 4 of this invention. It is explanatory drawing which shows the ladder program before moving the common part in Embodiment 4 of this invention out of a loop. It is explanatory drawing which shows the ladder program after moving the common part in Embodiment 4 of this invention out of a loop.

Explanation of symbols

  400 ladder program optimization device, 401 ladder program analysis means, 402, 402a, 402b program optimization means, 403 ladder program generation means, 404, 404a, 404b program replacement judgment means, 405 device sort means, 406 logic optimization means, 407 Device conversion means, 501 ladder program before optimization, 502 ladder program after optimization, 503 IL program, 504, 504a IL program after optimization.

Claims (5)

Ladder program analysis means for analyzing the ladder program;
For a plurality of circuit blocks having the same instruction configuration and device type in the program analyzed by the ladder program analysis means and having different device numbers, treat them as common sub-expressions by replacing the device representation. A program optimizing means for confirming whether the program size is reduced for the replaced program and whether processing equivalence is maintained before and after the replacement;
A ladder program optimizing device comprising: ladder program generating means for generating a ladder program from a program confirmed by the program optimizing means. Device sort means to replace the device list,
2. The ladder program optimizing apparatus according to claim 1, wherein the program optimizing unit replaces the representation of the device with respect to the program in which the device arrangement is replaced by the device sort unit. Device conversion means for replacing at least one of the device type and device number,
3. The ladder program optimization according to claim 1, wherein the program optimization unit replaces the representation of the device with respect to the program in which at least one of the device type and the device number is replaced by the device conversion unit. Device   The program optimization means moves a process irrelevant to the loop out of the loop with respect to the program replaced with the loop process by replacing the device expression. The ladder program optimizing device according to any one of the preceding claims.   An optimization program for causing a computer that performs optimization processing on a ladder program to function as the ladder program optimization device according to any one of claims 1 to 4.

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